1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 /* 7 * mpc8313epb board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_E300 1 17 #define CONFIG_MPC831x 1 18 #define CONFIG_MPC8313 1 19 #define CONFIG_MPC8313ERDB 1 20 21 #ifdef CONFIG_NAND 22 #define CONFIG_SPL_INIT_MINIMAL 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 25 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 26 27 #ifdef CONFIG_SPL_BUILD 28 #define CONFIG_NS16550_MIN_FUNCTIONS 29 #endif 30 31 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 32 #define CONFIG_SPL_MAX_SIZE (4 * 1024) 33 #define CONFIG_SPL_PAD_TO 0x4000 34 35 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 36 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 37 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 38 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 39 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 40 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 41 42 #ifdef CONFIG_SPL_BUILD 43 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 44 #endif 45 46 #endif /* CONFIG_NAND */ 47 48 #ifndef CONFIG_SYS_MONITOR_BASE 49 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 50 #endif 51 52 #define CONFIG_PCI_INDIRECT_BRIDGE 53 #define CONFIG_FSL_ELBC 1 54 55 #define CONFIG_MISC_INIT_R 56 57 /* 58 * On-board devices 59 * 60 * TSEC1 is VSC switch 61 * TSEC2 is SoC TSEC 62 */ 63 #define CONFIG_VSC7385_ENET 64 #define CONFIG_TSEC2 65 66 #ifdef CONFIG_SYS_66MHZ 67 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 68 #elif defined(CONFIG_SYS_33MHZ) 69 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 70 #else 71 #error Unknown oscillator frequency. 72 #endif 73 74 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 75 76 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */ 77 78 #define CONFIG_SYS_IMMR 0xE0000000 79 80 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) 81 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 82 #endif 83 84 #define CONFIG_SYS_MEMTEST_START 0x00001000 85 #define CONFIG_SYS_MEMTEST_END 0x07f00000 86 87 /* Early revs of this board will lock up hard when attempting 88 * to access the PMC registers, unless a JTAG debugger is 89 * connected, or some resistor modifications are made. 90 */ 91 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 92 93 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 94 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 95 96 /* 97 * Device configurations 98 */ 99 100 /* Vitesse 7385 */ 101 102 #ifdef CONFIG_VSC7385_ENET 103 104 #define CONFIG_TSEC1 105 106 /* The flash address and size of the VSC7385 firmware image */ 107 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 108 #define CONFIG_VSC7385_IMAGE_SIZE 8192 109 110 #endif 111 112 /* 113 * DDR Setup 114 */ 115 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 116 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 117 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 118 119 /* 120 * Manually set up DDR parameters, as this board does not 121 * seem to have the SPD connected to I2C. 122 */ 123 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 124 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 125 | CSCONFIG_ODT_RD_NEVER \ 126 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 127 | CSCONFIG_ROW_BIT_13 \ 128 | CSCONFIG_COL_BIT_10) 129 /* 0x80010102 */ 130 131 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 132 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 133 | (0 << TIMING_CFG0_WRT_SHIFT) \ 134 | (0 << TIMING_CFG0_RRT_SHIFT) \ 135 | (0 << TIMING_CFG0_WWT_SHIFT) \ 136 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 137 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 138 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 139 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 140 /* 0x00220802 */ 141 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 142 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 143 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 144 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 145 | (10 << TIMING_CFG1_REFREC_SHIFT) \ 146 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 147 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 148 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 149 /* 0x3835a322 */ 150 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 151 | (5 << TIMING_CFG2_CPO_SHIFT) \ 152 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 153 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 154 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 155 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 156 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 157 /* 0x129048c6 */ /* P9-45,may need tuning */ 158 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 159 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 160 /* 0x05100500 */ 161 #if defined(CONFIG_DDR_2T_TIMING) 162 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 163 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 164 | SDRAM_CFG_DBW_32 \ 165 | SDRAM_CFG_2T_EN) 166 /* 0x43088000 */ 167 #else 168 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 169 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 170 | SDRAM_CFG_DBW_32) 171 /* 0x43080000 */ 172 #endif 173 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 174 /* set burst length to 8 for 32-bit data path */ 175 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 176 | (0x0632 << SDRAM_MODE_SD_SHIFT)) 177 /* 0x44480632 */ 178 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 179 180 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 181 /*0x02000000*/ 182 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 183 | DDRCDR_PZ_NOMZ \ 184 | DDRCDR_NZ_NOMZ \ 185 | DDRCDR_M_ODR) 186 187 /* 188 * FLASH on the Local Bus 189 */ 190 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 191 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 192 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 193 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 194 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 195 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 196 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 197 198 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 199 | BR_PS_16 /* 16 bit port */ \ 200 | BR_MS_GPCM /* MSEL = GPCM */ \ 201 | BR_V) /* valid */ 202 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 203 | OR_GPCM_XACS \ 204 | OR_GPCM_SCY_9 \ 205 | OR_GPCM_EHTR \ 206 | OR_GPCM_EAD) 207 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 208 /* window base at flash base */ 209 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 210 /* 16 MB window size */ 211 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 212 213 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 214 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 215 216 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 217 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 218 219 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 220 !defined(CONFIG_SPL_BUILD) 221 #define CONFIG_SYS_RAMBOOT 222 #endif 223 224 #define CONFIG_SYS_INIT_RAM_LOCK 1 225 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 226 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 227 228 #define CONFIG_SYS_GBL_DATA_OFFSET \ 229 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 230 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 231 232 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 233 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 234 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 235 236 /* 237 * Local Bus LCRR and LBCR regs 238 */ 239 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 240 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 241 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 242 | (0xFF << LBCR_BMT_SHIFT) \ 243 | 0xF) /* 0x0004ff0f */ 244 245 /* LB refresh timer prescal, 266MHz/32 */ 246 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 247 248 /* drivers/mtd/nand/nand.c */ 249 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) 250 #define CONFIG_SYS_NAND_BASE 0xFFF00000 251 #else 252 #define CONFIG_SYS_NAND_BASE 0xE2800000 253 #endif 254 255 #define CONFIG_MTD_DEVICE 256 #define CONFIG_MTD_PARTITION 257 258 #define CONFIG_SYS_MAX_NAND_DEVICE 1 259 #define CONFIG_NAND_FSL_ELBC 1 260 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 261 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 262 263 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 264 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 265 | BR_PS_8 /* 8 bit port */ \ 266 | BR_MS_FCM /* MSEL = FCM */ \ 267 | BR_V) /* valid */ 268 #define CONFIG_SYS_NAND_OR_PRELIM \ 269 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 270 | OR_FCM_CSCT \ 271 | OR_FCM_CST \ 272 | OR_FCM_CHT \ 273 | OR_FCM_SCY_1 \ 274 | OR_FCM_TRLX \ 275 | OR_FCM_EHTR) 276 /* 0xFFFF8396 */ 277 278 #ifdef CONFIG_NAND 279 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 280 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 281 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 282 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 283 #else 284 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 285 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 286 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 287 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 288 #endif 289 290 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 291 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 292 293 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 294 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 295 296 /* local bus write LED / read status buffer (BCSR) mapping */ 297 #define CONFIG_SYS_BCSR_ADDR 0xFA000000 298 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 299 /* map at 0xFA000000 on LCS3 */ 300 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 301 | BR_PS_8 /* 8 bit port */ \ 302 | BR_MS_GPCM /* MSEL = GPCM */ \ 303 | BR_V) /* valid */ 304 /* 0xFA000801 */ 305 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 306 | OR_GPCM_CSNT \ 307 | OR_GPCM_ACS_DIV2 \ 308 | OR_GPCM_XACS \ 309 | OR_GPCM_SCY_15 \ 310 | OR_GPCM_TRLX_SET \ 311 | OR_GPCM_EHTR_SET \ 312 | OR_GPCM_EAD) 313 /* 0xFFFF8FF7 */ 314 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 315 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 316 317 /* Vitesse 7385 */ 318 319 #ifdef CONFIG_VSC7385_ENET 320 321 /* VSC7385 Base address on LCS2 */ 322 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 323 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 324 325 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 326 | BR_PS_8 /* 8 bit port */ \ 327 | BR_MS_GPCM /* MSEL = GPCM */ \ 328 | BR_V) /* valid */ 329 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 330 | OR_GPCM_CSNT \ 331 | OR_GPCM_XACS \ 332 | OR_GPCM_SCY_15 \ 333 | OR_GPCM_SETA \ 334 | OR_GPCM_TRLX_SET \ 335 | OR_GPCM_EHTR_SET \ 336 | OR_GPCM_EAD) 337 /* 0xFFFE09FF */ 338 339 /* Access window base at VSC7385 base */ 340 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 341 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 342 343 #endif 344 345 #define CONFIG_MPC83XX_GPIO 1 346 347 /* 348 * Serial Port 349 */ 350 #define CONFIG_SYS_NS16550_SERIAL 351 #define CONFIG_SYS_NS16550_REG_SIZE 1 352 353 #define CONFIG_SYS_BAUDRATE_TABLE \ 354 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 355 356 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 357 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 358 359 /* I2C */ 360 #define CONFIG_SYS_I2C 361 #define CONFIG_SYS_I2C_FSL 362 #define CONFIG_SYS_FSL_I2C_SPEED 400000 363 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 364 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 365 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 366 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 367 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 368 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 369 370 /* 371 * General PCI 372 * Addresses are mapped 1-1. 373 */ 374 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 375 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 376 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 377 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 378 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 379 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 380 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 381 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 382 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 383 384 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 385 386 /* 387 * TSEC 388 */ 389 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 390 391 #define CONFIG_GMII /* MII PHY management */ 392 393 #ifdef CONFIG_TSEC1 394 #define CONFIG_HAS_ETH0 395 #define CONFIG_TSEC1_NAME "TSEC0" 396 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 397 #define TSEC1_PHY_ADDR 0x1c 398 #define TSEC1_FLAGS TSEC_GIGABIT 399 #define TSEC1_PHYIDX 0 400 #endif 401 402 #ifdef CONFIG_TSEC2 403 #define CONFIG_HAS_ETH1 404 #define CONFIG_TSEC2_NAME "TSEC1" 405 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 406 #define TSEC2_PHY_ADDR 4 407 #define TSEC2_FLAGS TSEC_GIGABIT 408 #define TSEC2_PHYIDX 0 409 #endif 410 411 /* Options are: TSEC[0-1] */ 412 #define CONFIG_ETHPRIME "TSEC1" 413 414 /* 415 * Configure on-board RTC 416 */ 417 #define CONFIG_RTC_DS1337 418 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 419 420 /* 421 * Environment 422 */ 423 #if defined(CONFIG_NAND) 424 #define CONFIG_ENV_OFFSET (512 * 1024) 425 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 426 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 427 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 428 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 429 #define CONFIG_ENV_OFFSET_REDUND \ 430 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 431 #elif !defined(CONFIG_SYS_RAMBOOT) 432 #define CONFIG_ENV_ADDR \ 433 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 434 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 435 #define CONFIG_ENV_SIZE 0x2000 436 437 /* Address and size of Redundant Environment Sector */ 438 #else 439 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 440 #define CONFIG_ENV_SIZE 0x2000 441 #endif 442 443 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 444 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 445 446 /* 447 * BOOTP options 448 */ 449 #define CONFIG_BOOTP_BOOTFILESIZE 450 451 /* 452 * Command line configuration. 453 */ 454 455 /* 456 * Miscellaneous configurable options 457 */ 458 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 459 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 460 461 /* Boot Argument Buffer Size */ 462 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 463 464 /* 465 * For booting Linux, the board info and command line data 466 * have to be in the first 256 MB of memory, since this is 467 * the maximum mapped by the Linux kernel during initialization. 468 */ 469 /* Initial Memory map for Linux*/ 470 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 471 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 472 473 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 474 475 #ifdef CONFIG_SYS_66MHZ 476 477 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 478 /* 0x62040000 */ 479 #define CONFIG_SYS_HRCW_LOW (\ 480 0x20000000 /* reserved, must be set */ |\ 481 HRCWL_DDRCM |\ 482 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 483 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 484 HRCWL_CSB_TO_CLKIN_2X1 |\ 485 HRCWL_CORE_TO_CSB_2X1) 486 487 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 488 489 #elif defined(CONFIG_SYS_33MHZ) 490 491 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 492 /* 0x65040000 */ 493 #define CONFIG_SYS_HRCW_LOW (\ 494 0x20000000 /* reserved, must be set */ |\ 495 HRCWL_DDRCM |\ 496 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 497 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 498 HRCWL_CSB_TO_CLKIN_5X1 |\ 499 HRCWL_CORE_TO_CSB_2X1) 500 501 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 502 503 #endif 504 505 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 506 HRCWH_PCI_HOST |\ 507 HRCWH_PCI1_ARBITER_ENABLE |\ 508 HRCWH_CORE_ENABLE |\ 509 HRCWH_BOOTSEQ_DISABLE |\ 510 HRCWH_SW_WATCHDOG_DISABLE |\ 511 HRCWH_TSEC1M_IN_RGMII |\ 512 HRCWH_TSEC2M_IN_RGMII |\ 513 HRCWH_BIG_ENDIAN) 514 515 #ifdef CONFIG_NAND 516 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 517 HRCWH_FROM_0XFFF00100 |\ 518 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 519 HRCWH_RL_EXT_NAND) 520 #else 521 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 522 HRCWH_FROM_0X00000100 |\ 523 HRCWH_ROM_LOC_LOCAL_16BIT |\ 524 HRCWH_RL_EXT_LEGACY) 525 #endif 526 527 /* System IO Config */ 528 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 529 /* Enable Internal USB Phy and GPIO on LCD Connector */ 530 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 531 532 #define CONFIG_SYS_HID0_INIT 0x000000000 533 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 534 HID0_ENABLE_INSTRUCTION_CACHE | \ 535 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 536 537 #define CONFIG_SYS_HID2 HID2_HBE 538 539 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 540 541 /* DDR @ 0x00000000 */ 542 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 543 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 544 | BATU_BL_256M \ 545 | BATU_VS \ 546 | BATU_VP) 547 548 /* PCI @ 0x80000000 */ 549 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 550 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 551 | BATU_BL_256M \ 552 | BATU_VS \ 553 | BATU_VP) 554 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 555 | BATL_PP_RW \ 556 | BATL_CACHEINHIBIT \ 557 | BATL_GUARDEDSTORAGE) 558 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 559 | BATU_BL_256M \ 560 | BATU_VS \ 561 | BATU_VP) 562 563 /* PCI2 not supported on 8313 */ 564 #define CONFIG_SYS_IBAT3L (0) 565 #define CONFIG_SYS_IBAT3U (0) 566 #define CONFIG_SYS_IBAT4L (0) 567 #define CONFIG_SYS_IBAT4U (0) 568 569 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 570 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 571 | BATL_PP_RW \ 572 | BATL_CACHEINHIBIT \ 573 | BATL_GUARDEDSTORAGE) 574 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 575 | BATU_BL_256M \ 576 | BATU_VS \ 577 | BATU_VP) 578 579 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 580 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 581 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 582 583 #define CONFIG_SYS_IBAT7L (0) 584 #define CONFIG_SYS_IBAT7U (0) 585 586 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 587 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 588 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 589 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 590 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 591 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 592 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 593 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 594 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 595 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 596 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 597 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 598 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 599 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 600 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 601 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 602 603 /* 604 * Environment Configuration 605 */ 606 #define CONFIG_ENV_OVERWRITE 607 608 #define CONFIG_NETDEV "eth1" 609 610 #define CONFIG_HOSTNAME mpc8313erdb 611 #define CONFIG_ROOTPATH "/nfs/root/path" 612 #define CONFIG_BOOTFILE "uImage" 613 /* U-Boot image on TFTP server */ 614 #define CONFIG_UBOOTPATH "u-boot.bin" 615 #define CONFIG_FDTFILE "mpc8313erdb.dtb" 616 617 /* default location for tftp and bootm */ 618 #define CONFIG_LOADADDR 800000 619 620 #define CONFIG_EXTRA_ENV_SETTINGS \ 621 "netdev=" CONFIG_NETDEV "\0" \ 622 "ethprime=TSEC1\0" \ 623 "uboot=" CONFIG_UBOOTPATH "\0" \ 624 "tftpflash=tftpboot $loadaddr $uboot; " \ 625 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 626 " +$filesize; " \ 627 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 628 " +$filesize; " \ 629 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 630 " $filesize; " \ 631 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 632 " +$filesize; " \ 633 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 634 " $filesize\0" \ 635 "fdtaddr=780000\0" \ 636 "fdtfile=" CONFIG_FDTFILE "\0" \ 637 "console=ttyS0\0" \ 638 "setbootargs=setenv bootargs " \ 639 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 640 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 641 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 642 "$netdev:off " \ 643 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 644 645 #define CONFIG_NFSBOOTCOMMAND \ 646 "setenv rootdev /dev/nfs;" \ 647 "run setbootargs;" \ 648 "run setipargs;" \ 649 "tftp $loadaddr $bootfile;" \ 650 "tftp $fdtaddr $fdtfile;" \ 651 "bootm $loadaddr - $fdtaddr" 652 653 #define CONFIG_RAMBOOTCOMMAND \ 654 "setenv rootdev /dev/ram;" \ 655 "run setbootargs;" \ 656 "tftp $ramdiskaddr $ramdiskfile;" \ 657 "tftp $loadaddr $bootfile;" \ 658 "tftp $fdtaddr $fdtfile;" \ 659 "bootm $loadaddr $ramdiskaddr $fdtaddr" 660 661 #endif /* __CONFIG_H */ 662