1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 /* 7 * mpc8313epb board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 /* 16 * High Level Configuration Options 17 */ 18 #define CONFIG_E300 1 19 #define CONFIG_MPC831x 1 20 #define CONFIG_MPC8313 1 21 #define CONFIG_MPC8313ERDB 1 22 23 #ifdef CONFIG_NAND 24 #define CONFIG_SPL_INIT_MINIMAL 25 #define CONFIG_SPL_SERIAL_SUPPORT 26 #define CONFIG_SPL_NAND_SUPPORT 27 #define CONFIG_SPL_FLUSH_IMAGE 28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 29 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 30 31 #ifdef CONFIG_SPL_BUILD 32 #define CONFIG_NS16550_MIN_FUNCTIONS 33 #endif 34 35 #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 36 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 37 #define CONFIG_SPL_MAX_SIZE (4 * 1024) 38 #define CONFIG_SPL_PAD_TO 0x4000 39 40 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 41 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 42 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 43 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 44 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 45 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 46 47 #ifdef CONFIG_SPL_BUILD 48 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 49 #endif 50 51 #endif /* CONFIG_NAND */ 52 53 #ifndef CONFIG_SYS_TEXT_BASE 54 #define CONFIG_SYS_TEXT_BASE 0xFE000000 55 #endif 56 57 #ifndef CONFIG_SYS_MONITOR_BASE 58 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 59 #endif 60 61 #define CONFIG_PCI 62 #define CONFIG_PCI_INDIRECT_BRIDGE 63 #define CONFIG_FSL_ELBC 1 64 65 #define CONFIG_MISC_INIT_R 66 67 /* 68 * On-board devices 69 * 70 * TSEC1 is VSC switch 71 * TSEC2 is SoC TSEC 72 */ 73 #define CONFIG_VSC7385_ENET 74 #define CONFIG_TSEC2 75 76 #ifdef CONFIG_SYS_66MHZ 77 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 78 #elif defined(CONFIG_SYS_33MHZ) 79 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 80 #else 81 #error Unknown oscillator frequency. 82 #endif 83 84 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 85 86 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ 87 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */ 88 89 #define CONFIG_SYS_IMMR 0xE0000000 90 91 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) 92 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 93 #endif 94 95 #define CONFIG_SYS_MEMTEST_START 0x00001000 96 #define CONFIG_SYS_MEMTEST_END 0x07f00000 97 98 /* Early revs of this board will lock up hard when attempting 99 * to access the PMC registers, unless a JTAG debugger is 100 * connected, or some resistor modifications are made. 101 */ 102 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 103 104 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 105 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 106 107 /* 108 * Device configurations 109 */ 110 111 /* Vitesse 7385 */ 112 113 #ifdef CONFIG_VSC7385_ENET 114 115 #define CONFIG_TSEC1 116 117 /* The flash address and size of the VSC7385 firmware image */ 118 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 119 #define CONFIG_VSC7385_IMAGE_SIZE 8192 120 121 #endif 122 123 /* 124 * DDR Setup 125 */ 126 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 127 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 128 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 129 130 /* 131 * Manually set up DDR parameters, as this board does not 132 * seem to have the SPD connected to I2C. 133 */ 134 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 135 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 136 | CSCONFIG_ODT_RD_NEVER \ 137 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 138 | CSCONFIG_ROW_BIT_13 \ 139 | CSCONFIG_COL_BIT_10) 140 /* 0x80010102 */ 141 142 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 143 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 144 | (0 << TIMING_CFG0_WRT_SHIFT) \ 145 | (0 << TIMING_CFG0_RRT_SHIFT) \ 146 | (0 << TIMING_CFG0_WWT_SHIFT) \ 147 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 148 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 149 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 150 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 151 /* 0x00220802 */ 152 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 153 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 154 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 155 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 156 | (10 << TIMING_CFG1_REFREC_SHIFT) \ 157 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 158 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 159 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 160 /* 0x3835a322 */ 161 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 162 | (5 << TIMING_CFG2_CPO_SHIFT) \ 163 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 164 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 165 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 166 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 167 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 168 /* 0x129048c6 */ /* P9-45,may need tuning */ 169 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 170 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 171 /* 0x05100500 */ 172 #if defined(CONFIG_DDR_2T_TIMING) 173 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 174 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 175 | SDRAM_CFG_DBW_32 \ 176 | SDRAM_CFG_2T_EN) 177 /* 0x43088000 */ 178 #else 179 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 180 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 181 | SDRAM_CFG_DBW_32) 182 /* 0x43080000 */ 183 #endif 184 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 185 /* set burst length to 8 for 32-bit data path */ 186 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 187 | (0x0632 << SDRAM_MODE_SD_SHIFT)) 188 /* 0x44480632 */ 189 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 190 191 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 192 /*0x02000000*/ 193 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 194 | DDRCDR_PZ_NOMZ \ 195 | DDRCDR_NZ_NOMZ \ 196 | DDRCDR_M_ODR) 197 198 /* 199 * FLASH on the Local Bus 200 */ 201 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 202 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 203 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 204 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 205 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 206 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 207 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 208 209 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 210 | BR_PS_16 /* 16 bit port */ \ 211 | BR_MS_GPCM /* MSEL = GPCM */ \ 212 | BR_V) /* valid */ 213 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 214 | OR_GPCM_XACS \ 215 | OR_GPCM_SCY_9 \ 216 | OR_GPCM_EHTR \ 217 | OR_GPCM_EAD) 218 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 219 /* window base at flash base */ 220 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 221 /* 16 MB window size */ 222 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 223 224 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 225 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 226 227 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 228 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 229 230 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 231 !defined(CONFIG_SPL_BUILD) 232 #define CONFIG_SYS_RAMBOOT 233 #endif 234 235 #define CONFIG_SYS_INIT_RAM_LOCK 1 236 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 237 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 238 239 #define CONFIG_SYS_GBL_DATA_OFFSET \ 240 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 241 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 242 243 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 244 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 245 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 246 247 /* 248 * Local Bus LCRR and LBCR regs 249 */ 250 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 251 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 252 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 253 | (0xFF << LBCR_BMT_SHIFT) \ 254 | 0xF) /* 0x0004ff0f */ 255 256 /* LB refresh timer prescal, 266MHz/32 */ 257 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 258 259 /* drivers/mtd/nand/nand.c */ 260 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) 261 #define CONFIG_SYS_NAND_BASE 0xFFF00000 262 #else 263 #define CONFIG_SYS_NAND_BASE 0xE2800000 264 #endif 265 266 #define CONFIG_MTD_DEVICE 267 #define CONFIG_MTD_PARTITION 268 #define CONFIG_CMD_MTDPARTS 269 #define MTDIDS_DEFAULT "nand0=e2800000.flash" 270 #define MTDPARTS_DEFAULT \ 271 "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" 272 273 #define CONFIG_SYS_MAX_NAND_DEVICE 1 274 #define CONFIG_CMD_NAND 1 275 #define CONFIG_NAND_FSL_ELBC 1 276 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 277 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 278 279 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 280 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 281 | BR_PS_8 /* 8 bit port */ \ 282 | BR_MS_FCM /* MSEL = FCM */ \ 283 | BR_V) /* valid */ 284 #define CONFIG_SYS_NAND_OR_PRELIM \ 285 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 286 | OR_FCM_CSCT \ 287 | OR_FCM_CST \ 288 | OR_FCM_CHT \ 289 | OR_FCM_SCY_1 \ 290 | OR_FCM_TRLX \ 291 | OR_FCM_EHTR) 292 /* 0xFFFF8396 */ 293 294 #ifdef CONFIG_NAND 295 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 296 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 297 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 298 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 299 #else 300 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 301 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 302 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 303 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 304 #endif 305 306 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 307 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 308 309 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 310 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 311 312 /* local bus write LED / read status buffer (BCSR) mapping */ 313 #define CONFIG_SYS_BCSR_ADDR 0xFA000000 314 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 315 /* map at 0xFA000000 on LCS3 */ 316 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 317 | BR_PS_8 /* 8 bit port */ \ 318 | BR_MS_GPCM /* MSEL = GPCM */ \ 319 | BR_V) /* valid */ 320 /* 0xFA000801 */ 321 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 322 | OR_GPCM_CSNT \ 323 | OR_GPCM_ACS_DIV2 \ 324 | OR_GPCM_XACS \ 325 | OR_GPCM_SCY_15 \ 326 | OR_GPCM_TRLX_SET \ 327 | OR_GPCM_EHTR_SET \ 328 | OR_GPCM_EAD) 329 /* 0xFFFF8FF7 */ 330 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 331 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 332 333 /* Vitesse 7385 */ 334 335 #ifdef CONFIG_VSC7385_ENET 336 337 /* VSC7385 Base address on LCS2 */ 338 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 339 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 340 341 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 342 | BR_PS_8 /* 8 bit port */ \ 343 | BR_MS_GPCM /* MSEL = GPCM */ \ 344 | BR_V) /* valid */ 345 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 346 | OR_GPCM_CSNT \ 347 | OR_GPCM_XACS \ 348 | OR_GPCM_SCY_15 \ 349 | OR_GPCM_SETA \ 350 | OR_GPCM_TRLX_SET \ 351 | OR_GPCM_EHTR_SET \ 352 | OR_GPCM_EAD) 353 /* 0xFFFE09FF */ 354 355 /* Access window base at VSC7385 base */ 356 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 357 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 358 359 #endif 360 361 #define CONFIG_MPC83XX_GPIO 1 362 363 /* 364 * Serial Port 365 */ 366 #define CONFIG_CONS_INDEX 1 367 #define CONFIG_SYS_NS16550_SERIAL 368 #define CONFIG_SYS_NS16550_REG_SIZE 1 369 370 #define CONFIG_SYS_BAUDRATE_TABLE \ 371 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 372 373 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 374 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 375 376 /* I2C */ 377 #define CONFIG_SYS_I2C 378 #define CONFIG_SYS_I2C_FSL 379 #define CONFIG_SYS_FSL_I2C_SPEED 400000 380 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 381 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 382 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 383 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 384 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 385 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 386 387 /* 388 * General PCI 389 * Addresses are mapped 1-1. 390 */ 391 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 392 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 393 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 394 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 395 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 396 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 397 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 398 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 399 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 400 401 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 402 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 403 404 /* 405 * TSEC 406 */ 407 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 408 409 #define CONFIG_GMII /* MII PHY management */ 410 411 #ifdef CONFIG_TSEC1 412 #define CONFIG_HAS_ETH0 413 #define CONFIG_TSEC1_NAME "TSEC0" 414 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 415 #define TSEC1_PHY_ADDR 0x1c 416 #define TSEC1_FLAGS TSEC_GIGABIT 417 #define TSEC1_PHYIDX 0 418 #endif 419 420 #ifdef CONFIG_TSEC2 421 #define CONFIG_HAS_ETH1 422 #define CONFIG_TSEC2_NAME "TSEC1" 423 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 424 #define TSEC2_PHY_ADDR 4 425 #define TSEC2_FLAGS TSEC_GIGABIT 426 #define TSEC2_PHYIDX 0 427 #endif 428 429 /* Options are: TSEC[0-1] */ 430 #define CONFIG_ETHPRIME "TSEC1" 431 432 /* 433 * Configure on-board RTC 434 */ 435 #define CONFIG_RTC_DS1337 436 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 437 438 /* 439 * Environment 440 */ 441 #if defined(CONFIG_NAND) 442 #define CONFIG_ENV_IS_IN_NAND 1 443 #define CONFIG_ENV_OFFSET (512 * 1024) 444 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 445 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 446 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 447 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 448 #define CONFIG_ENV_OFFSET_REDUND \ 449 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 450 #elif !defined(CONFIG_SYS_RAMBOOT) 451 #define CONFIG_ENV_IS_IN_FLASH 1 452 #define CONFIG_ENV_ADDR \ 453 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 454 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 455 #define CONFIG_ENV_SIZE 0x2000 456 457 /* Address and size of Redundant Environment Sector */ 458 #else 459 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 460 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 461 #define CONFIG_ENV_SIZE 0x2000 462 #endif 463 464 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 465 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 466 467 /* 468 * BOOTP options 469 */ 470 #define CONFIG_BOOTP_BOOTFILESIZE 471 #define CONFIG_BOOTP_BOOTPATH 472 #define CONFIG_BOOTP_GATEWAY 473 #define CONFIG_BOOTP_HOSTNAME 474 475 /* 476 * Command line configuration. 477 */ 478 #define CONFIG_CMD_DATE 479 #define CONFIG_CMD_PCI 480 481 #define CONFIG_CMDLINE_EDITING 1 482 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 483 484 /* 485 * Miscellaneous configurable options 486 */ 487 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 488 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 489 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 490 491 /* Print Buffer Size */ 492 #define CONFIG_SYS_PBSIZE \ 493 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 494 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 495 /* Boot Argument Buffer Size */ 496 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 497 498 /* 499 * For booting Linux, the board info and command line data 500 * have to be in the first 256 MB of memory, since this is 501 * the maximum mapped by the Linux kernel during initialization. 502 */ 503 /* Initial Memory map for Linux*/ 504 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 505 506 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 507 508 #ifdef CONFIG_SYS_66MHZ 509 510 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 511 /* 0x62040000 */ 512 #define CONFIG_SYS_HRCW_LOW (\ 513 0x20000000 /* reserved, must be set */ |\ 514 HRCWL_DDRCM |\ 515 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 516 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 517 HRCWL_CSB_TO_CLKIN_2X1 |\ 518 HRCWL_CORE_TO_CSB_2X1) 519 520 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 521 522 #elif defined(CONFIG_SYS_33MHZ) 523 524 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 525 /* 0x65040000 */ 526 #define CONFIG_SYS_HRCW_LOW (\ 527 0x20000000 /* reserved, must be set */ |\ 528 HRCWL_DDRCM |\ 529 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 530 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 531 HRCWL_CSB_TO_CLKIN_5X1 |\ 532 HRCWL_CORE_TO_CSB_2X1) 533 534 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 535 536 #endif 537 538 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 539 HRCWH_PCI_HOST |\ 540 HRCWH_PCI1_ARBITER_ENABLE |\ 541 HRCWH_CORE_ENABLE |\ 542 HRCWH_BOOTSEQ_DISABLE |\ 543 HRCWH_SW_WATCHDOG_DISABLE |\ 544 HRCWH_TSEC1M_IN_RGMII |\ 545 HRCWH_TSEC2M_IN_RGMII |\ 546 HRCWH_BIG_ENDIAN) 547 548 #ifdef CONFIG_NAND 549 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 550 HRCWH_FROM_0XFFF00100 |\ 551 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 552 HRCWH_RL_EXT_NAND) 553 #else 554 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 555 HRCWH_FROM_0X00000100 |\ 556 HRCWH_ROM_LOC_LOCAL_16BIT |\ 557 HRCWH_RL_EXT_LEGACY) 558 #endif 559 560 /* System IO Config */ 561 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 562 /* Enable Internal USB Phy and GPIO on LCD Connector */ 563 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 564 565 #define CONFIG_SYS_HID0_INIT 0x000000000 566 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 567 HID0_ENABLE_INSTRUCTION_CACHE | \ 568 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 569 570 #define CONFIG_SYS_HID2 HID2_HBE 571 572 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 573 574 /* DDR @ 0x00000000 */ 575 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 576 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 577 | BATU_BL_256M \ 578 | BATU_VS \ 579 | BATU_VP) 580 581 /* PCI @ 0x80000000 */ 582 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 583 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 584 | BATU_BL_256M \ 585 | BATU_VS \ 586 | BATU_VP) 587 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 588 | BATL_PP_RW \ 589 | BATL_CACHEINHIBIT \ 590 | BATL_GUARDEDSTORAGE) 591 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 592 | BATU_BL_256M \ 593 | BATU_VS \ 594 | BATU_VP) 595 596 /* PCI2 not supported on 8313 */ 597 #define CONFIG_SYS_IBAT3L (0) 598 #define CONFIG_SYS_IBAT3U (0) 599 #define CONFIG_SYS_IBAT4L (0) 600 #define CONFIG_SYS_IBAT4U (0) 601 602 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 603 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 604 | BATL_PP_RW \ 605 | BATL_CACHEINHIBIT \ 606 | BATL_GUARDEDSTORAGE) 607 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 608 | BATU_BL_256M \ 609 | BATU_VS \ 610 | BATU_VP) 611 612 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 613 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 614 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 615 616 #define CONFIG_SYS_IBAT7L (0) 617 #define CONFIG_SYS_IBAT7U (0) 618 619 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 620 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 621 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 622 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 623 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 624 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 625 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 626 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 627 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 628 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 629 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 630 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 631 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 632 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 633 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 634 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 635 636 /* 637 * Environment Configuration 638 */ 639 #define CONFIG_ENV_OVERWRITE 640 641 #define CONFIG_NETDEV "eth1" 642 643 #define CONFIG_HOSTNAME mpc8313erdb 644 #define CONFIG_ROOTPATH "/nfs/root/path" 645 #define CONFIG_BOOTFILE "uImage" 646 /* U-Boot image on TFTP server */ 647 #define CONFIG_UBOOTPATH "u-boot.bin" 648 #define CONFIG_FDTFILE "mpc8313erdb.dtb" 649 650 /* default location for tftp and bootm */ 651 #define CONFIG_LOADADDR 800000 652 #define CONFIG_BAUDRATE 115200 653 654 #define CONFIG_EXTRA_ENV_SETTINGS \ 655 "netdev=" CONFIG_NETDEV "\0" \ 656 "ethprime=TSEC1\0" \ 657 "uboot=" CONFIG_UBOOTPATH "\0" \ 658 "tftpflash=tftpboot $loadaddr $uboot; " \ 659 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 660 " +$filesize; " \ 661 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 662 " +$filesize; " \ 663 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 664 " $filesize; " \ 665 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 666 " +$filesize; " \ 667 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 668 " $filesize\0" \ 669 "fdtaddr=780000\0" \ 670 "fdtfile=" CONFIG_FDTFILE "\0" \ 671 "console=ttyS0\0" \ 672 "setbootargs=setenv bootargs " \ 673 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 674 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 675 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 676 "$netdev:off " \ 677 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 678 679 #define CONFIG_NFSBOOTCOMMAND \ 680 "setenv rootdev /dev/nfs;" \ 681 "run setbootargs;" \ 682 "run setipargs;" \ 683 "tftp $loadaddr $bootfile;" \ 684 "tftp $fdtaddr $fdtfile;" \ 685 "bootm $loadaddr - $fdtaddr" 686 687 #define CONFIG_RAMBOOTCOMMAND \ 688 "setenv rootdev /dev/ram;" \ 689 "run setbootargs;" \ 690 "tftp $ramdiskaddr $ramdiskfile;" \ 691 "tftp $loadaddr $bootfile;" \ 692 "tftp $fdtaddr $fdtfile;" \ 693 "bootm $loadaddr $ramdiskaddr $fdtaddr" 694 695 #endif /* __CONFIG_H */ 696