1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 /* 7 * mpc8313epb board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_E300 1 17 #define CONFIG_MPC831x 1 18 #define CONFIG_MPC8313 1 19 #define CONFIG_MPC8313ERDB 1 20 21 #ifdef CONFIG_NAND 22 #define CONFIG_SPL_INIT_MINIMAL 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 25 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 26 27 #ifdef CONFIG_SPL_BUILD 28 #define CONFIG_NS16550_MIN_FUNCTIONS 29 #endif 30 31 #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 32 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 33 #define CONFIG_SPL_MAX_SIZE (4 * 1024) 34 #define CONFIG_SPL_PAD_TO 0x4000 35 36 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 37 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 38 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 39 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 40 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 41 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 42 43 #ifdef CONFIG_SPL_BUILD 44 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 45 #endif 46 47 #endif /* CONFIG_NAND */ 48 49 #ifndef CONFIG_SYS_TEXT_BASE 50 #define CONFIG_SYS_TEXT_BASE 0xFE000000 51 #endif 52 53 #ifndef CONFIG_SYS_MONITOR_BASE 54 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 55 #endif 56 57 #define CONFIG_PCI_INDIRECT_BRIDGE 58 #define CONFIG_FSL_ELBC 1 59 60 #define CONFIG_MISC_INIT_R 61 62 /* 63 * On-board devices 64 * 65 * TSEC1 is VSC switch 66 * TSEC2 is SoC TSEC 67 */ 68 #define CONFIG_VSC7385_ENET 69 #define CONFIG_TSEC2 70 71 #ifdef CONFIG_SYS_66MHZ 72 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 73 #elif defined(CONFIG_SYS_33MHZ) 74 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 75 #else 76 #error Unknown oscillator frequency. 77 #endif 78 79 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 80 81 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */ 82 83 #define CONFIG_SYS_IMMR 0xE0000000 84 85 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) 86 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 87 #endif 88 89 #define CONFIG_SYS_MEMTEST_START 0x00001000 90 #define CONFIG_SYS_MEMTEST_END 0x07f00000 91 92 /* Early revs of this board will lock up hard when attempting 93 * to access the PMC registers, unless a JTAG debugger is 94 * connected, or some resistor modifications are made. 95 */ 96 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 97 98 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 99 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 100 101 /* 102 * Device configurations 103 */ 104 105 /* Vitesse 7385 */ 106 107 #ifdef CONFIG_VSC7385_ENET 108 109 #define CONFIG_TSEC1 110 111 /* The flash address and size of the VSC7385 firmware image */ 112 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 113 #define CONFIG_VSC7385_IMAGE_SIZE 8192 114 115 #endif 116 117 /* 118 * DDR Setup 119 */ 120 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 121 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 122 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 123 124 /* 125 * Manually set up DDR parameters, as this board does not 126 * seem to have the SPD connected to I2C. 127 */ 128 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 129 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 130 | CSCONFIG_ODT_RD_NEVER \ 131 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 132 | CSCONFIG_ROW_BIT_13 \ 133 | CSCONFIG_COL_BIT_10) 134 /* 0x80010102 */ 135 136 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 137 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 138 | (0 << TIMING_CFG0_WRT_SHIFT) \ 139 | (0 << TIMING_CFG0_RRT_SHIFT) \ 140 | (0 << TIMING_CFG0_WWT_SHIFT) \ 141 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 142 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 143 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 144 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 145 /* 0x00220802 */ 146 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 147 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 148 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 149 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 150 | (10 << TIMING_CFG1_REFREC_SHIFT) \ 151 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 152 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 153 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 154 /* 0x3835a322 */ 155 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 156 | (5 << TIMING_CFG2_CPO_SHIFT) \ 157 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 158 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 159 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 160 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 161 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 162 /* 0x129048c6 */ /* P9-45,may need tuning */ 163 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 164 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 165 /* 0x05100500 */ 166 #if defined(CONFIG_DDR_2T_TIMING) 167 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 168 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 169 | SDRAM_CFG_DBW_32 \ 170 | SDRAM_CFG_2T_EN) 171 /* 0x43088000 */ 172 #else 173 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 174 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 175 | SDRAM_CFG_DBW_32) 176 /* 0x43080000 */ 177 #endif 178 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 179 /* set burst length to 8 for 32-bit data path */ 180 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 181 | (0x0632 << SDRAM_MODE_SD_SHIFT)) 182 /* 0x44480632 */ 183 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 184 185 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 186 /*0x02000000*/ 187 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 188 | DDRCDR_PZ_NOMZ \ 189 | DDRCDR_NZ_NOMZ \ 190 | DDRCDR_M_ODR) 191 192 /* 193 * FLASH on the Local Bus 194 */ 195 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 196 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 197 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 198 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 199 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 200 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 201 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 202 203 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 204 | BR_PS_16 /* 16 bit port */ \ 205 | BR_MS_GPCM /* MSEL = GPCM */ \ 206 | BR_V) /* valid */ 207 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 208 | OR_GPCM_XACS \ 209 | OR_GPCM_SCY_9 \ 210 | OR_GPCM_EHTR \ 211 | OR_GPCM_EAD) 212 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 213 /* window base at flash base */ 214 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 215 /* 16 MB window size */ 216 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 217 218 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 219 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 220 221 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 222 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 223 224 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 225 !defined(CONFIG_SPL_BUILD) 226 #define CONFIG_SYS_RAMBOOT 227 #endif 228 229 #define CONFIG_SYS_INIT_RAM_LOCK 1 230 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 231 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 232 233 #define CONFIG_SYS_GBL_DATA_OFFSET \ 234 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 235 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 236 237 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 238 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 239 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 240 241 /* 242 * Local Bus LCRR and LBCR regs 243 */ 244 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 245 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 246 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 247 | (0xFF << LBCR_BMT_SHIFT) \ 248 | 0xF) /* 0x0004ff0f */ 249 250 /* LB refresh timer prescal, 266MHz/32 */ 251 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 252 253 /* drivers/mtd/nand/nand.c */ 254 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) 255 #define CONFIG_SYS_NAND_BASE 0xFFF00000 256 #else 257 #define CONFIG_SYS_NAND_BASE 0xE2800000 258 #endif 259 260 #define CONFIG_MTD_DEVICE 261 #define CONFIG_MTD_PARTITION 262 263 #define CONFIG_SYS_MAX_NAND_DEVICE 1 264 #define CONFIG_NAND_FSL_ELBC 1 265 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 266 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 267 268 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 269 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 270 | BR_PS_8 /* 8 bit port */ \ 271 | BR_MS_FCM /* MSEL = FCM */ \ 272 | BR_V) /* valid */ 273 #define CONFIG_SYS_NAND_OR_PRELIM \ 274 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 275 | OR_FCM_CSCT \ 276 | OR_FCM_CST \ 277 | OR_FCM_CHT \ 278 | OR_FCM_SCY_1 \ 279 | OR_FCM_TRLX \ 280 | OR_FCM_EHTR) 281 /* 0xFFFF8396 */ 282 283 #ifdef CONFIG_NAND 284 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 285 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 286 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 287 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 288 #else 289 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 290 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 291 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 292 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 293 #endif 294 295 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 296 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 297 298 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 299 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 300 301 /* local bus write LED / read status buffer (BCSR) mapping */ 302 #define CONFIG_SYS_BCSR_ADDR 0xFA000000 303 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 304 /* map at 0xFA000000 on LCS3 */ 305 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 306 | BR_PS_8 /* 8 bit port */ \ 307 | BR_MS_GPCM /* MSEL = GPCM */ \ 308 | BR_V) /* valid */ 309 /* 0xFA000801 */ 310 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 311 | OR_GPCM_CSNT \ 312 | OR_GPCM_ACS_DIV2 \ 313 | OR_GPCM_XACS \ 314 | OR_GPCM_SCY_15 \ 315 | OR_GPCM_TRLX_SET \ 316 | OR_GPCM_EHTR_SET \ 317 | OR_GPCM_EAD) 318 /* 0xFFFF8FF7 */ 319 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 320 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 321 322 /* Vitesse 7385 */ 323 324 #ifdef CONFIG_VSC7385_ENET 325 326 /* VSC7385 Base address on LCS2 */ 327 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 328 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 329 330 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 331 | BR_PS_8 /* 8 bit port */ \ 332 | BR_MS_GPCM /* MSEL = GPCM */ \ 333 | BR_V) /* valid */ 334 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 335 | OR_GPCM_CSNT \ 336 | OR_GPCM_XACS \ 337 | OR_GPCM_SCY_15 \ 338 | OR_GPCM_SETA \ 339 | OR_GPCM_TRLX_SET \ 340 | OR_GPCM_EHTR_SET \ 341 | OR_GPCM_EAD) 342 /* 0xFFFE09FF */ 343 344 /* Access window base at VSC7385 base */ 345 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 346 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 347 348 #endif 349 350 #define CONFIG_MPC83XX_GPIO 1 351 352 /* 353 * Serial Port 354 */ 355 #define CONFIG_CONS_INDEX 1 356 #define CONFIG_SYS_NS16550_SERIAL 357 #define CONFIG_SYS_NS16550_REG_SIZE 1 358 359 #define CONFIG_SYS_BAUDRATE_TABLE \ 360 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 361 362 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 363 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 364 365 /* I2C */ 366 #define CONFIG_SYS_I2C 367 #define CONFIG_SYS_I2C_FSL 368 #define CONFIG_SYS_FSL_I2C_SPEED 400000 369 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 370 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 371 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 372 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 373 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 374 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 375 376 /* 377 * General PCI 378 * Addresses are mapped 1-1. 379 */ 380 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 381 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 382 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 383 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 384 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 385 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 386 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 387 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 388 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 389 390 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 391 392 /* 393 * TSEC 394 */ 395 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 396 397 #define CONFIG_GMII /* MII PHY management */ 398 399 #ifdef CONFIG_TSEC1 400 #define CONFIG_HAS_ETH0 401 #define CONFIG_TSEC1_NAME "TSEC0" 402 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 403 #define TSEC1_PHY_ADDR 0x1c 404 #define TSEC1_FLAGS TSEC_GIGABIT 405 #define TSEC1_PHYIDX 0 406 #endif 407 408 #ifdef CONFIG_TSEC2 409 #define CONFIG_HAS_ETH1 410 #define CONFIG_TSEC2_NAME "TSEC1" 411 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 412 #define TSEC2_PHY_ADDR 4 413 #define TSEC2_FLAGS TSEC_GIGABIT 414 #define TSEC2_PHYIDX 0 415 #endif 416 417 /* Options are: TSEC[0-1] */ 418 #define CONFIG_ETHPRIME "TSEC1" 419 420 /* 421 * Configure on-board RTC 422 */ 423 #define CONFIG_RTC_DS1337 424 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 425 426 /* 427 * Environment 428 */ 429 #if defined(CONFIG_NAND) 430 #define CONFIG_ENV_OFFSET (512 * 1024) 431 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 432 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 433 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 434 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 435 #define CONFIG_ENV_OFFSET_REDUND \ 436 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 437 #elif !defined(CONFIG_SYS_RAMBOOT) 438 #define CONFIG_ENV_ADDR \ 439 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 440 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 441 #define CONFIG_ENV_SIZE 0x2000 442 443 /* Address and size of Redundant Environment Sector */ 444 #else 445 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 446 #define CONFIG_ENV_SIZE 0x2000 447 #endif 448 449 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 450 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 451 452 /* 453 * BOOTP options 454 */ 455 #define CONFIG_BOOTP_BOOTFILESIZE 456 #define CONFIG_BOOTP_BOOTPATH 457 #define CONFIG_BOOTP_GATEWAY 458 #define CONFIG_BOOTP_HOSTNAME 459 460 /* 461 * Command line configuration. 462 */ 463 464 #define CONFIG_CMDLINE_EDITING 1 465 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 466 467 /* 468 * Miscellaneous configurable options 469 */ 470 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 471 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 472 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 473 474 /* Boot Argument Buffer Size */ 475 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 476 477 /* 478 * For booting Linux, the board info and command line data 479 * have to be in the first 256 MB of memory, since this is 480 * the maximum mapped by the Linux kernel during initialization. 481 */ 482 /* Initial Memory map for Linux*/ 483 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 484 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 485 486 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 487 488 #ifdef CONFIG_SYS_66MHZ 489 490 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 491 /* 0x62040000 */ 492 #define CONFIG_SYS_HRCW_LOW (\ 493 0x20000000 /* reserved, must be set */ |\ 494 HRCWL_DDRCM |\ 495 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 496 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 497 HRCWL_CSB_TO_CLKIN_2X1 |\ 498 HRCWL_CORE_TO_CSB_2X1) 499 500 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 501 502 #elif defined(CONFIG_SYS_33MHZ) 503 504 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 505 /* 0x65040000 */ 506 #define CONFIG_SYS_HRCW_LOW (\ 507 0x20000000 /* reserved, must be set */ |\ 508 HRCWL_DDRCM |\ 509 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 510 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 511 HRCWL_CSB_TO_CLKIN_5X1 |\ 512 HRCWL_CORE_TO_CSB_2X1) 513 514 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 515 516 #endif 517 518 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 519 HRCWH_PCI_HOST |\ 520 HRCWH_PCI1_ARBITER_ENABLE |\ 521 HRCWH_CORE_ENABLE |\ 522 HRCWH_BOOTSEQ_DISABLE |\ 523 HRCWH_SW_WATCHDOG_DISABLE |\ 524 HRCWH_TSEC1M_IN_RGMII |\ 525 HRCWH_TSEC2M_IN_RGMII |\ 526 HRCWH_BIG_ENDIAN) 527 528 #ifdef CONFIG_NAND 529 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 530 HRCWH_FROM_0XFFF00100 |\ 531 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 532 HRCWH_RL_EXT_NAND) 533 #else 534 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 535 HRCWH_FROM_0X00000100 |\ 536 HRCWH_ROM_LOC_LOCAL_16BIT |\ 537 HRCWH_RL_EXT_LEGACY) 538 #endif 539 540 /* System IO Config */ 541 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 542 /* Enable Internal USB Phy and GPIO on LCD Connector */ 543 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 544 545 #define CONFIG_SYS_HID0_INIT 0x000000000 546 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 547 HID0_ENABLE_INSTRUCTION_CACHE | \ 548 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 549 550 #define CONFIG_SYS_HID2 HID2_HBE 551 552 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 553 554 /* DDR @ 0x00000000 */ 555 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 556 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 557 | BATU_BL_256M \ 558 | BATU_VS \ 559 | BATU_VP) 560 561 /* PCI @ 0x80000000 */ 562 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 563 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 564 | BATU_BL_256M \ 565 | BATU_VS \ 566 | BATU_VP) 567 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 568 | BATL_PP_RW \ 569 | BATL_CACHEINHIBIT \ 570 | BATL_GUARDEDSTORAGE) 571 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 572 | BATU_BL_256M \ 573 | BATU_VS \ 574 | BATU_VP) 575 576 /* PCI2 not supported on 8313 */ 577 #define CONFIG_SYS_IBAT3L (0) 578 #define CONFIG_SYS_IBAT3U (0) 579 #define CONFIG_SYS_IBAT4L (0) 580 #define CONFIG_SYS_IBAT4U (0) 581 582 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 583 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 584 | BATL_PP_RW \ 585 | BATL_CACHEINHIBIT \ 586 | BATL_GUARDEDSTORAGE) 587 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 588 | BATU_BL_256M \ 589 | BATU_VS \ 590 | BATU_VP) 591 592 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 593 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 594 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 595 596 #define CONFIG_SYS_IBAT7L (0) 597 #define CONFIG_SYS_IBAT7U (0) 598 599 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 600 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 601 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 602 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 603 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 604 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 605 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 606 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 607 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 608 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 609 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 610 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 611 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 612 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 613 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 614 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 615 616 /* 617 * Environment Configuration 618 */ 619 #define CONFIG_ENV_OVERWRITE 620 621 #define CONFIG_NETDEV "eth1" 622 623 #define CONFIG_HOSTNAME mpc8313erdb 624 #define CONFIG_ROOTPATH "/nfs/root/path" 625 #define CONFIG_BOOTFILE "uImage" 626 /* U-Boot image on TFTP server */ 627 #define CONFIG_UBOOTPATH "u-boot.bin" 628 #define CONFIG_FDTFILE "mpc8313erdb.dtb" 629 630 /* default location for tftp and bootm */ 631 #define CONFIG_LOADADDR 800000 632 633 #define CONFIG_EXTRA_ENV_SETTINGS \ 634 "netdev=" CONFIG_NETDEV "\0" \ 635 "ethprime=TSEC1\0" \ 636 "uboot=" CONFIG_UBOOTPATH "\0" \ 637 "tftpflash=tftpboot $loadaddr $uboot; " \ 638 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 639 " +$filesize; " \ 640 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 641 " +$filesize; " \ 642 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 643 " $filesize; " \ 644 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 645 " +$filesize; " \ 646 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 647 " $filesize\0" \ 648 "fdtaddr=780000\0" \ 649 "fdtfile=" CONFIG_FDTFILE "\0" \ 650 "console=ttyS0\0" \ 651 "setbootargs=setenv bootargs " \ 652 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 653 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 654 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 655 "$netdev:off " \ 656 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 657 658 #define CONFIG_NFSBOOTCOMMAND \ 659 "setenv rootdev /dev/nfs;" \ 660 "run setbootargs;" \ 661 "run setipargs;" \ 662 "tftp $loadaddr $bootfile;" \ 663 "tftp $fdtaddr $fdtfile;" \ 664 "bootm $loadaddr - $fdtaddr" 665 666 #define CONFIG_RAMBOOTCOMMAND \ 667 "setenv rootdev /dev/ram;" \ 668 "run setbootargs;" \ 669 "tftp $ramdiskaddr $ramdiskfile;" \ 670 "tftp $loadaddr $bootfile;" \ 671 "tftp $fdtaddr $fdtfile;" \ 672 "bootm $loadaddr $ramdiskaddr $fdtaddr" 673 674 #endif /* __CONFIG_H */ 675