1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 /* 7 * mpc8313epb board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_E300 1 17 #define CONFIG_MPC831x 1 18 #define CONFIG_MPC8313 1 19 #define CONFIG_MPC8313ERDB 1 20 21 #ifdef CONFIG_NAND 22 #define CONFIG_SPL_INIT_MINIMAL 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 25 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 26 27 #ifdef CONFIG_SPL_BUILD 28 #define CONFIG_NS16550_MIN_FUNCTIONS 29 #endif 30 31 #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 32 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 33 #define CONFIG_SPL_MAX_SIZE (4 * 1024) 34 #define CONFIG_SPL_PAD_TO 0x4000 35 36 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 37 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 38 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 39 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 40 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 41 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 42 43 #ifdef CONFIG_SPL_BUILD 44 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 45 #endif 46 47 #endif /* CONFIG_NAND */ 48 49 #ifndef CONFIG_SYS_TEXT_BASE 50 #define CONFIG_SYS_TEXT_BASE 0xFE000000 51 #endif 52 53 #ifndef CONFIG_SYS_MONITOR_BASE 54 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 55 #endif 56 57 #define CONFIG_PCI_INDIRECT_BRIDGE 58 #define CONFIG_FSL_ELBC 1 59 60 #define CONFIG_MISC_INIT_R 61 62 /* 63 * On-board devices 64 * 65 * TSEC1 is VSC switch 66 * TSEC2 is SoC TSEC 67 */ 68 #define CONFIG_VSC7385_ENET 69 #define CONFIG_TSEC2 70 71 #ifdef CONFIG_SYS_66MHZ 72 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 73 #elif defined(CONFIG_SYS_33MHZ) 74 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 75 #else 76 #error Unknown oscillator frequency. 77 #endif 78 79 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 80 81 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ 82 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */ 83 84 #define CONFIG_SYS_IMMR 0xE0000000 85 86 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) 87 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 88 #endif 89 90 #define CONFIG_SYS_MEMTEST_START 0x00001000 91 #define CONFIG_SYS_MEMTEST_END 0x07f00000 92 93 /* Early revs of this board will lock up hard when attempting 94 * to access the PMC registers, unless a JTAG debugger is 95 * connected, or some resistor modifications are made. 96 */ 97 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 98 99 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 100 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 101 102 /* 103 * Device configurations 104 */ 105 106 /* Vitesse 7385 */ 107 108 #ifdef CONFIG_VSC7385_ENET 109 110 #define CONFIG_TSEC1 111 112 /* The flash address and size of the VSC7385 firmware image */ 113 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 114 #define CONFIG_VSC7385_IMAGE_SIZE 8192 115 116 #endif 117 118 /* 119 * DDR Setup 120 */ 121 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 122 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 123 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 124 125 /* 126 * Manually set up DDR parameters, as this board does not 127 * seem to have the SPD connected to I2C. 128 */ 129 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 130 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 131 | CSCONFIG_ODT_RD_NEVER \ 132 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 133 | CSCONFIG_ROW_BIT_13 \ 134 | CSCONFIG_COL_BIT_10) 135 /* 0x80010102 */ 136 137 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 138 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 139 | (0 << TIMING_CFG0_WRT_SHIFT) \ 140 | (0 << TIMING_CFG0_RRT_SHIFT) \ 141 | (0 << TIMING_CFG0_WWT_SHIFT) \ 142 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 143 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 144 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 145 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 146 /* 0x00220802 */ 147 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 148 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 149 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 150 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 151 | (10 << TIMING_CFG1_REFREC_SHIFT) \ 152 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 153 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 154 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 155 /* 0x3835a322 */ 156 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 157 | (5 << TIMING_CFG2_CPO_SHIFT) \ 158 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 159 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 160 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 161 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 162 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 163 /* 0x129048c6 */ /* P9-45,may need tuning */ 164 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 165 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 166 /* 0x05100500 */ 167 #if defined(CONFIG_DDR_2T_TIMING) 168 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 169 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 170 | SDRAM_CFG_DBW_32 \ 171 | SDRAM_CFG_2T_EN) 172 /* 0x43088000 */ 173 #else 174 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 175 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 176 | SDRAM_CFG_DBW_32) 177 /* 0x43080000 */ 178 #endif 179 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 180 /* set burst length to 8 for 32-bit data path */ 181 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 182 | (0x0632 << SDRAM_MODE_SD_SHIFT)) 183 /* 0x44480632 */ 184 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 185 186 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 187 /*0x02000000*/ 188 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 189 | DDRCDR_PZ_NOMZ \ 190 | DDRCDR_NZ_NOMZ \ 191 | DDRCDR_M_ODR) 192 193 /* 194 * FLASH on the Local Bus 195 */ 196 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 197 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 198 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 199 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 200 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 201 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 202 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 203 204 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 205 | BR_PS_16 /* 16 bit port */ \ 206 | BR_MS_GPCM /* MSEL = GPCM */ \ 207 | BR_V) /* valid */ 208 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 209 | OR_GPCM_XACS \ 210 | OR_GPCM_SCY_9 \ 211 | OR_GPCM_EHTR \ 212 | OR_GPCM_EAD) 213 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 214 /* window base at flash base */ 215 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 216 /* 16 MB window size */ 217 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 218 219 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 220 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 221 222 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 223 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 224 225 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 226 !defined(CONFIG_SPL_BUILD) 227 #define CONFIG_SYS_RAMBOOT 228 #endif 229 230 #define CONFIG_SYS_INIT_RAM_LOCK 1 231 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 232 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 233 234 #define CONFIG_SYS_GBL_DATA_OFFSET \ 235 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 236 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 237 238 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 239 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 240 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 241 242 /* 243 * Local Bus LCRR and LBCR regs 244 */ 245 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 246 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 247 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 248 | (0xFF << LBCR_BMT_SHIFT) \ 249 | 0xF) /* 0x0004ff0f */ 250 251 /* LB refresh timer prescal, 266MHz/32 */ 252 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 253 254 /* drivers/mtd/nand/nand.c */ 255 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) 256 #define CONFIG_SYS_NAND_BASE 0xFFF00000 257 #else 258 #define CONFIG_SYS_NAND_BASE 0xE2800000 259 #endif 260 261 #define CONFIG_MTD_DEVICE 262 #define CONFIG_MTD_PARTITION 263 #define CONFIG_CMD_MTDPARTS 264 #define MTDIDS_DEFAULT "nand0=e2800000.flash" 265 #define MTDPARTS_DEFAULT \ 266 "mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" 267 268 #define CONFIG_SYS_MAX_NAND_DEVICE 1 269 #define CONFIG_CMD_NAND 1 270 #define CONFIG_NAND_FSL_ELBC 1 271 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 272 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 273 274 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 275 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 276 | BR_PS_8 /* 8 bit port */ \ 277 | BR_MS_FCM /* MSEL = FCM */ \ 278 | BR_V) /* valid */ 279 #define CONFIG_SYS_NAND_OR_PRELIM \ 280 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 281 | OR_FCM_CSCT \ 282 | OR_FCM_CST \ 283 | OR_FCM_CHT \ 284 | OR_FCM_SCY_1 \ 285 | OR_FCM_TRLX \ 286 | OR_FCM_EHTR) 287 /* 0xFFFF8396 */ 288 289 #ifdef CONFIG_NAND 290 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 291 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 292 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 293 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 294 #else 295 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 296 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 297 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 298 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 299 #endif 300 301 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 302 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 303 304 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 305 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 306 307 /* local bus write LED / read status buffer (BCSR) mapping */ 308 #define CONFIG_SYS_BCSR_ADDR 0xFA000000 309 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 310 /* map at 0xFA000000 on LCS3 */ 311 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 312 | BR_PS_8 /* 8 bit port */ \ 313 | BR_MS_GPCM /* MSEL = GPCM */ \ 314 | BR_V) /* valid */ 315 /* 0xFA000801 */ 316 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 317 | OR_GPCM_CSNT \ 318 | OR_GPCM_ACS_DIV2 \ 319 | OR_GPCM_XACS \ 320 | OR_GPCM_SCY_15 \ 321 | OR_GPCM_TRLX_SET \ 322 | OR_GPCM_EHTR_SET \ 323 | OR_GPCM_EAD) 324 /* 0xFFFF8FF7 */ 325 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 326 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 327 328 /* Vitesse 7385 */ 329 330 #ifdef CONFIG_VSC7385_ENET 331 332 /* VSC7385 Base address on LCS2 */ 333 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 334 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 335 336 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 337 | BR_PS_8 /* 8 bit port */ \ 338 | BR_MS_GPCM /* MSEL = GPCM */ \ 339 | BR_V) /* valid */ 340 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 341 | OR_GPCM_CSNT \ 342 | OR_GPCM_XACS \ 343 | OR_GPCM_SCY_15 \ 344 | OR_GPCM_SETA \ 345 | OR_GPCM_TRLX_SET \ 346 | OR_GPCM_EHTR_SET \ 347 | OR_GPCM_EAD) 348 /* 0xFFFE09FF */ 349 350 /* Access window base at VSC7385 base */ 351 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 352 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 353 354 #endif 355 356 #define CONFIG_MPC83XX_GPIO 1 357 358 /* 359 * Serial Port 360 */ 361 #define CONFIG_CONS_INDEX 1 362 #define CONFIG_SYS_NS16550_SERIAL 363 #define CONFIG_SYS_NS16550_REG_SIZE 1 364 365 #define CONFIG_SYS_BAUDRATE_TABLE \ 366 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 367 368 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 369 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 370 371 /* I2C */ 372 #define CONFIG_SYS_I2C 373 #define CONFIG_SYS_I2C_FSL 374 #define CONFIG_SYS_FSL_I2C_SPEED 400000 375 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 376 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 377 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 378 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 379 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 380 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 381 382 /* 383 * General PCI 384 * Addresses are mapped 1-1. 385 */ 386 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 387 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 388 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 389 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 390 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 391 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 392 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 393 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 394 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 395 396 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 397 398 /* 399 * TSEC 400 */ 401 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 402 403 #define CONFIG_GMII /* MII PHY management */ 404 405 #ifdef CONFIG_TSEC1 406 #define CONFIG_HAS_ETH0 407 #define CONFIG_TSEC1_NAME "TSEC0" 408 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 409 #define TSEC1_PHY_ADDR 0x1c 410 #define TSEC1_FLAGS TSEC_GIGABIT 411 #define TSEC1_PHYIDX 0 412 #endif 413 414 #ifdef CONFIG_TSEC2 415 #define CONFIG_HAS_ETH1 416 #define CONFIG_TSEC2_NAME "TSEC1" 417 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 418 #define TSEC2_PHY_ADDR 4 419 #define TSEC2_FLAGS TSEC_GIGABIT 420 #define TSEC2_PHYIDX 0 421 #endif 422 423 /* Options are: TSEC[0-1] */ 424 #define CONFIG_ETHPRIME "TSEC1" 425 426 /* 427 * Configure on-board RTC 428 */ 429 #define CONFIG_RTC_DS1337 430 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 431 432 /* 433 * Environment 434 */ 435 #if defined(CONFIG_NAND) 436 #define CONFIG_ENV_IS_IN_NAND 1 437 #define CONFIG_ENV_OFFSET (512 * 1024) 438 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 439 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 440 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 441 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 442 #define CONFIG_ENV_OFFSET_REDUND \ 443 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 444 #elif !defined(CONFIG_SYS_RAMBOOT) 445 #define CONFIG_ENV_IS_IN_FLASH 1 446 #define CONFIG_ENV_ADDR \ 447 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 448 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 449 #define CONFIG_ENV_SIZE 0x2000 450 451 /* Address and size of Redundant Environment Sector */ 452 #else 453 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 454 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 455 #define CONFIG_ENV_SIZE 0x2000 456 #endif 457 458 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 459 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 460 461 /* 462 * BOOTP options 463 */ 464 #define CONFIG_BOOTP_BOOTFILESIZE 465 #define CONFIG_BOOTP_BOOTPATH 466 #define CONFIG_BOOTP_GATEWAY 467 #define CONFIG_BOOTP_HOSTNAME 468 469 /* 470 * Command line configuration. 471 */ 472 #define CONFIG_CMD_DATE 473 #define CONFIG_CMD_PCI 474 475 #define CONFIG_CMDLINE_EDITING 1 476 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 477 478 /* 479 * Miscellaneous configurable options 480 */ 481 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 482 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 483 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 484 485 /* Print Buffer Size */ 486 #define CONFIG_SYS_PBSIZE \ 487 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 488 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 489 /* Boot Argument Buffer Size */ 490 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 491 492 /* 493 * For booting Linux, the board info and command line data 494 * have to be in the first 256 MB of memory, since this is 495 * the maximum mapped by the Linux kernel during initialization. 496 */ 497 /* Initial Memory map for Linux*/ 498 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 499 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 500 501 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 502 503 #ifdef CONFIG_SYS_66MHZ 504 505 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 506 /* 0x62040000 */ 507 #define CONFIG_SYS_HRCW_LOW (\ 508 0x20000000 /* reserved, must be set */ |\ 509 HRCWL_DDRCM |\ 510 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 511 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 512 HRCWL_CSB_TO_CLKIN_2X1 |\ 513 HRCWL_CORE_TO_CSB_2X1) 514 515 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 516 517 #elif defined(CONFIG_SYS_33MHZ) 518 519 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 520 /* 0x65040000 */ 521 #define CONFIG_SYS_HRCW_LOW (\ 522 0x20000000 /* reserved, must be set */ |\ 523 HRCWL_DDRCM |\ 524 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 525 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 526 HRCWL_CSB_TO_CLKIN_5X1 |\ 527 HRCWL_CORE_TO_CSB_2X1) 528 529 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 530 531 #endif 532 533 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 534 HRCWH_PCI_HOST |\ 535 HRCWH_PCI1_ARBITER_ENABLE |\ 536 HRCWH_CORE_ENABLE |\ 537 HRCWH_BOOTSEQ_DISABLE |\ 538 HRCWH_SW_WATCHDOG_DISABLE |\ 539 HRCWH_TSEC1M_IN_RGMII |\ 540 HRCWH_TSEC2M_IN_RGMII |\ 541 HRCWH_BIG_ENDIAN) 542 543 #ifdef CONFIG_NAND 544 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 545 HRCWH_FROM_0XFFF00100 |\ 546 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 547 HRCWH_RL_EXT_NAND) 548 #else 549 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 550 HRCWH_FROM_0X00000100 |\ 551 HRCWH_ROM_LOC_LOCAL_16BIT |\ 552 HRCWH_RL_EXT_LEGACY) 553 #endif 554 555 /* System IO Config */ 556 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 557 /* Enable Internal USB Phy and GPIO on LCD Connector */ 558 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 559 560 #define CONFIG_SYS_HID0_INIT 0x000000000 561 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 562 HID0_ENABLE_INSTRUCTION_CACHE | \ 563 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 564 565 #define CONFIG_SYS_HID2 HID2_HBE 566 567 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 568 569 /* DDR @ 0x00000000 */ 570 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 571 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 572 | BATU_BL_256M \ 573 | BATU_VS \ 574 | BATU_VP) 575 576 /* PCI @ 0x80000000 */ 577 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 578 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 579 | BATU_BL_256M \ 580 | BATU_VS \ 581 | BATU_VP) 582 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 583 | BATL_PP_RW \ 584 | BATL_CACHEINHIBIT \ 585 | BATL_GUARDEDSTORAGE) 586 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 587 | BATU_BL_256M \ 588 | BATU_VS \ 589 | BATU_VP) 590 591 /* PCI2 not supported on 8313 */ 592 #define CONFIG_SYS_IBAT3L (0) 593 #define CONFIG_SYS_IBAT3U (0) 594 #define CONFIG_SYS_IBAT4L (0) 595 #define CONFIG_SYS_IBAT4U (0) 596 597 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 598 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 599 | BATL_PP_RW \ 600 | BATL_CACHEINHIBIT \ 601 | BATL_GUARDEDSTORAGE) 602 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 603 | BATU_BL_256M \ 604 | BATU_VS \ 605 | BATU_VP) 606 607 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 608 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 609 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 610 611 #define CONFIG_SYS_IBAT7L (0) 612 #define CONFIG_SYS_IBAT7U (0) 613 614 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 615 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 616 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 617 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 618 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 619 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 620 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 621 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 622 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 623 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 624 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 625 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 626 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 627 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 628 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 629 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 630 631 /* 632 * Environment Configuration 633 */ 634 #define CONFIG_ENV_OVERWRITE 635 636 #define CONFIG_NETDEV "eth1" 637 638 #define CONFIG_HOSTNAME mpc8313erdb 639 #define CONFIG_ROOTPATH "/nfs/root/path" 640 #define CONFIG_BOOTFILE "uImage" 641 /* U-Boot image on TFTP server */ 642 #define CONFIG_UBOOTPATH "u-boot.bin" 643 #define CONFIG_FDTFILE "mpc8313erdb.dtb" 644 645 /* default location for tftp and bootm */ 646 #define CONFIG_LOADADDR 800000 647 #define CONFIG_BAUDRATE 115200 648 649 #define CONFIG_EXTRA_ENV_SETTINGS \ 650 "netdev=" CONFIG_NETDEV "\0" \ 651 "ethprime=TSEC1\0" \ 652 "uboot=" CONFIG_UBOOTPATH "\0" \ 653 "tftpflash=tftpboot $loadaddr $uboot; " \ 654 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 655 " +$filesize; " \ 656 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 657 " +$filesize; " \ 658 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 659 " $filesize; " \ 660 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 661 " +$filesize; " \ 662 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 663 " $filesize\0" \ 664 "fdtaddr=780000\0" \ 665 "fdtfile=" CONFIG_FDTFILE "\0" \ 666 "console=ttyS0\0" \ 667 "setbootargs=setenv bootargs " \ 668 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 669 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 670 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 671 "$netdev:off " \ 672 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 673 674 #define CONFIG_NFSBOOTCOMMAND \ 675 "setenv rootdev /dev/nfs;" \ 676 "run setbootargs;" \ 677 "run setipargs;" \ 678 "tftp $loadaddr $bootfile;" \ 679 "tftp $fdtaddr $fdtfile;" \ 680 "bootm $loadaddr - $fdtaddr" 681 682 #define CONFIG_RAMBOOTCOMMAND \ 683 "setenv rootdev /dev/ram;" \ 684 "run setbootargs;" \ 685 "tftp $ramdiskaddr $ramdiskfile;" \ 686 "tftp $loadaddr $bootfile;" \ 687 "tftp $fdtaddr $fdtfile;" \ 688 "bootm $loadaddr $ramdiskaddr $fdtaddr" 689 690 #endif /* __CONFIG_H */ 691