1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 /* 23 * mpc8313epb board configuration file 24 */ 25 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* 30 * High Level Configuration Options 31 */ 32 #define CONFIG_E300 1 33 #define CONFIG_MPC83XX 1 34 #define CONFIG_MPC831X 1 35 #define CONFIG_MPC8313 1 36 #define CONFIG_MPC8313ERDB 1 37 38 #define CONFIG_PCI 39 #define CONFIG_83XX_GENERIC_PCI 40 41 #ifdef CFG_66MHZ 42 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 43 #elif defined(CFG_33MHZ) 44 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 45 #else 46 #error Unknown oscillator frequency. 47 #endif 48 49 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 50 51 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 52 53 #define CFG_IMMR 0xE0000000 54 55 #define CFG_MEMTEST_START 0x00001000 56 #define CFG_MEMTEST_END 0x07f00000 57 58 /* Early revs of this board will lock up hard when attempting 59 * to access the PMC registers, unless a JTAG debugger is 60 * connected, or some resistor modifications are made. 61 */ 62 #define CFG_8313ERDB_BROKEN_PMC 1 63 64 #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 65 #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 66 67 /* 68 * DDR Setup 69 */ 70 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 71 #define CFG_SDRAM_BASE CFG_DDR_BASE 72 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 73 74 /* 75 * Manually set up DDR parameters, as this board does not 76 * seem to have the SPD connected to I2C. 77 */ 78 #define CFG_DDR_SIZE 128 /* MB */ 79 #define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP \ 80 | 0x00040000 /* TODO */ \ 81 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) 82 /* 0x80840102 */ 83 84 #define CFG_DDR_TIMING_3 0x00000000 85 #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 86 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 87 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 88 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 89 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 90 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 91 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 92 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 93 /* 0x00220802 */ 94 #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ 95 | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 96 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ 97 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 98 | (13 << TIMING_CFG1_REFREC_SHIFT ) \ 99 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ 100 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 101 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 102 /* 0x3935d322 */ 103 #define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 104 | (31 << TIMING_CFG2_CPO_SHIFT ) \ 105 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 106 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 107 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 108 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 109 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 110 /* 0x0f9048ca */ /* P9-45,may need tuning */ 111 #define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 112 | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 113 /* 0x03200064 */ 114 #if defined(CONFIG_DDR_2T_TIMING) 115 #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ 116 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 117 | SDRAM_CFG_2T_EN \ 118 | SDRAM_CFG_DBW_32 ) 119 #else 120 #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ 121 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 122 | SDRAM_CFG_32_BE ) 123 /* 0x43080000 */ 124 #endif 125 #define CFG_SDRAM_CFG2 0x00401000; 126 /* set burst length to 8 for 32-bit data path */ 127 #define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \ 128 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) 129 /* 0x44400232 */ 130 #define CFG_DDR_MODE_2 0x8000C000; 131 132 #define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 133 /*0x02000000*/ 134 #define CFG_DDRCDR_VALUE ( DDRCDR_EN \ 135 | DDRCDR_PZ_NOMZ \ 136 | DDRCDR_NZ_NOMZ \ 137 | DDRCDR_M_ODR ) 138 139 /* 140 * FLASH on the Local Bus 141 */ 142 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 143 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 144 #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ 145 #define CFG_FLASH_SIZE 8 /* flash size in MB */ 146 #define CFG_FLASH_EMPTY_INFO /* display empty sectors */ 147 #define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 148 149 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ 150 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 151 BR_V) /* valid */ 152 #define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \ 153 | OR_GPCM_XACS \ 154 | OR_GPCM_SCY_9 \ 155 | OR_GPCM_EHTR \ 156 | OR_GPCM_EAD ) 157 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 158 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ 159 #define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ 160 161 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 162 #define CFG_MAX_FLASH_SECT 135 /* sectors per device */ 163 164 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 165 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 166 167 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 168 169 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 170 #define CFG_RAMBOOT 171 #endif 172 173 #define CFG_INIT_RAM_LOCK 1 174 #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 175 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 176 177 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 178 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 179 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 180 181 /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ 182 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 183 #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 184 185 /* 186 * Local Bus LCRR and LBCR regs 187 */ 188 #define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */ 189 #define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ 190 | (0xFF << LBCR_BMT_SHIFT) \ 191 | 0xF ) /* 0x0004ff0f */ 192 193 #define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ 194 195 /* drivers/mtd/nand/nand.c */ 196 #define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ 197 #define CFG_MAX_NAND_DEVICE 1 198 #define NAND_MAX_CHIPS 1 199 #define CONFIG_MTD_NAND_VERIFY_WRITE 200 201 #define CFG_BR1_PRELIM ( CFG_NAND_BASE \ 202 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 203 | BR_PS_8 /* Port Size = 8 bit */ \ 204 | BR_MS_FCM /* MSEL = FCM */ \ 205 | BR_V ) /* valid */ 206 #define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ 207 | OR_FCM_CSCT \ 208 | OR_FCM_CST \ 209 | OR_FCM_CHT \ 210 | OR_FCM_SCY_1 \ 211 | OR_FCM_TRLX \ 212 | OR_FCM_EHTR ) 213 /* 0xFFFF8396 */ 214 #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE 215 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 216 217 #define CFG_VSC7385_BASE 0xF0000000 218 219 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 220 #define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ 221 #define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ 222 #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */ 223 #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ 224 225 /* local bus read write buffer mapping */ 226 #define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ 227 #define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ 228 #define CFG_LBLAWBAR3_PRELIM 0xFA000000 229 #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 230 231 /* pass open firmware flat tree */ 232 #define CONFIG_OF_LIBFDT 1 233 #define CONFIG_OF_BOARD_SETUP 1 234 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 235 236 /* 237 * Serial Port 238 */ 239 #define CONFIG_CONS_INDEX 1 240 #define CFG_NS16550 241 #define CFG_NS16550_SERIAL 242 #define CFG_NS16550_REG_SIZE 1 243 #define CFG_NS16550_CLK get_bus_freq(0) 244 245 #define CFG_BAUDRATE_TABLE \ 246 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 247 248 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 249 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 250 251 /* Use the HUSH parser */ 252 #define CFG_HUSH_PARSER 253 #define CFG_PROMPT_HUSH_PS2 "> " 254 255 /* I2C */ 256 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 257 #define CONFIG_FSL_I2C 258 #define CONFIG_I2C_MULTI_BUS 259 #define CONFIG_I2C_CMD_TREE 260 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 261 #define CFG_I2C_SLAVE 0x7F 262 #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 263 #define CFG_I2C_OFFSET 0x3000 264 #define CFG_I2C2_OFFSET 0x3100 265 266 /* TSEC */ 267 #define CFG_TSEC1_OFFSET 0x24000 268 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) 269 #define CFG_TSEC2_OFFSET 0x25000 270 #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) 271 #define CONFIG_NET_MULTI 272 273 /* 274 * General PCI 275 * Addresses are mapped 1-1. 276 */ 277 #define CFG_PCI1_MEM_BASE 0x80000000 278 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 279 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 280 #define CFG_PCI1_MMIO_BASE 0x90000000 281 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 282 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 283 #define CFG_PCI1_IO_BASE 0x00000000 284 #define CFG_PCI1_IO_PHYS 0xE2000000 285 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 286 287 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 288 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 289 290 /* 291 * TSEC configuration 292 */ 293 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 294 295 #ifndef CONFIG_NET_MULTI 296 #define CONFIG_NET_MULTI 1 297 #endif 298 299 #define CONFIG_GMII 1 /* MII PHY management */ 300 #define CONFIG_TSEC1 1 301 302 #define CONFIG_TSEC1_NAME "TSEC0" 303 #define CONFIG_TSEC2 1 304 #define CONFIG_TSEC2_NAME "TSEC1" 305 #define TSEC1_PHY_ADDR 0x1c 306 #define TSEC2_PHY_ADDR 4 307 #define TSEC1_FLAGS TSEC_GIGABIT 308 #define TSEC2_FLAGS TSEC_GIGABIT 309 #define TSEC1_PHYIDX 0 310 #define TSEC2_PHYIDX 0 311 312 /* Options are: TSEC[0-1] */ 313 #define CONFIG_ETHPRIME "TSEC1" 314 315 /* 316 * Configure on-board RTC 317 */ 318 #define CONFIG_RTC_DS1337 319 #define CFG_I2C_RTC_ADDR 0x68 320 321 /* 322 * Environment 323 */ 324 #ifndef CFG_RAMBOOT 325 #define CFG_ENV_IS_IN_FLASH 1 326 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 327 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 328 #define CFG_ENV_SIZE 0x2000 329 330 /* Address and size of Redundant Environment Sector */ 331 #else 332 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 333 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 334 #define CFG_ENV_SIZE 0x2000 335 #endif 336 337 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 338 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 339 340 /* 341 * BOOTP options 342 */ 343 #define CONFIG_BOOTP_BOOTFILESIZE 344 #define CONFIG_BOOTP_BOOTPATH 345 #define CONFIG_BOOTP_GATEWAY 346 #define CONFIG_BOOTP_HOSTNAME 347 348 349 /* 350 * Command line configuration. 351 */ 352 #include <config_cmd_default.h> 353 354 #define CONFIG_CMD_PING 355 #define CONFIG_CMD_DHCP 356 #define CONFIG_CMD_I2C 357 #define CONFIG_CMD_MII 358 #define CONFIG_CMD_DATE 359 #define CONFIG_CMD_PCI 360 361 #if defined(CFG_RAMBOOT) 362 #undef CONFIG_CMD_ENV 363 #undef CONFIG_CMD_LOADS 364 #endif 365 366 #define CONFIG_CMDLINE_EDITING 1 367 368 369 /* 370 * Miscellaneous configurable options 371 */ 372 #define CFG_LONGHELP /* undef to save memory */ 373 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 374 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 375 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 376 377 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 378 #define CFG_MAXARGS 16 /* max number of command args */ 379 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 380 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 381 382 /* 383 * For booting Linux, the board info and command line data 384 * have to be in the first 8 MB of memory, since this is 385 * the maximum mapped by the Linux kernel during initialization. 386 */ 387 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 388 389 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 390 391 #ifdef CFG_66MHZ 392 393 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 394 /* 0x62040000 */ 395 #define CFG_HRCW_LOW (\ 396 0x20000000 /* reserved, must be set */ |\ 397 HRCWL_DDRCM |\ 398 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 399 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 400 HRCWL_CSB_TO_CLKIN_2X1 |\ 401 HRCWL_CORE_TO_CSB_2X1) 402 403 #elif defined(CFG_33MHZ) 404 405 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 406 /* 0x65040000 */ 407 #define CFG_HRCW_LOW (\ 408 0x20000000 /* reserved, must be set */ |\ 409 HRCWL_DDRCM |\ 410 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 411 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 412 HRCWL_CSB_TO_CLKIN_5X1 |\ 413 HRCWL_CORE_TO_CSB_2X1) 414 415 #endif 416 417 /* 0xa0606c00 */ 418 #define CFG_HRCW_HIGH (\ 419 HRCWH_PCI_HOST |\ 420 HRCWH_PCI1_ARBITER_ENABLE |\ 421 HRCWH_CORE_ENABLE |\ 422 HRCWH_FROM_0X00000100 |\ 423 HRCWH_BOOTSEQ_DISABLE |\ 424 HRCWH_SW_WATCHDOG_DISABLE |\ 425 HRCWH_ROM_LOC_LOCAL_16BIT |\ 426 HRCWH_RL_EXT_LEGACY |\ 427 HRCWH_TSEC1M_IN_RGMII |\ 428 HRCWH_TSEC2M_IN_RGMII |\ 429 HRCWH_BIG_ENDIAN |\ 430 HRCWH_LALE_NORMAL) 431 432 /* System IO Config */ 433 #define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 434 #define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ 435 436 #define CFG_HID0_INIT 0x000000000 437 #define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 438 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 439 440 #define CFG_HID2 HID2_HBE 441 442 /* DDR @ 0x00000000 */ 443 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) 444 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 445 446 /* PCI @ 0x80000000 */ 447 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10) 448 #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 449 #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 450 #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 451 452 /* PCI2 not supported on 8313 */ 453 #define CFG_IBAT3L (0) 454 #define CFG_IBAT3U (0) 455 #define CFG_IBAT4L (0) 456 #define CFG_IBAT4U (0) 457 458 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 459 #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 460 #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 461 462 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 463 #define CFG_IBAT6L (0xF0000000 | BATL_PP_10) 464 #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 465 466 #define CFG_IBAT7L (0) 467 #define CFG_IBAT7U (0) 468 469 #define CFG_DBAT0L CFG_IBAT0L 470 #define CFG_DBAT0U CFG_IBAT0U 471 #define CFG_DBAT1L CFG_IBAT1L 472 #define CFG_DBAT1U CFG_IBAT1U 473 #define CFG_DBAT2L CFG_IBAT2L 474 #define CFG_DBAT2U CFG_IBAT2U 475 #define CFG_DBAT3L CFG_IBAT3L 476 #define CFG_DBAT3U CFG_IBAT3U 477 #define CFG_DBAT4L CFG_IBAT4L 478 #define CFG_DBAT4U CFG_IBAT4U 479 #define CFG_DBAT5L CFG_IBAT5L 480 #define CFG_DBAT5U CFG_IBAT5U 481 #define CFG_DBAT6L CFG_IBAT6L 482 #define CFG_DBAT6U CFG_IBAT6U 483 #define CFG_DBAT7L CFG_IBAT7L 484 #define CFG_DBAT7U CFG_IBAT7U 485 486 /* 487 * Internal Definitions 488 * 489 * Boot Flags 490 */ 491 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 492 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 493 494 /* 495 * Environment Configuration 496 */ 497 #define CONFIG_ENV_OVERWRITE 498 499 #define CONFIG_ETHADDR 00:E0:0C:00:95:01 500 #define CONFIG_HAS_ETH1 501 #define CONFIG_HAS_ETH0 502 #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 503 504 #define CONFIG_IPADDR 10.0.0.2 505 #define CONFIG_SERVERIP 10.0.0.1 506 #define CONFIG_GATEWAYIP 10.0.0.1 507 #define CONFIG_NETMASK 255.0.0.0 508 #define CONFIG_NETDEV eth1 509 510 #define CONFIG_HOSTNAME mpc8313erdb 511 #define CONFIG_ROOTPATH /nfs/root/path 512 #define CONFIG_BOOTFILE uImage 513 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 514 #define CONFIG_FDTFILE mpc8313erdb.dtb 515 516 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 517 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 518 #define CONFIG_BAUDRATE 115200 519 520 #define XMK_STR(x) #x 521 #define MK_STR(x) XMK_STR(x) 522 523 #define CONFIG_EXTRA_ENV_SETTINGS \ 524 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 525 "ethprime=TSEC1\0" \ 526 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 527 "tftpflash=tftpboot $loadaddr $uboot; " \ 528 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 529 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 530 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 531 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 532 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 533 "fdtaddr=400000\0" \ 534 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 535 "console=ttyS0\0" \ 536 "setbootargs=setenv bootargs " \ 537 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 538 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 539 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 540 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 541 542 #define CONFIG_NFSBOOTCOMMAND \ 543 "setenv rootdev /dev/nfs;" \ 544 "run setbootargs;" \ 545 "run setipargs;" \ 546 "tftp $loadaddr $bootfile;" \ 547 "tftp $fdtaddr $fdtfile;" \ 548 "bootm $loadaddr - $fdtaddr" 549 550 #define CONFIG_RAMBOOTCOMMAND \ 551 "setenv rootdev /dev/ram;" \ 552 "run setbootargs;" \ 553 "tftp $ramdiskaddr $ramdiskfile;" \ 554 "tftp $loadaddr $bootfile;" \ 555 "tftp $fdtaddr $fdtfile;" \ 556 "bootm $loadaddr $ramdiskaddr $fdtaddr" 557 558 #undef MK_STR 559 #undef XMK_STR 560 561 #endif /* __CONFIG_H */ 562