1 /*
2  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 /*
7  * mpc8313epb board configuration file
8  */
9 
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 #define CONFIG_DISPLAY_BOARDINFO
14 
15 /*
16  * High Level Configuration Options
17  */
18 #define CONFIG_E300		1
19 #define CONFIG_MPC831x		1
20 #define CONFIG_MPC8313		1
21 #define CONFIG_MPC8313ERDB	1
22 
23 #ifdef CONFIG_NAND
24 #define CONFIG_SPL_INIT_MINIMAL
25 #define CONFIG_SPL_SERIAL_SUPPORT
26 #define CONFIG_SPL_NAND_SUPPORT
27 #define CONFIG_SPL_FLUSH_IMAGE
28 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
29 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
30 
31 #ifdef CONFIG_SPL_BUILD
32 #define CONFIG_NS16550_MIN_FUNCTIONS
33 #endif
34 
35 #define CONFIG_SYS_TEXT_BASE	0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
36 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
37 #define CONFIG_SPL_MAX_SIZE	(4 * 1024)
38 #define CONFIG_SPL_PAD_TO	0x4000
39 
40 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
41 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
42 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
43 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
44 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
45 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
46 
47 #ifdef CONFIG_SPL_BUILD
48 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
49 #endif
50 
51 #endif /* CONFIG_NAND */
52 
53 #ifndef CONFIG_SYS_TEXT_BASE
54 #define CONFIG_SYS_TEXT_BASE	0xFE000000
55 #endif
56 
57 #ifndef CONFIG_SYS_MONITOR_BASE
58 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
59 #endif
60 
61 #define CONFIG_PCI
62 #define CONFIG_PCI_INDIRECT_BRIDGE
63 #define CONFIG_FSL_ELBC 1
64 
65 #define CONFIG_MISC_INIT_R
66 
67 /*
68  * On-board devices
69  *
70  * TSEC1 is VSC switch
71  * TSEC2 is SoC TSEC
72  */
73 #define CONFIG_VSC7385_ENET
74 #define CONFIG_TSEC2
75 
76 #ifdef CONFIG_SYS_66MHZ
77 #define CONFIG_83XX_CLKIN	66666667	/* in Hz */
78 #elif defined(CONFIG_SYS_33MHZ)
79 #define CONFIG_83XX_CLKIN	33333333	/* in Hz */
80 #else
81 #error Unknown oscillator frequency.
82 #endif
83 
84 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
85 
86 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f */
87 #define CONFIG_BOARD_EARLY_INIT_R		/* call board_early_init_r */
88 
89 #define CONFIG_SYS_IMMR		0xE0000000
90 
91 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
92 #define CONFIG_DEFAULT_IMMR	CONFIG_SYS_IMMR
93 #endif
94 
95 #define CONFIG_SYS_MEMTEST_START	0x00001000
96 #define CONFIG_SYS_MEMTEST_END		0x07f00000
97 
98 /* Early revs of this board will lock up hard when attempting
99  * to access the PMC registers, unless a JTAG debugger is
100  * connected, or some resistor modifications are made.
101  */
102 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
103 
104 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
105 #define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
106 
107 /*
108  * Device configurations
109  */
110 
111 /* Vitesse 7385 */
112 
113 #ifdef CONFIG_VSC7385_ENET
114 
115 #define CONFIG_TSEC1
116 
117 /* The flash address and size of the VSC7385 firmware image */
118 #define CONFIG_VSC7385_IMAGE		0xFE7FE000
119 #define CONFIG_VSC7385_IMAGE_SIZE	8192
120 
121 #endif
122 
123 /*
124  * DDR Setup
125  */
126 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory*/
127 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
128 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
129 
130 /*
131  * Manually set up DDR parameters, as this board does not
132  * seem to have the SPD connected to I2C.
133  */
134 #define CONFIG_SYS_DDR_SIZE	128		/* MB */
135 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
136 				| CSCONFIG_ODT_RD_NEVER \
137 				| CSCONFIG_ODT_WR_ONLY_CURRENT \
138 				| CSCONFIG_ROW_BIT_13 \
139 				| CSCONFIG_COL_BIT_10)
140 				/* 0x80010102 */
141 
142 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
143 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
144 				| (0 << TIMING_CFG0_WRT_SHIFT) \
145 				| (0 << TIMING_CFG0_RRT_SHIFT) \
146 				| (0 << TIMING_CFG0_WWT_SHIFT) \
147 				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
148 				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
149 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
150 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
151 				/* 0x00220802 */
152 #define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
153 				| (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
154 				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
155 				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
156 				| (10 << TIMING_CFG1_REFREC_SHIFT) \
157 				| (3 << TIMING_CFG1_WRREC_SHIFT) \
158 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
159 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
160 				/* 0x3835a322 */
161 #define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
162 				| (5 << TIMING_CFG2_CPO_SHIFT) \
163 				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
164 				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
165 				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
166 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
167 				| (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
168 				/* 0x129048c6 */ /* P9-45,may need tuning */
169 #define CONFIG_SYS_DDR_INTERVAL	((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
170 				| (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
171 				/* 0x05100500 */
172 #if defined(CONFIG_DDR_2T_TIMING)
173 #define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
174 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
175 				| SDRAM_CFG_DBW_32 \
176 				| SDRAM_CFG_2T_EN)
177 				/* 0x43088000 */
178 #else
179 #define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
180 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
181 				| SDRAM_CFG_DBW_32)
182 				/* 0x43080000 */
183 #endif
184 #define CONFIG_SYS_SDRAM_CFG2		0x00401000
185 /* set burst length to 8 for 32-bit data path */
186 #define CONFIG_SYS_DDR_MODE	((0x4448 << SDRAM_MODE_ESD_SHIFT) \
187 				| (0x0632 << SDRAM_MODE_SD_SHIFT))
188 				/* 0x44480632 */
189 #define CONFIG_SYS_DDR_MODE_2	0x8000C000
190 
191 #define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
192 				/*0x02000000*/
193 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
194 				| DDRCDR_PZ_NOMZ \
195 				| DDRCDR_NZ_NOMZ \
196 				| DDRCDR_M_ODR)
197 
198 /*
199  * FLASH on the Local Bus
200  */
201 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
202 #define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
203 #define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
204 #define CONFIG_SYS_FLASH_SIZE		8	/* flash size in MB */
205 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
206 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
207 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* buffer up multiple bytes */
208 
209 #define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
210 					| BR_PS_16	/* 16 bit port */ \
211 					| BR_MS_GPCM	/* MSEL = GPCM */ \
212 					| BR_V)		/* valid */
213 #define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
214 				| OR_GPCM_XACS \
215 				| OR_GPCM_SCY_9 \
216 				| OR_GPCM_EHTR \
217 				| OR_GPCM_EAD)
218 				/* 0xFF006FF7	TODO SLOW 16 MB flash size */
219 					/* window base at flash base */
220 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
221 					/* 16 MB window size */
222 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_16MB)
223 
224 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
225 #define CONFIG_SYS_MAX_FLASH_SECT	135	/* sectors per device */
226 
227 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
228 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
229 
230 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
231 	!defined(CONFIG_SPL_BUILD)
232 #define CONFIG_SYS_RAMBOOT
233 #endif
234 
235 #define CONFIG_SYS_INIT_RAM_LOCK	1
236 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
237 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
238 
239 #define CONFIG_SYS_GBL_DATA_OFFSET	\
240 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
241 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
242 
243 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
244 #define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
245 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
246 
247 /*
248  * Local Bus LCRR and LBCR regs
249  */
250 #define CONFIG_SYS_LCRR_EADC	LCRR_EADC_1
251 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
252 #define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
253 				| (0xFF << LBCR_BMT_SHIFT) \
254 				| 0xF)	/* 0x0004ff0f */
255 
256 				/* LB refresh timer prescal, 266MHz/32 */
257 #define CONFIG_SYS_LBC_MRTPR	0x20000000  /*TODO */
258 
259 /* drivers/mtd/nand/nand.c */
260 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
261 #define CONFIG_SYS_NAND_BASE		0xFFF00000
262 #else
263 #define CONFIG_SYS_NAND_BASE		0xE2800000
264 #endif
265 
266 #define CONFIG_MTD_DEVICE
267 #define CONFIG_MTD_PARTITION
268 #define CONFIG_CMD_MTDPARTS
269 #define MTDIDS_DEFAULT			"nand0=e2800000.flash"
270 #define MTDPARTS_DEFAULT		\
271 	"mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
272 
273 #define CONFIG_SYS_MAX_NAND_DEVICE	1
274 #define CONFIG_CMD_NAND 1
275 #define CONFIG_NAND_FSL_ELBC 1
276 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
277 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
278 
279 
280 #define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
281 				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
282 				| BR_PS_8		/* 8 bit port */ \
283 				| BR_MS_FCM		/* MSEL = FCM */ \
284 				| BR_V)			/* valid */
285 #define CONFIG_SYS_NAND_OR_PRELIM	\
286 				(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
287 				| OR_FCM_CSCT \
288 				| OR_FCM_CST \
289 				| OR_FCM_CHT \
290 				| OR_FCM_SCY_1 \
291 				| OR_FCM_TRLX \
292 				| OR_FCM_EHTR)
293 				/* 0xFFFF8396 */
294 
295 #ifdef CONFIG_NAND
296 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
297 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
298 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
299 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
300 #else
301 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
302 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
303 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
304 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
305 #endif
306 
307 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
308 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
309 
310 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
311 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
312 
313 /* local bus write LED / read status buffer (BCSR) mapping */
314 #define CONFIG_SYS_BCSR_ADDR		0xFA000000
315 #define CONFIG_SYS_BCSR_SIZE		(32 * 1024)	/* 0x00008000 */
316 					/* map at 0xFA000000 on LCS3 */
317 #define CONFIG_SYS_BR3_PRELIM		(CONFIG_SYS_BCSR_ADDR \
318 					| BR_PS_8	/* 8 bit port */ \
319 					| BR_MS_GPCM	/* MSEL = GPCM */ \
320 					| BR_V)		/* valid */
321 					/* 0xFA000801 */
322 #define CONFIG_SYS_OR3_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
323 					| OR_GPCM_CSNT \
324 					| OR_GPCM_ACS_DIV2 \
325 					| OR_GPCM_XACS \
326 					| OR_GPCM_SCY_15 \
327 					| OR_GPCM_TRLX_SET \
328 					| OR_GPCM_EHTR_SET \
329 					| OR_GPCM_EAD)
330 					/* 0xFFFF8FF7 */
331 #define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_BCSR_ADDR
332 #define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
333 
334 /* Vitesse 7385 */
335 
336 #ifdef CONFIG_VSC7385_ENET
337 
338 					/* VSC7385 Base address on LCS2 */
339 #define CONFIG_SYS_VSC7385_BASE		0xF0000000
340 #define CONFIG_SYS_VSC7385_SIZE		(128 * 1024)	/* 0x00020000 */
341 
342 #define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VSC7385_BASE \
343 					| BR_PS_8	/* 8 bit port */ \
344 					| BR_MS_GPCM	/* MSEL = GPCM */ \
345 					| BR_V)		/* valid */
346 #define CONFIG_SYS_OR2_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
347 					| OR_GPCM_CSNT \
348 					| OR_GPCM_XACS \
349 					| OR_GPCM_SCY_15 \
350 					| OR_GPCM_SETA \
351 					| OR_GPCM_TRLX_SET \
352 					| OR_GPCM_EHTR_SET \
353 					| OR_GPCM_EAD)
354 					/* 0xFFFE09FF */
355 
356 					/* Access window base at VSC7385 base */
357 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
358 #define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
359 
360 #endif
361 
362 #define CONFIG_MPC83XX_GPIO 1
363 
364 /*
365  * Serial Port
366  */
367 #define CONFIG_CONS_INDEX	1
368 #define CONFIG_SYS_NS16550_SERIAL
369 #define CONFIG_SYS_NS16550_REG_SIZE	1
370 
371 #define CONFIG_SYS_BAUDRATE_TABLE	\
372 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
373 
374 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
375 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
376 
377 /* Use the HUSH parser */
378 #define CONFIG_SYS_HUSH_PARSER
379 
380 /* I2C */
381 #define CONFIG_SYS_I2C
382 #define CONFIG_SYS_I2C_FSL
383 #define CONFIG_SYS_FSL_I2C_SPEED	400000
384 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
385 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
386 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
387 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
388 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
389 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
390 
391 /*
392  * General PCI
393  * Addresses are mapped 1-1.
394  */
395 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
396 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
397 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
398 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
399 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
400 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
401 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
402 #define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
403 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
404 
405 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
406 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
407 
408 /*
409  * TSEC
410  */
411 #define CONFIG_TSEC_ENET		/* TSEC ethernet support */
412 
413 #define CONFIG_GMII			/* MII PHY management */
414 
415 #ifdef CONFIG_TSEC1
416 #define CONFIG_HAS_ETH0
417 #define CONFIG_TSEC1_NAME	"TSEC0"
418 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
419 #define TSEC1_PHY_ADDR		0x1c
420 #define TSEC1_FLAGS		TSEC_GIGABIT
421 #define TSEC1_PHYIDX		0
422 #endif
423 
424 #ifdef CONFIG_TSEC2
425 #define CONFIG_HAS_ETH1
426 #define CONFIG_TSEC2_NAME	"TSEC1"
427 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
428 #define TSEC2_PHY_ADDR		4
429 #define TSEC2_FLAGS		TSEC_GIGABIT
430 #define TSEC2_PHYIDX		0
431 #endif
432 
433 
434 /* Options are: TSEC[0-1] */
435 #define CONFIG_ETHPRIME			"TSEC1"
436 
437 /*
438  * Configure on-board RTC
439  */
440 #define CONFIG_RTC_DS1337
441 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
442 
443 /*
444  * Environment
445  */
446 #if defined(CONFIG_NAND)
447 	#define CONFIG_ENV_IS_IN_NAND	1
448 	#define CONFIG_ENV_OFFSET		(512 * 1024)
449 	#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
450 	#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
451 	#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
452 	#define CONFIG_ENV_RANGE		(CONFIG_ENV_SECT_SIZE * 4)
453 	#define CONFIG_ENV_OFFSET_REDUND	\
454 					(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
455 #elif !defined(CONFIG_SYS_RAMBOOT)
456 	#define CONFIG_ENV_IS_IN_FLASH	1
457 	#define CONFIG_ENV_ADDR		\
458 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
459 	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
460 	#define CONFIG_ENV_SIZE		0x2000
461 
462 /* Address and size of Redundant Environment Sector */
463 #else
464 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
465 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
466 	#define CONFIG_ENV_SIZE		0x2000
467 #endif
468 
469 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
470 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
471 
472 /*
473  * BOOTP options
474  */
475 #define CONFIG_BOOTP_BOOTFILESIZE
476 #define CONFIG_BOOTP_BOOTPATH
477 #define CONFIG_BOOTP_GATEWAY
478 #define CONFIG_BOOTP_HOSTNAME
479 
480 
481 /*
482  * Command line configuration.
483  */
484 #define CONFIG_CMD_PING
485 #define CONFIG_CMD_DHCP
486 #define CONFIG_CMD_I2C
487 #define CONFIG_CMD_MII
488 #define CONFIG_CMD_DATE
489 #define CONFIG_CMD_PCI
490 
491 #define CONFIG_CMDLINE_EDITING 1
492 #define CONFIG_AUTO_COMPLETE	/* add autocompletion support   */
493 
494 /*
495  * Miscellaneous configurable options
496  */
497 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
498 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
499 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
500 
501 						/* Print Buffer Size */
502 #define CONFIG_SYS_PBSIZE	\
503 			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
504 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
505 				/* Boot Argument Buffer Size */
506 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
507 
508 /*
509  * For booting Linux, the board info and command line data
510  * have to be in the first 256 MB of memory, since this is
511  * the maximum mapped by the Linux kernel during initialization.
512  */
513 				/* Initial Memory map for Linux*/
514 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
515 
516 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000	/* PCIHOST  */
517 
518 #ifdef CONFIG_SYS_66MHZ
519 
520 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
521 /* 0x62040000 */
522 #define CONFIG_SYS_HRCW_LOW (\
523 	0x20000000 /* reserved, must be set */ |\
524 	HRCWL_DDRCM |\
525 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
526 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
527 	HRCWL_CSB_TO_CLKIN_2X1 |\
528 	HRCWL_CORE_TO_CSB_2X1)
529 
530 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
531 
532 #elif defined(CONFIG_SYS_33MHZ)
533 
534 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
535 /* 0x65040000 */
536 #define CONFIG_SYS_HRCW_LOW (\
537 	0x20000000 /* reserved, must be set */ |\
538 	HRCWL_DDRCM |\
539 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
540 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
541 	HRCWL_CSB_TO_CLKIN_5X1 |\
542 	HRCWL_CORE_TO_CSB_2X1)
543 
544 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
545 
546 #endif
547 
548 #define CONFIG_SYS_HRCW_HIGH_BASE (\
549 	HRCWH_PCI_HOST |\
550 	HRCWH_PCI1_ARBITER_ENABLE |\
551 	HRCWH_CORE_ENABLE |\
552 	HRCWH_BOOTSEQ_DISABLE |\
553 	HRCWH_SW_WATCHDOG_DISABLE |\
554 	HRCWH_TSEC1M_IN_RGMII |\
555 	HRCWH_TSEC2M_IN_RGMII |\
556 	HRCWH_BIG_ENDIAN)
557 
558 #ifdef CONFIG_NAND
559 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
560 		       HRCWH_FROM_0XFFF00100 |\
561 		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
562 		       HRCWH_RL_EXT_NAND)
563 #else
564 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
565 		       HRCWH_FROM_0X00000100 |\
566 		       HRCWH_ROM_LOC_LOCAL_16BIT |\
567 		       HRCWH_RL_EXT_LEGACY)
568 #endif
569 
570 /* System IO Config */
571 #define CONFIG_SYS_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
572 			/* Enable Internal USB Phy and GPIO on LCD Connector */
573 #define CONFIG_SYS_SICRL	(SICRL_USBDR_10 | SICRL_LBC)
574 
575 #define CONFIG_SYS_HID0_INIT	0x000000000
576 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
577 				 HID0_ENABLE_INSTRUCTION_CACHE | \
578 				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
579 
580 #define CONFIG_SYS_HID2 HID2_HBE
581 
582 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
583 
584 /* DDR @ 0x00000000 */
585 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
586 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
587 				| BATU_BL_256M \
588 				| BATU_VS \
589 				| BATU_VP)
590 
591 /* PCI @ 0x80000000 */
592 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
593 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
594 				| BATU_BL_256M \
595 				| BATU_VS \
596 				| BATU_VP)
597 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
598 				| BATL_PP_RW \
599 				| BATL_CACHEINHIBIT \
600 				| BATL_GUARDEDSTORAGE)
601 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
602 				| BATU_BL_256M \
603 				| BATU_VS \
604 				| BATU_VP)
605 
606 /* PCI2 not supported on 8313 */
607 #define CONFIG_SYS_IBAT3L	(0)
608 #define CONFIG_SYS_IBAT3U	(0)
609 #define CONFIG_SYS_IBAT4L	(0)
610 #define CONFIG_SYS_IBAT4U	(0)
611 
612 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
613 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
614 				| BATL_PP_RW \
615 				| BATL_CACHEINHIBIT \
616 				| BATL_GUARDEDSTORAGE)
617 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
618 				| BATU_BL_256M \
619 				| BATU_VS \
620 				| BATU_VP)
621 
622 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
623 #define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
624 #define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
625 
626 #define CONFIG_SYS_IBAT7L	(0)
627 #define CONFIG_SYS_IBAT7U	(0)
628 
629 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
630 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
631 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
632 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
633 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
634 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
635 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
636 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
637 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
638 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
639 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
640 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
641 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
642 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
643 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
644 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
645 
646 /*
647  * Environment Configuration
648  */
649 #define CONFIG_ENV_OVERWRITE
650 
651 #define CONFIG_NETDEV		"eth1"
652 
653 #define CONFIG_HOSTNAME		mpc8313erdb
654 #define CONFIG_ROOTPATH		"/nfs/root/path"
655 #define CONFIG_BOOTFILE		"uImage"
656 				/* U-Boot image on TFTP server */
657 #define CONFIG_UBOOTPATH	"u-boot.bin"
658 #define CONFIG_FDTFILE		"mpc8313erdb.dtb"
659 
660 				/* default location for tftp and bootm */
661 #define CONFIG_LOADADDR		800000
662 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
663 #define CONFIG_BAUDRATE		115200
664 
665 #define CONFIG_EXTRA_ENV_SETTINGS \
666 	"netdev=" CONFIG_NETDEV "\0"					\
667 	"ethprime=TSEC1\0"						\
668 	"uboot=" CONFIG_UBOOTPATH "\0"					\
669 	"tftpflash=tftpboot $loadaddr $uboot; "				\
670 		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
671 			" +$filesize; "	\
672 		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
673 			" +$filesize; "	\
674 		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
675 			" $filesize; "	\
676 		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
677 			" +$filesize; "	\
678 		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
679 			" $filesize\0"	\
680 	"fdtaddr=780000\0"						\
681 	"fdtfile=" CONFIG_FDTFILE "\0"					\
682 	"console=ttyS0\0"						\
683 	"setbootargs=setenv bootargs "					\
684 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
685 	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	 \
686 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
687 							"$netdev:off " \
688 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
689 
690 #define CONFIG_NFSBOOTCOMMAND						\
691 	"setenv rootdev /dev/nfs;"					\
692 	"run setbootargs;"						\
693 	"run setipargs;"						\
694 	"tftp $loadaddr $bootfile;"					\
695 	"tftp $fdtaddr $fdtfile;"					\
696 	"bootm $loadaddr - $fdtaddr"
697 
698 #define CONFIG_RAMBOOTCOMMAND						\
699 	"setenv rootdev /dev/ram;"					\
700 	"run setbootargs;"						\
701 	"tftp $ramdiskaddr $ramdiskfile;"				\
702 	"tftp $loadaddr $bootfile;"					\
703 	"tftp $fdtaddr $fdtfile;"					\
704 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
705 
706 #endif	/* __CONFIG_H */
707