xref: /openbmc/u-boot/include/configs/MPC8313ERDB.h (revision 284170309cab2006e7730c65454458680921b16a)
1 /*
2  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 /*
23  * mpc8313epb board configuration file
24  */
25 
26 #ifndef __CONFIG_H
27 #define __CONFIG_H
28 
29 /*
30  * High Level Configuration Options
31  */
32 #define CONFIG_E300		1
33 #define CONFIG_MPC83xx		1
34 #define CONFIG_MPC831x		1
35 #define CONFIG_MPC8313		1
36 #define CONFIG_MPC8313ERDB	1
37 
38 #ifndef CONFIG_SYS_TEXT_BASE
39 #define CONFIG_SYS_TEXT_BASE	0xFE000000
40 #endif
41 
42 #define CONFIG_PCI
43 #define CONFIG_FSL_ELBC 1
44 
45 #define CONFIG_MISC_INIT_R
46 
47 /*
48  * On-board devices
49  *
50  * TSEC1 is VSC switch
51  * TSEC2 is SoC TSEC
52  */
53 #define CONFIG_VSC7385_ENET
54 #define CONFIG_TSEC2
55 
56 #ifdef CONFIG_SYS_66MHZ
57 #define CONFIG_83XX_CLKIN	66666667	/* in Hz */
58 #elif defined(CONFIG_SYS_33MHZ)
59 #define CONFIG_83XX_CLKIN	33333333	/* in Hz */
60 #else
61 #error Unknown oscillator frequency.
62 #endif
63 
64 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
65 
66 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
67 
68 #define CONFIG_SYS_IMMR		0xE0000000
69 
70 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
71 #define CONFIG_DEFAULT_IMMR	CONFIG_SYS_IMMR
72 #endif
73 
74 #define CONFIG_SYS_MEMTEST_START	0x00001000
75 #define CONFIG_SYS_MEMTEST_END		0x07f00000
76 
77 /* Early revs of this board will lock up hard when attempting
78  * to access the PMC registers, unless a JTAG debugger is
79  * connected, or some resistor modifications are made.
80  */
81 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
82 
83 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
84 #define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
85 
86 /*
87  * Device configurations
88  */
89 
90 /* Vitesse 7385 */
91 
92 #ifdef CONFIG_VSC7385_ENET
93 
94 #define CONFIG_TSEC1
95 
96 /* The flash address and size of the VSC7385 firmware image */
97 #define CONFIG_VSC7385_IMAGE		0xFE7FE000
98 #define CONFIG_VSC7385_IMAGE_SIZE	8192
99 
100 #endif
101 
102 /*
103  * DDR Setup
104  */
105 #define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
106 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
107 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
108 
109 /*
110  * Manually set up DDR parameters, as this board does not
111  * seem to have the SPD connected to I2C.
112  */
113 #define CONFIG_SYS_DDR_SIZE		128		/* MB */
114 #define CONFIG_SYS_DDR_CONFIG		( CSCONFIG_EN \
115 				| 0x00010000 /* TODO */ \
116 				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
117 				/* 0x80010102 */
118 
119 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
120 #define CONFIG_SYS_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
121 				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
122 				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
123 				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
124 				| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
125 				| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
126 				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
127 				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
128 				/* 0x00220802 */
129 #define CONFIG_SYS_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
130 				| ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
131 				| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
132 				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
133 				| (10 << TIMING_CFG1_REFREC_SHIFT ) \
134 				| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
135 				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
136 				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
137 				/* 0x3835a322 */
138 #define CONFIG_SYS_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
139 				| ( 5 << TIMING_CFG2_CPO_SHIFT ) \
140 				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
141 				| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
142 				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
143 				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
144 				| ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) )
145 				/* 0x129048c6 */ /* P9-45,may need tuning */
146 #define CONFIG_SYS_DDR_INTERVAL	( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \
147 				| ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
148 				/* 0x05100500 */
149 #if defined(CONFIG_DDR_2T_TIMING)
150 #define CONFIG_SYS_SDRAM_CFG		( SDRAM_CFG_SREN \
151 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
152 				| SDRAM_CFG_2T_EN \
153 				| SDRAM_CFG_DBW_32 )
154 #else
155 #define CONFIG_SYS_SDRAM_CFG		( SDRAM_CFG_SREN \
156 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
157 				| SDRAM_CFG_32_BE )
158 				/* 0x43080000 */
159 #endif
160 #define CONFIG_SYS_SDRAM_CFG2		0x00401000
161 /* set burst length to 8 for 32-bit data path */
162 #define CONFIG_SYS_DDR_MODE		( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
163 				| ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
164 				/* 0x44480632 */
165 #define CONFIG_SYS_DDR_MODE_2		0x8000C000
166 
167 #define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
168 				/*0x02000000*/
169 #define CONFIG_SYS_DDRCDR_VALUE	( DDRCDR_EN \
170 				| DDRCDR_PZ_NOMZ \
171 				| DDRCDR_NZ_NOMZ \
172 				| DDRCDR_M_ODR )
173 
174 /*
175  * FLASH on the Local Bus
176  */
177 #define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
178 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
179 #define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
180 #define CONFIG_SYS_FLASH_SIZE		8		/* flash size in MB */
181 #define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
182 #define CONFIG_SYS_FLASH_EMPTY_INFO			/* display empty sectors */
183 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE		/* buffer up multiple bytes */
184 
185 #define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE |	/* flash Base address */ \
186 				(2 << BR_PS_SHIFT) |	/* 16 bit port size */ \
187 				BR_V)			/* valid */
188 #define CONFIG_SYS_NOR_OR_PRELIM	( 0xFF800000		/* 8 MByte */ \
189 				| OR_GPCM_XACS \
190 				| OR_GPCM_SCY_9 \
191 				| OR_GPCM_EHTR \
192 				| OR_GPCM_EAD )
193 				/* 0xFF006FF7	TODO SLOW 16 MB flash size */
194 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE	/* window base at flash base */
195 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000017	/* 16 MB window size */
196 
197 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
198 #define CONFIG_SYS_MAX_FLASH_SECT	135		/* sectors per device */
199 
200 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
201 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
202 
203 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
204 
205 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_SPL)
206 #define CONFIG_SYS_RAMBOOT
207 #endif
208 
209 #define CONFIG_SYS_INIT_RAM_LOCK	1
210 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
211 #define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
212 
213 #define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
214 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
215 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
216 
217 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
218 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Mon */
219 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */
220 
221 /*
222  * Local Bus LCRR and LBCR regs
223  */
224 #define CONFIG_SYS_LCRR_EADC	LCRR_EADC_1
225 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
226 #define CONFIG_SYS_LBC_LBCR	( 0x00040000 /* TODO */ \
227 			| (0xFF << LBCR_BMT_SHIFT) \
228 			| 0xF )	/* 0x0004ff0f */
229 
230 #define CONFIG_SYS_LBC_MRTPR	0x20000000  /*TODO */	/* LB refresh timer prescal, 266MHz/32 */
231 
232 /* drivers/mtd/nand/nand.c */
233 #ifdef CONFIG_NAND_SPL
234 #define CONFIG_SYS_NAND_BASE		0xFFF00000
235 #else
236 #define CONFIG_SYS_NAND_BASE		0xE2800000
237 #endif
238 
239 #define CONFIG_MTD_DEVICE
240 #define CONFIG_MTD_PARTITION
241 #define CONFIG_CMD_MTDPARTS
242 #define MTDIDS_DEFAULT			"nand0=e2800000.flash"
243 #define MTDPARTS_DEFAULT 		\
244 	"mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
245 
246 #define CONFIG_SYS_MAX_NAND_DEVICE	1
247 #define CONFIG_MTD_NAND_VERIFY_WRITE
248 #define CONFIG_CMD_NAND 1
249 #define CONFIG_NAND_FSL_ELBC 1
250 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
251 
252 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
253 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
254 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
255 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
256 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
257 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
258 
259 #define CONFIG_SYS_NAND_BR_PRELIM	( CONFIG_SYS_NAND_BASE \
260 				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
261 				| BR_PS_8		/* Port Size = 8 bit */ \
262 				| BR_MS_FCM		/* MSEL = FCM */ \
263 				| BR_V )		/* valid */
264 #define CONFIG_SYS_NAND_OR_PRELIM	( 0xFFFF8000		/* length 32K */ \
265 				| OR_FCM_CSCT \
266 				| OR_FCM_CST \
267 				| OR_FCM_CHT \
268 				| OR_FCM_SCY_1 \
269 				| OR_FCM_TRLX \
270 				| OR_FCM_EHTR )
271 				/* 0xFFFF8396 */
272 
273 #ifdef CONFIG_NAND_U_BOOT
274 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
275 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
276 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
277 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
278 #else
279 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
280 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
281 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
282 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
283 #endif
284 
285 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
286 #define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
287 
288 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
289 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
290 
291 /* local bus read write buffer mapping */
292 #define CONFIG_SYS_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
293 #define CONFIG_SYS_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
294 #define CONFIG_SYS_LBLAWBAR3_PRELIM	0xFA000000
295 #define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
296 
297 /* Vitesse 7385 */
298 
299 #define CONFIG_SYS_VSC7385_BASE	0xF0000000
300 
301 #ifdef CONFIG_VSC7385_ENET
302 
303 #define CONFIG_SYS_BR2_PRELIM		0xf0000801	/* VSC7385 Base address */
304 #define CONFIG_SYS_OR2_PRELIM		0xfffe09ff	/* VSC7385, 128K bytes*/
305 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE/* Access window base at VSC7385 base */
306 #define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000010	/* Access window size 128K */
307 
308 #endif
309 
310 /* pass open firmware flat tree */
311 #define CONFIG_OF_LIBFDT	1
312 #define CONFIG_OF_BOARD_SETUP	1
313 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
314 
315 /*
316  * Serial Port
317  */
318 #define CONFIG_CONS_INDEX	1
319 #define CONFIG_SYS_NS16550
320 #define CONFIG_SYS_NS16550_SERIAL
321 #define CONFIG_SYS_NS16550_REG_SIZE	1
322 
323 #define CONFIG_SYS_BAUDRATE_TABLE	\
324 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
325 
326 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
327 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
328 
329 /* Use the HUSH parser */
330 #define CONFIG_SYS_HUSH_PARSER
331 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
332 
333 /* I2C */
334 #define CONFIG_HARD_I2C			/* I2C with hardware support*/
335 #define CONFIG_FSL_I2C
336 #define CONFIG_I2C_MULTI_BUS
337 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
338 #define CONFIG_SYS_I2C_SLAVE		0x7F
339 #define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}} /* Don't probe these addrs */
340 #define CONFIG_SYS_I2C_OFFSET		0x3000
341 #define CONFIG_SYS_I2C2_OFFSET		0x3100
342 
343 /*
344  * General PCI
345  * Addresses are mapped 1-1.
346  */
347 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
348 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
349 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
350 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
351 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
352 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
353 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
354 #define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
355 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
356 
357 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
358 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
359 
360 /*
361  * TSEC
362  */
363 #define CONFIG_TSEC_ENET		/* TSEC ethernet support */
364 
365 #define CONFIG_NET_MULTI
366 #define CONFIG_GMII			/* MII PHY management */
367 
368 #ifdef CONFIG_TSEC1
369 #define CONFIG_HAS_ETH0
370 #define CONFIG_TSEC1_NAME	"TSEC0"
371 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
372 #define TSEC1_PHY_ADDR		0x1c
373 #define TSEC1_FLAGS		TSEC_GIGABIT
374 #define TSEC1_PHYIDX		0
375 #endif
376 
377 #ifdef CONFIG_TSEC2
378 #define CONFIG_HAS_ETH1
379 #define CONFIG_TSEC2_NAME	"TSEC1"
380 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
381 #define TSEC2_PHY_ADDR		4
382 #define TSEC2_FLAGS		TSEC_GIGABIT
383 #define TSEC2_PHYIDX		0
384 #endif
385 
386 
387 /* Options are: TSEC[0-1] */
388 #define CONFIG_ETHPRIME			"TSEC1"
389 
390 /*
391  * Configure on-board RTC
392  */
393 #define CONFIG_RTC_DS1337
394 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
395 
396 /*
397  * Environment
398  */
399 #if defined(CONFIG_NAND_U_BOOT)
400 	#define CONFIG_ENV_IS_IN_NAND	1
401 	#define CONFIG_ENV_OFFSET		(512 * 1024)
402 	#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
403 	#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
404 	#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
405 	#define CONFIG_ENV_RANGE		(CONFIG_ENV_SECT_SIZE * 4)
406 	#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
407 #elif !defined(CONFIG_SYS_RAMBOOT)
408 	#define CONFIG_ENV_IS_IN_FLASH	1
409 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
410 	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
411 	#define CONFIG_ENV_SIZE		0x2000
412 
413 /* Address and size of Redundant Environment Sector */
414 #else
415 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
416 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
417 	#define CONFIG_ENV_SIZE		0x2000
418 #endif
419 
420 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
421 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
422 
423 /*
424  * BOOTP options
425  */
426 #define CONFIG_BOOTP_BOOTFILESIZE
427 #define CONFIG_BOOTP_BOOTPATH
428 #define CONFIG_BOOTP_GATEWAY
429 #define CONFIG_BOOTP_HOSTNAME
430 
431 
432 /*
433  * Command line configuration.
434  */
435 #include <config_cmd_default.h>
436 
437 #define CONFIG_CMD_PING
438 #define CONFIG_CMD_DHCP
439 #define CONFIG_CMD_I2C
440 #define CONFIG_CMD_MII
441 #define CONFIG_CMD_DATE
442 #define CONFIG_CMD_PCI
443 
444 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
445     #undef CONFIG_CMD_SAVEENV
446     #undef CONFIG_CMD_LOADS
447 #endif
448 
449 #define CONFIG_CMDLINE_EDITING 1
450 #define CONFIG_AUTO_COMPLETE	/* add autocompletion support   */
451 
452 /*
453  * Miscellaneous configurable options
454  */
455 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
456 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
457 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
458 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
459 
460 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
461 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
462 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
463 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
464 
465 /*
466  * For booting Linux, the board info and command line data
467  * have to be in the first 256 MB of memory, since this is
468  * the maximum mapped by the Linux kernel during initialization.
469  */
470 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
471 
472 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000	/* PCIHOST  */
473 
474 #ifdef CONFIG_SYS_66MHZ
475 
476 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
477 /* 0x62040000 */
478 #define CONFIG_SYS_HRCW_LOW (\
479 	0x20000000 /* reserved, must be set */ |\
480 	HRCWL_DDRCM |\
481 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
482 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
483 	HRCWL_CSB_TO_CLKIN_2X1 |\
484 	HRCWL_CORE_TO_CSB_2X1)
485 
486 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
487 
488 #elif defined(CONFIG_SYS_33MHZ)
489 
490 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
491 /* 0x65040000 */
492 #define CONFIG_SYS_HRCW_LOW (\
493 	0x20000000 /* reserved, must be set */ |\
494 	HRCWL_DDRCM |\
495 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
496 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
497 	HRCWL_CSB_TO_CLKIN_5X1 |\
498 	HRCWL_CORE_TO_CSB_2X1)
499 
500 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
501 
502 #endif
503 
504 #define CONFIG_SYS_HRCW_HIGH_BASE (\
505 	HRCWH_PCI_HOST |\
506 	HRCWH_PCI1_ARBITER_ENABLE |\
507 	HRCWH_CORE_ENABLE |\
508 	HRCWH_BOOTSEQ_DISABLE |\
509 	HRCWH_SW_WATCHDOG_DISABLE |\
510 	HRCWH_TSEC1M_IN_RGMII |\
511 	HRCWH_TSEC2M_IN_RGMII |\
512 	HRCWH_BIG_ENDIAN)
513 
514 #ifdef CONFIG_NAND_SPL
515 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
516 		       HRCWH_FROM_0XFFF00100 |\
517 		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
518 		       HRCWH_RL_EXT_NAND)
519 #else
520 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
521 		       HRCWH_FROM_0X00000100 |\
522 		       HRCWH_ROM_LOC_LOCAL_16BIT |\
523 		       HRCWH_RL_EXT_LEGACY)
524 #endif
525 
526 /* System IO Config */
527 #define CONFIG_SYS_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
528 #define CONFIG_SYS_SICRL	SICRL_USBDR_10			/* Enable Internal USB Phy  */
529 
530 #define CONFIG_SYS_HID0_INIT	0x000000000
531 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
532 				 HID0_ENABLE_INSTRUCTION_CACHE | \
533 				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
534 
535 #define CONFIG_SYS_HID2 HID2_HBE
536 
537 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
538 
539 /* DDR @ 0x00000000 */
540 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
541 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
542 
543 /* PCI @ 0x80000000 */
544 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
545 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
546 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
547 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
548 
549 /* PCI2 not supported on 8313 */
550 #define CONFIG_SYS_IBAT3L	(0)
551 #define CONFIG_SYS_IBAT3U	(0)
552 #define CONFIG_SYS_IBAT4L	(0)
553 #define CONFIG_SYS_IBAT4U	(0)
554 
555 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
556 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
557 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
558 
559 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
560 #define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
561 #define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
562 
563 #define CONFIG_SYS_IBAT7L	(0)
564 #define CONFIG_SYS_IBAT7U	(0)
565 
566 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
567 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
568 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
569 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
570 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
571 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
572 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
573 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
574 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
575 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
576 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
577 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
578 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
579 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
580 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
581 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
582 
583 /*
584  * Environment Configuration
585  */
586 #define CONFIG_ENV_OVERWRITE
587 
588 #define CONFIG_NETDEV		eth1
589 
590 #define CONFIG_HOSTNAME		mpc8313erdb
591 #define CONFIG_ROOTPATH		/nfs/root/path
592 #define CONFIG_BOOTFILE		uImage
593 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
594 #define CONFIG_FDTFILE		mpc8313erdb.dtb
595 
596 #define CONFIG_LOADADDR		800000	/* default location for tftp and bootm */
597 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
598 #define CONFIG_BAUDRATE		115200
599 
600 #define XMK_STR(x)	#x
601 #define MK_STR(x)	XMK_STR(x)
602 
603 #define CONFIG_EXTRA_ENV_SETTINGS \
604 	"netdev=" MK_STR(CONFIG_NETDEV) "\0"				\
605 	"ethprime=TSEC1\0"						\
606 	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
607 	"tftpflash=tftpboot $loadaddr $uboot; "				\
608 		"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
609 		"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "		\
610 		"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "	\
611 		"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "		\
612 		"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"	\
613 	"fdtaddr=780000\0"						\
614 	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
615 	"console=ttyS0\0"						\
616 	"setbootargs=setenv bootargs "					\
617 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
618 	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	 \
619 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
620 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
621 
622 #define CONFIG_NFSBOOTCOMMAND						\
623 	"setenv rootdev /dev/nfs;"					\
624 	"run setbootargs;"						\
625 	"run setipargs;"						\
626 	"tftp $loadaddr $bootfile;"					\
627 	"tftp $fdtaddr $fdtfile;"					\
628 	"bootm $loadaddr - $fdtaddr"
629 
630 #define CONFIG_RAMBOOTCOMMAND						\
631 	"setenv rootdev /dev/ram;"					\
632 	"run setbootargs;"						\
633 	"tftp $ramdiskaddr $ramdiskfile;"				\
634 	"tftp $loadaddr $bootfile;"					\
635 	"tftp $fdtaddr $fdtfile;"					\
636 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
637 
638 #undef MK_STR
639 #undef XMK_STR
640 
641 #endif	/* __CONFIG_H */
642