1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 /* 23 * mpc8313epb board configuration file 24 */ 25 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* 30 * High Level Configuration Options 31 */ 32 #define CONFIG_E300 1 33 #define CONFIG_MPC83xx 1 34 #define CONFIG_MPC831x 1 35 #define CONFIG_MPC8313 1 36 #define CONFIG_MPC8313ERDB 1 37 38 #ifndef CONFIG_SYS_TEXT_BASE 39 #define CONFIG_SYS_TEXT_BASE 0xFE000000 40 #endif 41 42 #define CONFIG_PCI 43 #define CONFIG_FSL_ELBC 1 44 45 #define CONFIG_MISC_INIT_R 46 47 /* 48 * On-board devices 49 * 50 * TSEC1 is VSC switch 51 * TSEC2 is SoC TSEC 52 */ 53 #define CONFIG_VSC7385_ENET 54 #define CONFIG_TSEC2 55 56 #ifdef CONFIG_SYS_66MHZ 57 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 58 #elif defined(CONFIG_SYS_33MHZ) 59 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 60 #else 61 #error Unknown oscillator frequency. 62 #endif 63 64 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 65 66 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 67 68 #define CONFIG_SYS_IMMR 0xE0000000 69 70 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 71 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 72 #endif 73 74 #define CONFIG_SYS_MEMTEST_START 0x00001000 75 #define CONFIG_SYS_MEMTEST_END 0x07f00000 76 77 /* Early revs of this board will lock up hard when attempting 78 * to access the PMC registers, unless a JTAG debugger is 79 * connected, or some resistor modifications are made. 80 */ 81 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 82 83 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 84 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 85 86 /* 87 * Device configurations 88 */ 89 90 /* Vitesse 7385 */ 91 92 #ifdef CONFIG_VSC7385_ENET 93 94 #define CONFIG_TSEC1 95 96 /* The flash address and size of the VSC7385 firmware image */ 97 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 98 #define CONFIG_VSC7385_IMAGE_SIZE 8192 99 100 #endif 101 102 /* 103 * DDR Setup 104 */ 105 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 106 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 107 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 108 109 /* 110 * Manually set up DDR parameters, as this board does not 111 * seem to have the SPD connected to I2C. 112 */ 113 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 114 #define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \ 115 | 0x00010000 /* TODO */ \ 116 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) 117 /* 0x80010102 */ 118 119 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 120 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 121 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 122 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 123 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 124 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 125 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 126 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 127 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 128 /* 0x00220802 */ 129 #define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ 130 | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 131 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ 132 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 133 | (10 << TIMING_CFG1_REFREC_SHIFT ) \ 134 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ 135 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 136 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 137 /* 0x3835a322 */ 138 #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 139 | ( 5 << TIMING_CFG2_CPO_SHIFT ) \ 140 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 141 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 142 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 143 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 144 | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 145 /* 0x129048c6 */ /* P9-45,may need tuning */ 146 #define CONFIG_SYS_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 147 | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 148 /* 0x05100500 */ 149 #if defined(CONFIG_DDR_2T_TIMING) 150 #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ 151 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 152 | SDRAM_CFG_2T_EN \ 153 | SDRAM_CFG_DBW_32 ) 154 #else 155 #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ 156 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 157 | SDRAM_CFG_32_BE ) 158 /* 0x43080000 */ 159 #endif 160 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 161 /* set burst length to 8 for 32-bit data path */ 162 #define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ 163 | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) ) 164 /* 0x44480632 */ 165 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 166 167 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 168 /*0x02000000*/ 169 #define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \ 170 | DDRCDR_PZ_NOMZ \ 171 | DDRCDR_NZ_NOMZ \ 172 | DDRCDR_M_ODR ) 173 174 /* 175 * FLASH on the Local Bus 176 */ 177 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 178 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 179 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 180 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 181 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 182 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 183 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 184 185 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ 186 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 187 BR_V) /* valid */ 188 #define CONFIG_SYS_NOR_OR_PRELIM ( 0xFF800000 /* 8 MByte */ \ 189 | OR_GPCM_XACS \ 190 | OR_GPCM_SCY_9 \ 191 | OR_GPCM_EHTR \ 192 | OR_GPCM_EAD ) 193 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 194 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ 195 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ 196 197 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 198 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 199 200 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 201 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 202 203 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 204 205 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_SPL) 206 #define CONFIG_SYS_RAMBOOT 207 #endif 208 209 #define CONFIG_SYS_INIT_RAM_LOCK 1 210 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 211 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 212 213 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 214 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 215 216 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 217 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 218 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 219 220 /* 221 * Local Bus LCRR and LBCR regs 222 */ 223 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 224 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 225 #define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \ 226 | (0xFF << LBCR_BMT_SHIFT) \ 227 | 0xF ) /* 0x0004ff0f */ 228 229 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ 230 231 /* drivers/mtd/nand/nand.c */ 232 #ifdef CONFIG_NAND_SPL 233 #define CONFIG_SYS_NAND_BASE 0xFFF00000 234 #else 235 #define CONFIG_SYS_NAND_BASE 0xE2800000 236 #endif 237 238 #define CONFIG_MTD_DEVICE 239 #define CONFIG_MTD_PARTITION 240 #define CONFIG_CMD_MTDPARTS 241 #define MTDIDS_DEFAULT "nand0=e2800000.flash" 242 #define MTDPARTS_DEFAULT \ 243 "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" 244 245 #define CONFIG_SYS_MAX_NAND_DEVICE 1 246 #define CONFIG_MTD_NAND_VERIFY_WRITE 247 #define CONFIG_CMD_NAND 1 248 #define CONFIG_NAND_FSL_ELBC 1 249 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 250 251 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 252 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 253 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 254 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 255 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 256 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 257 258 #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ 259 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 260 | BR_PS_8 /* Port Size = 8 bit */ \ 261 | BR_MS_FCM /* MSEL = FCM */ \ 262 | BR_V ) /* valid */ 263 #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \ 264 | OR_FCM_CSCT \ 265 | OR_FCM_CST \ 266 | OR_FCM_CHT \ 267 | OR_FCM_SCY_1 \ 268 | OR_FCM_TRLX \ 269 | OR_FCM_EHTR ) 270 /* 0xFFFF8396 */ 271 272 #ifdef CONFIG_NAND_U_BOOT 273 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 274 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 275 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 276 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 277 #else 278 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 279 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 280 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 281 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 282 #endif 283 284 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 285 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 286 287 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 288 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 289 290 /* local bus read write buffer mapping */ 291 #define CONFIG_SYS_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ 292 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ 293 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xFA000000 294 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 295 296 /* Vitesse 7385 */ 297 298 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 299 300 #ifdef CONFIG_VSC7385_ENET 301 302 #define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ 303 #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ 304 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE/* Access window base at VSC7385 base */ 305 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ 306 307 #endif 308 309 /* pass open firmware flat tree */ 310 #define CONFIG_OF_LIBFDT 1 311 #define CONFIG_OF_BOARD_SETUP 1 312 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 313 314 /* 315 * Serial Port 316 */ 317 #define CONFIG_CONS_INDEX 1 318 #define CONFIG_SYS_NS16550 319 #define CONFIG_SYS_NS16550_SERIAL 320 #define CONFIG_SYS_NS16550_REG_SIZE 1 321 322 #define CONFIG_SYS_BAUDRATE_TABLE \ 323 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 324 325 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 326 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 327 328 /* Use the HUSH parser */ 329 #define CONFIG_SYS_HUSH_PARSER 330 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 331 332 /* I2C */ 333 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 334 #define CONFIG_FSL_I2C 335 #define CONFIG_I2C_MULTI_BUS 336 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 337 #define CONFIG_SYS_I2C_SLAVE 0x7F 338 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 339 #define CONFIG_SYS_I2C_OFFSET 0x3000 340 #define CONFIG_SYS_I2C2_OFFSET 0x3100 341 342 /* 343 * General PCI 344 * Addresses are mapped 1-1. 345 */ 346 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 347 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 348 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 349 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 350 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 351 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 352 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 353 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 354 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 355 356 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 357 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 358 359 /* 360 * TSEC 361 */ 362 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 363 364 #define CONFIG_NET_MULTI 365 #define CONFIG_GMII /* MII PHY management */ 366 367 #ifdef CONFIG_TSEC1 368 #define CONFIG_HAS_ETH0 369 #define CONFIG_TSEC1_NAME "TSEC0" 370 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 371 #define TSEC1_PHY_ADDR 0x1c 372 #define TSEC1_FLAGS TSEC_GIGABIT 373 #define TSEC1_PHYIDX 0 374 #endif 375 376 #ifdef CONFIG_TSEC2 377 #define CONFIG_HAS_ETH1 378 #define CONFIG_TSEC2_NAME "TSEC1" 379 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 380 #define TSEC2_PHY_ADDR 4 381 #define TSEC2_FLAGS TSEC_GIGABIT 382 #define TSEC2_PHYIDX 0 383 #endif 384 385 386 /* Options are: TSEC[0-1] */ 387 #define CONFIG_ETHPRIME "TSEC1" 388 389 /* 390 * Configure on-board RTC 391 */ 392 #define CONFIG_RTC_DS1337 393 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 394 395 /* 396 * Environment 397 */ 398 #if defined(CONFIG_NAND_U_BOOT) 399 #define CONFIG_ENV_IS_IN_NAND 1 400 #define CONFIG_ENV_OFFSET (512 * 1024) 401 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 402 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 403 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 404 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 405 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 406 #elif !defined(CONFIG_SYS_RAMBOOT) 407 #define CONFIG_ENV_IS_IN_FLASH 1 408 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 409 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 410 #define CONFIG_ENV_SIZE 0x2000 411 412 /* Address and size of Redundant Environment Sector */ 413 #else 414 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 415 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 416 #define CONFIG_ENV_SIZE 0x2000 417 #endif 418 419 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 420 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 421 422 /* 423 * BOOTP options 424 */ 425 #define CONFIG_BOOTP_BOOTFILESIZE 426 #define CONFIG_BOOTP_BOOTPATH 427 #define CONFIG_BOOTP_GATEWAY 428 #define CONFIG_BOOTP_HOSTNAME 429 430 431 /* 432 * Command line configuration. 433 */ 434 #include <config_cmd_default.h> 435 436 #define CONFIG_CMD_PING 437 #define CONFIG_CMD_DHCP 438 #define CONFIG_CMD_I2C 439 #define CONFIG_CMD_MII 440 #define CONFIG_CMD_DATE 441 #define CONFIG_CMD_PCI 442 443 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) 444 #undef CONFIG_CMD_SAVEENV 445 #undef CONFIG_CMD_LOADS 446 #endif 447 448 #define CONFIG_CMDLINE_EDITING 1 449 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 450 451 /* 452 * Miscellaneous configurable options 453 */ 454 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 455 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 456 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 457 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 458 459 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 460 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 461 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 462 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 463 464 /* 465 * For booting Linux, the board info and command line data 466 * have to be in the first 256 MB of memory, since this is 467 * the maximum mapped by the Linux kernel during initialization. 468 */ 469 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 470 471 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 472 473 #ifdef CONFIG_SYS_66MHZ 474 475 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 476 /* 0x62040000 */ 477 #define CONFIG_SYS_HRCW_LOW (\ 478 0x20000000 /* reserved, must be set */ |\ 479 HRCWL_DDRCM |\ 480 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 481 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 482 HRCWL_CSB_TO_CLKIN_2X1 |\ 483 HRCWL_CORE_TO_CSB_2X1) 484 485 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 486 487 #elif defined(CONFIG_SYS_33MHZ) 488 489 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 490 /* 0x65040000 */ 491 #define CONFIG_SYS_HRCW_LOW (\ 492 0x20000000 /* reserved, must be set */ |\ 493 HRCWL_DDRCM |\ 494 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 495 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 496 HRCWL_CSB_TO_CLKIN_5X1 |\ 497 HRCWL_CORE_TO_CSB_2X1) 498 499 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 500 501 #endif 502 503 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 504 HRCWH_PCI_HOST |\ 505 HRCWH_PCI1_ARBITER_ENABLE |\ 506 HRCWH_CORE_ENABLE |\ 507 HRCWH_BOOTSEQ_DISABLE |\ 508 HRCWH_SW_WATCHDOG_DISABLE |\ 509 HRCWH_TSEC1M_IN_RGMII |\ 510 HRCWH_TSEC2M_IN_RGMII |\ 511 HRCWH_BIG_ENDIAN) 512 513 #ifdef CONFIG_NAND_SPL 514 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 515 HRCWH_FROM_0XFFF00100 |\ 516 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 517 HRCWH_RL_EXT_NAND) 518 #else 519 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 520 HRCWH_FROM_0X00000100 |\ 521 HRCWH_ROM_LOC_LOCAL_16BIT |\ 522 HRCWH_RL_EXT_LEGACY) 523 #endif 524 525 /* System IO Config */ 526 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 527 #define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */ 528 529 #define CONFIG_SYS_HID0_INIT 0x000000000 530 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 531 HID0_ENABLE_INSTRUCTION_CACHE | \ 532 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 533 534 #define CONFIG_SYS_HID2 HID2_HBE 535 536 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 537 538 /* DDR @ 0x00000000 */ 539 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) 540 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 541 542 /* PCI @ 0x80000000 */ 543 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) 544 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 545 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 546 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 547 548 /* PCI2 not supported on 8313 */ 549 #define CONFIG_SYS_IBAT3L (0) 550 #define CONFIG_SYS_IBAT3U (0) 551 #define CONFIG_SYS_IBAT4L (0) 552 #define CONFIG_SYS_IBAT4U (0) 553 554 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 555 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 556 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 557 558 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 559 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) 560 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 561 562 #define CONFIG_SYS_IBAT7L (0) 563 #define CONFIG_SYS_IBAT7U (0) 564 565 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 566 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 567 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 568 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 569 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 570 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 571 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 572 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 573 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 574 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 575 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 576 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 577 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 578 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 579 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 580 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 581 582 /* 583 * Environment Configuration 584 */ 585 #define CONFIG_ENV_OVERWRITE 586 587 #define CONFIG_NETDEV eth1 588 589 #define CONFIG_HOSTNAME mpc8313erdb 590 #define CONFIG_ROOTPATH /nfs/root/path 591 #define CONFIG_BOOTFILE uImage 592 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 593 #define CONFIG_FDTFILE mpc8313erdb.dtb 594 595 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 596 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 597 #define CONFIG_BAUDRATE 115200 598 599 #define XMK_STR(x) #x 600 #define MK_STR(x) XMK_STR(x) 601 602 #define CONFIG_EXTRA_ENV_SETTINGS \ 603 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 604 "ethprime=TSEC1\0" \ 605 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 606 "tftpflash=tftpboot $loadaddr $uboot; " \ 607 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 608 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 609 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 610 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 611 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 612 "fdtaddr=780000\0" \ 613 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 614 "console=ttyS0\0" \ 615 "setbootargs=setenv bootargs " \ 616 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 617 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 618 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 619 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 620 621 #define CONFIG_NFSBOOTCOMMAND \ 622 "setenv rootdev /dev/nfs;" \ 623 "run setbootargs;" \ 624 "run setipargs;" \ 625 "tftp $loadaddr $bootfile;" \ 626 "tftp $fdtaddr $fdtfile;" \ 627 "bootm $loadaddr - $fdtaddr" 628 629 #define CONFIG_RAMBOOTCOMMAND \ 630 "setenv rootdev /dev/ram;" \ 631 "run setbootargs;" \ 632 "tftp $ramdiskaddr $ramdiskfile;" \ 633 "tftp $loadaddr $bootfile;" \ 634 "tftp $fdtaddr $fdtfile;" \ 635 "bootm $loadaddr $ramdiskaddr $fdtaddr" 636 637 #undef MK_STR 638 #undef XMK_STR 639 640 #endif /* __CONFIG_H */ 641