1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 4 */ 5 /* 6 * mpc8313epb board configuration file 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 16 #define CONFIG_MPC831x 1 17 #define CONFIG_MPC8313 1 18 #define CONFIG_MPC8313ERDB 1 19 20 #ifdef CONFIG_NAND 21 #define CONFIG_SPL_INIT_MINIMAL 22 #define CONFIG_SPL_FLUSH_IMAGE 23 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 24 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 25 26 #ifdef CONFIG_SPL_BUILD 27 #define CONFIG_NS16550_MIN_FUNCTIONS 28 #endif 29 30 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 31 #define CONFIG_SPL_MAX_SIZE (4 * 1024) 32 #define CONFIG_SPL_PAD_TO 0x4000 33 34 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 35 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 36 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 37 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 38 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 39 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 40 41 #ifdef CONFIG_SPL_BUILD 42 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 43 #endif 44 45 #endif /* CONFIG_NAND */ 46 47 #ifndef CONFIG_SYS_MONITOR_BASE 48 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 49 #endif 50 51 #define CONFIG_PCI_INDIRECT_BRIDGE 52 #define CONFIG_FSL_ELBC 1 53 54 /* 55 * On-board devices 56 * 57 * TSEC1 is VSC switch 58 * TSEC2 is SoC TSEC 59 */ 60 #define CONFIG_VSC7385_ENET 61 #define CONFIG_TSEC2 62 63 #ifdef CONFIG_SYS_66MHZ 64 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 65 #elif defined(CONFIG_SYS_33MHZ) 66 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 67 #else 68 #error Unknown oscillator frequency. 69 #endif 70 71 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 72 73 #define CONFIG_SYS_IMMR 0xE0000000 74 75 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) 76 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 77 #endif 78 79 #define CONFIG_SYS_MEMTEST_START 0x00001000 80 #define CONFIG_SYS_MEMTEST_END 0x07f00000 81 82 /* Early revs of this board will lock up hard when attempting 83 * to access the PMC registers, unless a JTAG debugger is 84 * connected, or some resistor modifications are made. 85 */ 86 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 87 88 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 89 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 90 91 /* 92 * Device configurations 93 */ 94 95 /* Vitesse 7385 */ 96 97 #ifdef CONFIG_VSC7385_ENET 98 99 #define CONFIG_TSEC1 100 101 /* The flash address and size of the VSC7385 firmware image */ 102 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 103 #define CONFIG_VSC7385_IMAGE_SIZE 8192 104 105 #endif 106 107 /* 108 * DDR Setup 109 */ 110 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 111 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 112 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 113 114 /* 115 * Manually set up DDR parameters, as this board does not 116 * seem to have the SPD connected to I2C. 117 */ 118 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 119 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 120 | CSCONFIG_ODT_RD_NEVER \ 121 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 122 | CSCONFIG_ROW_BIT_13 \ 123 | CSCONFIG_COL_BIT_10) 124 /* 0x80010102 */ 125 126 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 127 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 128 | (0 << TIMING_CFG0_WRT_SHIFT) \ 129 | (0 << TIMING_CFG0_RRT_SHIFT) \ 130 | (0 << TIMING_CFG0_WWT_SHIFT) \ 131 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 132 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 133 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 134 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 135 /* 0x00220802 */ 136 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 137 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 138 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 139 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 140 | (10 << TIMING_CFG1_REFREC_SHIFT) \ 141 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 142 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 143 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 144 /* 0x3835a322 */ 145 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 146 | (5 << TIMING_CFG2_CPO_SHIFT) \ 147 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 148 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 149 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 150 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 151 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 152 /* 0x129048c6 */ /* P9-45,may need tuning */ 153 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 154 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 155 /* 0x05100500 */ 156 #if defined(CONFIG_DDR_2T_TIMING) 157 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 158 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 159 | SDRAM_CFG_DBW_32 \ 160 | SDRAM_CFG_2T_EN) 161 /* 0x43088000 */ 162 #else 163 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 164 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 165 | SDRAM_CFG_DBW_32) 166 /* 0x43080000 */ 167 #endif 168 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 169 /* set burst length to 8 for 32-bit data path */ 170 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 171 | (0x0632 << SDRAM_MODE_SD_SHIFT)) 172 /* 0x44480632 */ 173 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 174 175 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 176 /*0x02000000*/ 177 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 178 | DDRCDR_PZ_NOMZ \ 179 | DDRCDR_NZ_NOMZ \ 180 | DDRCDR_M_ODR) 181 182 /* 183 * FLASH on the Local Bus 184 */ 185 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 186 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 187 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 188 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 189 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 190 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 191 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 192 193 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 194 | BR_PS_16 /* 16 bit port */ \ 195 | BR_MS_GPCM /* MSEL = GPCM */ \ 196 | BR_V) /* valid */ 197 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 198 | OR_GPCM_XACS \ 199 | OR_GPCM_SCY_9 \ 200 | OR_GPCM_EHTR \ 201 | OR_GPCM_EAD) 202 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 203 /* window base at flash base */ 204 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 205 /* 16 MB window size */ 206 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 207 208 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 209 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 210 211 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 212 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 213 214 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 215 !defined(CONFIG_SPL_BUILD) 216 #define CONFIG_SYS_RAMBOOT 217 #endif 218 219 #define CONFIG_SYS_INIT_RAM_LOCK 1 220 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 221 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 222 223 #define CONFIG_SYS_GBL_DATA_OFFSET \ 224 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 225 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 226 227 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 228 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 229 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 230 231 /* 232 * Local Bus LCRR and LBCR regs 233 */ 234 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 235 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 236 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 237 | (0xFF << LBCR_BMT_SHIFT) \ 238 | 0xF) /* 0x0004ff0f */ 239 240 /* LB refresh timer prescal, 266MHz/32 */ 241 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 242 243 /* drivers/mtd/nand/raw/nand.c */ 244 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) 245 #define CONFIG_SYS_NAND_BASE 0xFFF00000 246 #else 247 #define CONFIG_SYS_NAND_BASE 0xE2800000 248 #endif 249 250 #define CONFIG_MTD_PARTITION 251 252 #define CONFIG_SYS_MAX_NAND_DEVICE 1 253 #define CONFIG_NAND_FSL_ELBC 1 254 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 255 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 256 257 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 258 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 259 | BR_PS_8 /* 8 bit port */ \ 260 | BR_MS_FCM /* MSEL = FCM */ \ 261 | BR_V) /* valid */ 262 #define CONFIG_SYS_NAND_OR_PRELIM \ 263 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 264 | OR_FCM_CSCT \ 265 | OR_FCM_CST \ 266 | OR_FCM_CHT \ 267 | OR_FCM_SCY_1 \ 268 | OR_FCM_TRLX \ 269 | OR_FCM_EHTR) 270 /* 0xFFFF8396 */ 271 272 #ifdef CONFIG_NAND 273 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 274 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 275 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 276 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 277 #else 278 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 279 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 280 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 281 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 282 #endif 283 284 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 285 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 286 287 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 288 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 289 290 /* local bus write LED / read status buffer (BCSR) mapping */ 291 #define CONFIG_SYS_BCSR_ADDR 0xFA000000 292 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 293 /* map at 0xFA000000 on LCS3 */ 294 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 295 | BR_PS_8 /* 8 bit port */ \ 296 | BR_MS_GPCM /* MSEL = GPCM */ \ 297 | BR_V) /* valid */ 298 /* 0xFA000801 */ 299 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 300 | OR_GPCM_CSNT \ 301 | OR_GPCM_ACS_DIV2 \ 302 | OR_GPCM_XACS \ 303 | OR_GPCM_SCY_15 \ 304 | OR_GPCM_TRLX_SET \ 305 | OR_GPCM_EHTR_SET \ 306 | OR_GPCM_EAD) 307 /* 0xFFFF8FF7 */ 308 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 309 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 310 311 /* Vitesse 7385 */ 312 313 #ifdef CONFIG_VSC7385_ENET 314 315 /* VSC7385 Base address on LCS2 */ 316 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 317 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 318 319 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 320 | BR_PS_8 /* 8 bit port */ \ 321 | BR_MS_GPCM /* MSEL = GPCM */ \ 322 | BR_V) /* valid */ 323 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 324 | OR_GPCM_CSNT \ 325 | OR_GPCM_XACS \ 326 | OR_GPCM_SCY_15 \ 327 | OR_GPCM_SETA \ 328 | OR_GPCM_TRLX_SET \ 329 | OR_GPCM_EHTR_SET \ 330 | OR_GPCM_EAD) 331 /* 0xFFFE09FF */ 332 333 /* Access window base at VSC7385 base */ 334 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 335 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 336 337 #endif 338 339 #define CONFIG_MPC83XX_GPIO 1 340 341 /* 342 * Serial Port 343 */ 344 #define CONFIG_SYS_NS16550_SERIAL 345 #define CONFIG_SYS_NS16550_REG_SIZE 1 346 347 #define CONFIG_SYS_BAUDRATE_TABLE \ 348 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 349 350 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 351 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 352 353 /* I2C */ 354 #define CONFIG_SYS_I2C 355 #define CONFIG_SYS_I2C_FSL 356 #define CONFIG_SYS_FSL_I2C_SPEED 400000 357 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 358 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 359 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 360 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 361 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 362 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 363 364 /* 365 * General PCI 366 * Addresses are mapped 1-1. 367 */ 368 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 369 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 370 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 371 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 372 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 373 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 374 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 375 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 376 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 377 378 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 379 380 /* 381 * TSEC 382 */ 383 384 #define CONFIG_GMII /* MII PHY management */ 385 386 #ifdef CONFIG_TSEC1 387 #define CONFIG_HAS_ETH0 388 #define CONFIG_TSEC1_NAME "TSEC0" 389 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 390 #define TSEC1_PHY_ADDR 0x1c 391 #define TSEC1_FLAGS TSEC_GIGABIT 392 #define TSEC1_PHYIDX 0 393 #endif 394 395 #ifdef CONFIG_TSEC2 396 #define CONFIG_HAS_ETH1 397 #define CONFIG_TSEC2_NAME "TSEC1" 398 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 399 #define TSEC2_PHY_ADDR 4 400 #define TSEC2_FLAGS TSEC_GIGABIT 401 #define TSEC2_PHYIDX 0 402 #endif 403 404 /* Options are: TSEC[0-1] */ 405 #define CONFIG_ETHPRIME "TSEC1" 406 407 /* 408 * Configure on-board RTC 409 */ 410 #define CONFIG_RTC_DS1337 411 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 412 413 /* 414 * Environment 415 */ 416 #if defined(CONFIG_NAND) 417 #define CONFIG_ENV_OFFSET (512 * 1024) 418 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 419 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 420 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 421 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 422 #define CONFIG_ENV_OFFSET_REDUND \ 423 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 424 #elif !defined(CONFIG_SYS_RAMBOOT) 425 #define CONFIG_ENV_ADDR \ 426 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 427 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 428 #define CONFIG_ENV_SIZE 0x2000 429 430 /* Address and size of Redundant Environment Sector */ 431 #else 432 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 433 #define CONFIG_ENV_SIZE 0x2000 434 #endif 435 436 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 437 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 438 439 /* 440 * BOOTP options 441 */ 442 #define CONFIG_BOOTP_BOOTFILESIZE 443 444 /* 445 * Command line configuration. 446 */ 447 448 /* 449 * Miscellaneous configurable options 450 */ 451 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 452 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 453 454 /* Boot Argument Buffer Size */ 455 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 456 457 /* 458 * For booting Linux, the board info and command line data 459 * have to be in the first 256 MB of memory, since this is 460 * the maximum mapped by the Linux kernel during initialization. 461 */ 462 /* Initial Memory map for Linux*/ 463 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 464 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 465 466 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 467 468 #ifdef CONFIG_SYS_66MHZ 469 470 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 471 /* 0x62040000 */ 472 #define CONFIG_SYS_HRCW_LOW (\ 473 0x20000000 /* reserved, must be set */ |\ 474 HRCWL_DDRCM |\ 475 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 476 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 477 HRCWL_CSB_TO_CLKIN_2X1 |\ 478 HRCWL_CORE_TO_CSB_2X1) 479 480 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 481 482 #elif defined(CONFIG_SYS_33MHZ) 483 484 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 485 /* 0x65040000 */ 486 #define CONFIG_SYS_HRCW_LOW (\ 487 0x20000000 /* reserved, must be set */ |\ 488 HRCWL_DDRCM |\ 489 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 490 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 491 HRCWL_CSB_TO_CLKIN_5X1 |\ 492 HRCWL_CORE_TO_CSB_2X1) 493 494 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 495 496 #endif 497 498 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 499 HRCWH_PCI_HOST |\ 500 HRCWH_PCI1_ARBITER_ENABLE |\ 501 HRCWH_CORE_ENABLE |\ 502 HRCWH_BOOTSEQ_DISABLE |\ 503 HRCWH_SW_WATCHDOG_DISABLE |\ 504 HRCWH_TSEC1M_IN_RGMII |\ 505 HRCWH_TSEC2M_IN_RGMII |\ 506 HRCWH_BIG_ENDIAN) 507 508 #ifdef CONFIG_NAND 509 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 510 HRCWH_FROM_0XFFF00100 |\ 511 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 512 HRCWH_RL_EXT_NAND) 513 #else 514 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 515 HRCWH_FROM_0X00000100 |\ 516 HRCWH_ROM_LOC_LOCAL_16BIT |\ 517 HRCWH_RL_EXT_LEGACY) 518 #endif 519 520 /* System IO Config */ 521 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 522 /* Enable Internal USB Phy and GPIO on LCD Connector */ 523 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 524 525 #define CONFIG_SYS_HID0_INIT 0x000000000 526 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 527 HID0_ENABLE_INSTRUCTION_CACHE | \ 528 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 529 530 #define CONFIG_SYS_HID2 HID2_HBE 531 532 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 533 534 /* DDR @ 0x00000000 */ 535 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 536 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 537 | BATU_BL_256M \ 538 | BATU_VS \ 539 | BATU_VP) 540 541 /* PCI @ 0x80000000 */ 542 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 543 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 544 | BATU_BL_256M \ 545 | BATU_VS \ 546 | BATU_VP) 547 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 548 | BATL_PP_RW \ 549 | BATL_CACHEINHIBIT \ 550 | BATL_GUARDEDSTORAGE) 551 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 552 | BATU_BL_256M \ 553 | BATU_VS \ 554 | BATU_VP) 555 556 /* PCI2 not supported on 8313 */ 557 #define CONFIG_SYS_IBAT3L (0) 558 #define CONFIG_SYS_IBAT3U (0) 559 #define CONFIG_SYS_IBAT4L (0) 560 #define CONFIG_SYS_IBAT4U (0) 561 562 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 563 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 564 | BATL_PP_RW \ 565 | BATL_CACHEINHIBIT \ 566 | BATL_GUARDEDSTORAGE) 567 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 568 | BATU_BL_256M \ 569 | BATU_VS \ 570 | BATU_VP) 571 572 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 573 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 574 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 575 576 #define CONFIG_SYS_IBAT7L (0) 577 #define CONFIG_SYS_IBAT7U (0) 578 579 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 580 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 581 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 582 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 583 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 584 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 585 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 586 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 587 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 588 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 589 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 590 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 591 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 592 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 593 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 594 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 595 596 /* 597 * Environment Configuration 598 */ 599 #define CONFIG_ENV_OVERWRITE 600 601 #define CONFIG_NETDEV "eth1" 602 603 #define CONFIG_HOSTNAME "mpc8313erdb" 604 #define CONFIG_ROOTPATH "/nfs/root/path" 605 #define CONFIG_BOOTFILE "uImage" 606 /* U-Boot image on TFTP server */ 607 #define CONFIG_UBOOTPATH "u-boot.bin" 608 #define CONFIG_FDTFILE "mpc8313erdb.dtb" 609 610 /* default location for tftp and bootm */ 611 #define CONFIG_LOADADDR 800000 612 613 #define CONFIG_EXTRA_ENV_SETTINGS \ 614 "netdev=" CONFIG_NETDEV "\0" \ 615 "ethprime=TSEC1\0" \ 616 "uboot=" CONFIG_UBOOTPATH "\0" \ 617 "tftpflash=tftpboot $loadaddr $uboot; " \ 618 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 619 " +$filesize; " \ 620 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 621 " +$filesize; " \ 622 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 623 " $filesize; " \ 624 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 625 " +$filesize; " \ 626 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 627 " $filesize\0" \ 628 "fdtaddr=780000\0" \ 629 "fdtfile=" CONFIG_FDTFILE "\0" \ 630 "console=ttyS0\0" \ 631 "setbootargs=setenv bootargs " \ 632 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 633 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 634 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 635 "$netdev:off " \ 636 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 637 638 #define CONFIG_NFSBOOTCOMMAND \ 639 "setenv rootdev /dev/nfs;" \ 640 "run setbootargs;" \ 641 "run setipargs;" \ 642 "tftp $loadaddr $bootfile;" \ 643 "tftp $fdtaddr $fdtfile;" \ 644 "bootm $loadaddr - $fdtaddr" 645 646 #define CONFIG_RAMBOOTCOMMAND \ 647 "setenv rootdev /dev/ram;" \ 648 "run setbootargs;" \ 649 "tftp $ramdiskaddr $ramdiskfile;" \ 650 "tftp $loadaddr $bootfile;" \ 651 "tftp $fdtaddr $fdtfile;" \ 652 "bootm $loadaddr $ramdiskaddr $fdtaddr" 653 654 #endif /* __CONFIG_H */ 655