1 /*
2  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 /*
7  * mpc8313epb board configuration file
8  */
9 
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 /*
14  * High Level Configuration Options
15  */
16 #define CONFIG_E300		1
17 #define CONFIG_MPC83xx		1
18 #define CONFIG_MPC831x		1
19 #define CONFIG_MPC8313		1
20 #define CONFIG_MPC8313ERDB	1
21 
22 #ifdef CONFIG_NAND
23 #define CONFIG_SPL
24 #define CONFIG_SPL_INIT_MINIMAL
25 #define CONFIG_SPL_SERIAL_SUPPORT
26 #define CONFIG_SPL_NAND_SUPPORT
27 #define CONFIG_SPL_NAND_MINIMAL
28 #define CONFIG_SPL_FLUSH_IMAGE
29 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
30 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
31 
32 #ifdef CONFIG_SPL_BUILD
33 #define CONFIG_NS16550_MIN_FUNCTIONS
34 #endif
35 
36 #define CONFIG_SYS_TEXT_BASE	0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
37 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
38 #define CONFIG_SPL_MAX_SIZE	(4 * 1024)
39 #define CONFIG_SPL_PAD_TO	0x4000
40 
41 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
42 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
43 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
44 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
45 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
46 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
47 
48 #ifdef CONFIG_SPL_BUILD
49 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
50 #endif
51 
52 #endif /* CONFIG_NAND */
53 
54 #ifndef CONFIG_SYS_TEXT_BASE
55 #define CONFIG_SYS_TEXT_BASE	0xFE000000
56 #endif
57 
58 #ifndef CONFIG_SYS_MONITOR_BASE
59 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
60 #endif
61 
62 #define CONFIG_PCI
63 #define CONFIG_PCI_INDIRECT_BRIDGE
64 #define CONFIG_FSL_ELBC 1
65 
66 #define CONFIG_MISC_INIT_R
67 
68 /*
69  * On-board devices
70  *
71  * TSEC1 is VSC switch
72  * TSEC2 is SoC TSEC
73  */
74 #define CONFIG_VSC7385_ENET
75 #define CONFIG_TSEC2
76 
77 #ifdef CONFIG_SYS_66MHZ
78 #define CONFIG_83XX_CLKIN	66666667	/* in Hz */
79 #elif defined(CONFIG_SYS_33MHZ)
80 #define CONFIG_83XX_CLKIN	33333333	/* in Hz */
81 #else
82 #error Unknown oscillator frequency.
83 #endif
84 
85 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
86 
87 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f */
88 #define CONFIG_BOARD_EARLY_INIT_R		/* call board_early_init_r */
89 
90 #define CONFIG_SYS_IMMR		0xE0000000
91 
92 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
93 #define CONFIG_DEFAULT_IMMR	CONFIG_SYS_IMMR
94 #endif
95 
96 #define CONFIG_SYS_MEMTEST_START	0x00001000
97 #define CONFIG_SYS_MEMTEST_END		0x07f00000
98 
99 /* Early revs of this board will lock up hard when attempting
100  * to access the PMC registers, unless a JTAG debugger is
101  * connected, or some resistor modifications are made.
102  */
103 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
104 
105 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
106 #define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
107 
108 /*
109  * Device configurations
110  */
111 
112 /* Vitesse 7385 */
113 
114 #ifdef CONFIG_VSC7385_ENET
115 
116 #define CONFIG_TSEC1
117 
118 /* The flash address and size of the VSC7385 firmware image */
119 #define CONFIG_VSC7385_IMAGE		0xFE7FE000
120 #define CONFIG_VSC7385_IMAGE_SIZE	8192
121 
122 #endif
123 
124 /*
125  * DDR Setup
126  */
127 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory*/
128 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
129 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
130 
131 /*
132  * Manually set up DDR parameters, as this board does not
133  * seem to have the SPD connected to I2C.
134  */
135 #define CONFIG_SYS_DDR_SIZE	128		/* MB */
136 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
137 				| CSCONFIG_ODT_RD_NEVER \
138 				| CSCONFIG_ODT_WR_ONLY_CURRENT \
139 				| CSCONFIG_ROW_BIT_13 \
140 				| CSCONFIG_COL_BIT_10)
141 				/* 0x80010102 */
142 
143 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
144 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
145 				| (0 << TIMING_CFG0_WRT_SHIFT) \
146 				| (0 << TIMING_CFG0_RRT_SHIFT) \
147 				| (0 << TIMING_CFG0_WWT_SHIFT) \
148 				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
149 				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
150 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
151 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
152 				/* 0x00220802 */
153 #define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
154 				| (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
155 				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
156 				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
157 				| (10 << TIMING_CFG1_REFREC_SHIFT) \
158 				| (3 << TIMING_CFG1_WRREC_SHIFT) \
159 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
160 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
161 				/* 0x3835a322 */
162 #define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
163 				| (5 << TIMING_CFG2_CPO_SHIFT) \
164 				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
165 				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
166 				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
167 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
168 				| (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
169 				/* 0x129048c6 */ /* P9-45,may need tuning */
170 #define CONFIG_SYS_DDR_INTERVAL	((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
171 				| (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
172 				/* 0x05100500 */
173 #if defined(CONFIG_DDR_2T_TIMING)
174 #define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
175 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
176 				| SDRAM_CFG_DBW_32 \
177 				| SDRAM_CFG_2T_EN)
178 				/* 0x43088000 */
179 #else
180 #define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
181 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
182 				| SDRAM_CFG_DBW_32)
183 				/* 0x43080000 */
184 #endif
185 #define CONFIG_SYS_SDRAM_CFG2		0x00401000
186 /* set burst length to 8 for 32-bit data path */
187 #define CONFIG_SYS_DDR_MODE	((0x4448 << SDRAM_MODE_ESD_SHIFT) \
188 				| (0x0632 << SDRAM_MODE_SD_SHIFT))
189 				/* 0x44480632 */
190 #define CONFIG_SYS_DDR_MODE_2	0x8000C000
191 
192 #define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
193 				/*0x02000000*/
194 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
195 				| DDRCDR_PZ_NOMZ \
196 				| DDRCDR_NZ_NOMZ \
197 				| DDRCDR_M_ODR)
198 
199 /*
200  * FLASH on the Local Bus
201  */
202 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
203 #define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
204 #define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
205 #define CONFIG_SYS_FLASH_SIZE		8	/* flash size in MB */
206 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
207 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
208 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* buffer up multiple bytes */
209 
210 #define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
211 					| BR_PS_16	/* 16 bit port */ \
212 					| BR_MS_GPCM	/* MSEL = GPCM */ \
213 					| BR_V)		/* valid */
214 #define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
215 				| OR_GPCM_XACS \
216 				| OR_GPCM_SCY_9 \
217 				| OR_GPCM_EHTR \
218 				| OR_GPCM_EAD)
219 				/* 0xFF006FF7	TODO SLOW 16 MB flash size */
220 					/* window base at flash base */
221 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
222 					/* 16 MB window size */
223 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_16MB)
224 
225 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
226 #define CONFIG_SYS_MAX_FLASH_SECT	135	/* sectors per device */
227 
228 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
229 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
230 
231 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
232 	!defined(CONFIG_SPL_BUILD)
233 #define CONFIG_SYS_RAMBOOT
234 #endif
235 
236 #define CONFIG_SYS_INIT_RAM_LOCK	1
237 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
238 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
239 
240 #define CONFIG_SYS_GBL_DATA_OFFSET	\
241 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
242 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
243 
244 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
245 #define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
246 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
247 
248 /*
249  * Local Bus LCRR and LBCR regs
250  */
251 #define CONFIG_SYS_LCRR_EADC	LCRR_EADC_1
252 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
253 #define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
254 				| (0xFF << LBCR_BMT_SHIFT) \
255 				| 0xF)	/* 0x0004ff0f */
256 
257 				/* LB refresh timer prescal, 266MHz/32 */
258 #define CONFIG_SYS_LBC_MRTPR	0x20000000  /*TODO */
259 
260 /* drivers/mtd/nand/nand.c */
261 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
262 #define CONFIG_SYS_NAND_BASE		0xFFF00000
263 #else
264 #define CONFIG_SYS_NAND_BASE		0xE2800000
265 #endif
266 
267 #define CONFIG_MTD_DEVICE
268 #define CONFIG_MTD_PARTITION
269 #define CONFIG_CMD_MTDPARTS
270 #define MTDIDS_DEFAULT			"nand0=e2800000.flash"
271 #define MTDPARTS_DEFAULT		\
272 	"mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
273 
274 #define CONFIG_SYS_MAX_NAND_DEVICE	1
275 #define CONFIG_MTD_NAND_VERIFY_WRITE
276 #define CONFIG_CMD_NAND 1
277 #define CONFIG_NAND_FSL_ELBC 1
278 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
279 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
280 
281 
282 #define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
283 				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
284 				| BR_PS_8		/* 8 bit port */ \
285 				| BR_MS_FCM		/* MSEL = FCM */ \
286 				| BR_V)			/* valid */
287 #define CONFIG_SYS_NAND_OR_PRELIM	\
288 				(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
289 				| OR_FCM_CSCT \
290 				| OR_FCM_CST \
291 				| OR_FCM_CHT \
292 				| OR_FCM_SCY_1 \
293 				| OR_FCM_TRLX \
294 				| OR_FCM_EHTR)
295 				/* 0xFFFF8396 */
296 
297 #ifdef CONFIG_NAND
298 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
299 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
300 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
301 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
302 #else
303 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
304 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
305 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
306 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
307 #endif
308 
309 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
310 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
311 
312 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
313 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
314 
315 /* local bus write LED / read status buffer (BCSR) mapping */
316 #define CONFIG_SYS_BCSR_ADDR		0xFA000000
317 #define CONFIG_SYS_BCSR_SIZE		(32 * 1024)	/* 0x00008000 */
318 					/* map at 0xFA000000 on LCS3 */
319 #define CONFIG_SYS_BR3_PRELIM		(CONFIG_SYS_BCSR_ADDR \
320 					| BR_PS_8	/* 8 bit port */ \
321 					| BR_MS_GPCM	/* MSEL = GPCM */ \
322 					| BR_V)		/* valid */
323 					/* 0xFA000801 */
324 #define CONFIG_SYS_OR3_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
325 					| OR_GPCM_CSNT \
326 					| OR_GPCM_ACS_DIV2 \
327 					| OR_GPCM_XACS \
328 					| OR_GPCM_SCY_15 \
329 					| OR_GPCM_TRLX_SET \
330 					| OR_GPCM_EHTR_SET \
331 					| OR_GPCM_EAD)
332 					/* 0xFFFF8FF7 */
333 #define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_BCSR_ADDR
334 #define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
335 
336 /* Vitesse 7385 */
337 
338 #ifdef CONFIG_VSC7385_ENET
339 
340 					/* VSC7385 Base address on LCS2 */
341 #define CONFIG_SYS_VSC7385_BASE		0xF0000000
342 #define CONFIG_SYS_VSC7385_SIZE		(128 * 1024)	/* 0x00020000 */
343 
344 #define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VSC7385_BASE \
345 					| BR_PS_8	/* 8 bit port */ \
346 					| BR_MS_GPCM	/* MSEL = GPCM */ \
347 					| BR_V)		/* valid */
348 #define CONFIG_SYS_OR2_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
349 					| OR_GPCM_CSNT \
350 					| OR_GPCM_XACS \
351 					| OR_GPCM_SCY_15 \
352 					| OR_GPCM_SETA \
353 					| OR_GPCM_TRLX_SET \
354 					| OR_GPCM_EHTR_SET \
355 					| OR_GPCM_EAD)
356 					/* 0xFFFE09FF */
357 
358 					/* Access window base at VSC7385 base */
359 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
360 #define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
361 
362 #endif
363 
364 /* pass open firmware flat tree */
365 #define CONFIG_OF_LIBFDT	1
366 #define CONFIG_OF_BOARD_SETUP	1
367 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
368 
369 #define CONFIG_MPC83XX_GPIO 1
370 #define CONFIG_CMD_GPIO 1
371 
372 /*
373  * Serial Port
374  */
375 #define CONFIG_CONS_INDEX	1
376 #define CONFIG_SYS_NS16550
377 #define CONFIG_SYS_NS16550_SERIAL
378 #define CONFIG_SYS_NS16550_REG_SIZE	1
379 
380 #define CONFIG_SYS_BAUDRATE_TABLE	\
381 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
382 
383 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
384 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
385 
386 /* Use the HUSH parser */
387 #define CONFIG_SYS_HUSH_PARSER
388 
389 /* I2C */
390 #define CONFIG_SYS_I2C
391 #define CONFIG_SYS_I2C_FSL
392 #define CONFIG_SYS_FSL_I2C_SPEED	400000
393 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
394 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
395 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
396 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
397 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
398 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
399 
400 /*
401  * General PCI
402  * Addresses are mapped 1-1.
403  */
404 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
405 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
406 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
407 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
408 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
409 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
410 #define CONFIG_SYS_PCI1_IO_BASE	0x00000000
411 #define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
412 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
413 
414 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
415 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
416 
417 /*
418  * TSEC
419  */
420 #define CONFIG_TSEC_ENET		/* TSEC ethernet support */
421 
422 #define CONFIG_GMII			/* MII PHY management */
423 
424 #ifdef CONFIG_TSEC1
425 #define CONFIG_HAS_ETH0
426 #define CONFIG_TSEC1_NAME	"TSEC0"
427 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
428 #define TSEC1_PHY_ADDR		0x1c
429 #define TSEC1_FLAGS		TSEC_GIGABIT
430 #define TSEC1_PHYIDX		0
431 #endif
432 
433 #ifdef CONFIG_TSEC2
434 #define CONFIG_HAS_ETH1
435 #define CONFIG_TSEC2_NAME	"TSEC1"
436 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
437 #define TSEC2_PHY_ADDR		4
438 #define TSEC2_FLAGS		TSEC_GIGABIT
439 #define TSEC2_PHYIDX		0
440 #endif
441 
442 
443 /* Options are: TSEC[0-1] */
444 #define CONFIG_ETHPRIME			"TSEC1"
445 
446 /*
447  * Configure on-board RTC
448  */
449 #define CONFIG_RTC_DS1337
450 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
451 
452 /*
453  * Environment
454  */
455 #if defined(CONFIG_NAND)
456 	#define CONFIG_ENV_IS_IN_NAND	1
457 	#define CONFIG_ENV_OFFSET		(512 * 1024)
458 	#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
459 	#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
460 	#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
461 	#define CONFIG_ENV_RANGE		(CONFIG_ENV_SECT_SIZE * 4)
462 	#define CONFIG_ENV_OFFSET_REDUND	\
463 					(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
464 #elif !defined(CONFIG_SYS_RAMBOOT)
465 	#define CONFIG_ENV_IS_IN_FLASH	1
466 	#define CONFIG_ENV_ADDR		\
467 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
468 	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
469 	#define CONFIG_ENV_SIZE		0x2000
470 
471 /* Address and size of Redundant Environment Sector */
472 #else
473 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
474 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
475 	#define CONFIG_ENV_SIZE		0x2000
476 #endif
477 
478 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
479 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
480 
481 /*
482  * BOOTP options
483  */
484 #define CONFIG_BOOTP_BOOTFILESIZE
485 #define CONFIG_BOOTP_BOOTPATH
486 #define CONFIG_BOOTP_GATEWAY
487 #define CONFIG_BOOTP_HOSTNAME
488 
489 
490 /*
491  * Command line configuration.
492  */
493 #include <config_cmd_default.h>
494 
495 #define CONFIG_CMD_PING
496 #define CONFIG_CMD_DHCP
497 #define CONFIG_CMD_I2C
498 #define CONFIG_CMD_MII
499 #define CONFIG_CMD_DATE
500 #define CONFIG_CMD_PCI
501 
502 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND)
503     #undef CONFIG_CMD_SAVEENV
504     #undef CONFIG_CMD_LOADS
505 #endif
506 
507 #define CONFIG_CMDLINE_EDITING 1
508 #define CONFIG_AUTO_COMPLETE	/* add autocompletion support   */
509 
510 /*
511  * Miscellaneous configurable options
512  */
513 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
514 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
515 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
516 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
517 
518 						/* Print Buffer Size */
519 #define CONFIG_SYS_PBSIZE	\
520 			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
521 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
522 				/* Boot Argument Buffer Size */
523 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
524 #define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
525 
526 /*
527  * For booting Linux, the board info and command line data
528  * have to be in the first 256 MB of memory, since this is
529  * the maximum mapped by the Linux kernel during initialization.
530  */
531 				/* Initial Memory map for Linux*/
532 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
533 
534 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000	/* PCIHOST  */
535 
536 #ifdef CONFIG_SYS_66MHZ
537 
538 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
539 /* 0x62040000 */
540 #define CONFIG_SYS_HRCW_LOW (\
541 	0x20000000 /* reserved, must be set */ |\
542 	HRCWL_DDRCM |\
543 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
544 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
545 	HRCWL_CSB_TO_CLKIN_2X1 |\
546 	HRCWL_CORE_TO_CSB_2X1)
547 
548 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
549 
550 #elif defined(CONFIG_SYS_33MHZ)
551 
552 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
553 /* 0x65040000 */
554 #define CONFIG_SYS_HRCW_LOW (\
555 	0x20000000 /* reserved, must be set */ |\
556 	HRCWL_DDRCM |\
557 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
558 	HRCWL_DDR_TO_SCB_CLK_2X1 |\
559 	HRCWL_CSB_TO_CLKIN_5X1 |\
560 	HRCWL_CORE_TO_CSB_2X1)
561 
562 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
563 
564 #endif
565 
566 #define CONFIG_SYS_HRCW_HIGH_BASE (\
567 	HRCWH_PCI_HOST |\
568 	HRCWH_PCI1_ARBITER_ENABLE |\
569 	HRCWH_CORE_ENABLE |\
570 	HRCWH_BOOTSEQ_DISABLE |\
571 	HRCWH_SW_WATCHDOG_DISABLE |\
572 	HRCWH_TSEC1M_IN_RGMII |\
573 	HRCWH_TSEC2M_IN_RGMII |\
574 	HRCWH_BIG_ENDIAN)
575 
576 #ifdef CONFIG_NAND
577 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
578 		       HRCWH_FROM_0XFFF00100 |\
579 		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
580 		       HRCWH_RL_EXT_NAND)
581 #else
582 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
583 		       HRCWH_FROM_0X00000100 |\
584 		       HRCWH_ROM_LOC_LOCAL_16BIT |\
585 		       HRCWH_RL_EXT_LEGACY)
586 #endif
587 
588 /* System IO Config */
589 #define CONFIG_SYS_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
590 			/* Enable Internal USB Phy and GPIO on LCD Connector */
591 #define CONFIG_SYS_SICRL	(SICRL_USBDR_10 | SICRL_LBC)
592 
593 #define CONFIG_SYS_HID0_INIT	0x000000000
594 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
595 				 HID0_ENABLE_INSTRUCTION_CACHE | \
596 				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
597 
598 #define CONFIG_SYS_HID2 HID2_HBE
599 
600 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
601 
602 /* DDR @ 0x00000000 */
603 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
604 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
605 				| BATU_BL_256M \
606 				| BATU_VS \
607 				| BATU_VP)
608 
609 /* PCI @ 0x80000000 */
610 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
611 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
612 				| BATU_BL_256M \
613 				| BATU_VS \
614 				| BATU_VP)
615 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
616 				| BATL_PP_RW \
617 				| BATL_CACHEINHIBIT \
618 				| BATL_GUARDEDSTORAGE)
619 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
620 				| BATU_BL_256M \
621 				| BATU_VS \
622 				| BATU_VP)
623 
624 /* PCI2 not supported on 8313 */
625 #define CONFIG_SYS_IBAT3L	(0)
626 #define CONFIG_SYS_IBAT3U	(0)
627 #define CONFIG_SYS_IBAT4L	(0)
628 #define CONFIG_SYS_IBAT4U	(0)
629 
630 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
631 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
632 				| BATL_PP_RW \
633 				| BATL_CACHEINHIBIT \
634 				| BATL_GUARDEDSTORAGE)
635 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
636 				| BATU_BL_256M \
637 				| BATU_VS \
638 				| BATU_VP)
639 
640 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
641 #define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
642 #define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
643 
644 #define CONFIG_SYS_IBAT7L	(0)
645 #define CONFIG_SYS_IBAT7U	(0)
646 
647 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
648 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
649 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
650 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
651 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
652 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
653 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
654 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
655 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
656 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
657 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
658 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
659 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
660 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
661 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
662 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
663 
664 /*
665  * Environment Configuration
666  */
667 #define CONFIG_ENV_OVERWRITE
668 
669 #define CONFIG_NETDEV		"eth1"
670 
671 #define CONFIG_HOSTNAME		mpc8313erdb
672 #define CONFIG_ROOTPATH		"/nfs/root/path"
673 #define CONFIG_BOOTFILE		"uImage"
674 				/* U-Boot image on TFTP server */
675 #define CONFIG_UBOOTPATH	"u-boot.bin"
676 #define CONFIG_FDTFILE		"mpc8313erdb.dtb"
677 
678 				/* default location for tftp and bootm */
679 #define CONFIG_LOADADDR		800000
680 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
681 #define CONFIG_BAUDRATE		115200
682 
683 #define CONFIG_EXTRA_ENV_SETTINGS \
684 	"netdev=" CONFIG_NETDEV "\0"					\
685 	"ethprime=TSEC1\0"						\
686 	"uboot=" CONFIG_UBOOTPATH "\0"					\
687 	"tftpflash=tftpboot $loadaddr $uboot; "				\
688 		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
689 			" +$filesize; "	\
690 		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
691 			" +$filesize; "	\
692 		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
693 			" $filesize; "	\
694 		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
695 			" +$filesize; "	\
696 		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
697 			" $filesize\0"	\
698 	"fdtaddr=780000\0"						\
699 	"fdtfile=" CONFIG_FDTFILE "\0"					\
700 	"console=ttyS0\0"						\
701 	"setbootargs=setenv bootargs "					\
702 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
703 	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	 \
704 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
705 							"$netdev:off " \
706 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
707 
708 #define CONFIG_NFSBOOTCOMMAND						\
709 	"setenv rootdev /dev/nfs;"					\
710 	"run setbootargs;"						\
711 	"run setipargs;"						\
712 	"tftp $loadaddr $bootfile;"					\
713 	"tftp $fdtaddr $fdtfile;"					\
714 	"bootm $loadaddr - $fdtaddr"
715 
716 #define CONFIG_RAMBOOTCOMMAND						\
717 	"setenv rootdev /dev/ram;"					\
718 	"run setbootargs;"						\
719 	"tftp $ramdiskaddr $ramdiskfile;"				\
720 	"tftp $loadaddr $bootfile;"					\
721 	"tftp $fdtaddr $fdtfile;"					\
722 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
723 
724 #endif	/* __CONFIG_H */
725