1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 /* 7 * mpc8313epb board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_E300 1 17 #define CONFIG_MPC831x 1 18 #define CONFIG_MPC8313 1 19 #define CONFIG_MPC8313ERDB 1 20 21 #ifdef CONFIG_NAND 22 #define CONFIG_SPL_INIT_MINIMAL 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 25 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 26 27 #ifdef CONFIG_SPL_BUILD 28 #define CONFIG_NS16550_MIN_FUNCTIONS 29 #endif 30 31 #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 32 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 33 #define CONFIG_SPL_MAX_SIZE (4 * 1024) 34 #define CONFIG_SPL_PAD_TO 0x4000 35 36 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 37 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 38 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 39 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 40 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 41 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 42 43 #ifdef CONFIG_SPL_BUILD 44 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 45 #endif 46 47 #endif /* CONFIG_NAND */ 48 49 #ifndef CONFIG_SYS_TEXT_BASE 50 #define CONFIG_SYS_TEXT_BASE 0xFE000000 51 #endif 52 53 #ifndef CONFIG_SYS_MONITOR_BASE 54 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 55 #endif 56 57 #define CONFIG_PCI 58 #define CONFIG_PCI_INDIRECT_BRIDGE 59 #define CONFIG_FSL_ELBC 1 60 61 #define CONFIG_MISC_INIT_R 62 63 /* 64 * On-board devices 65 * 66 * TSEC1 is VSC switch 67 * TSEC2 is SoC TSEC 68 */ 69 #define CONFIG_VSC7385_ENET 70 #define CONFIG_TSEC2 71 72 #ifdef CONFIG_SYS_66MHZ 73 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 74 #elif defined(CONFIG_SYS_33MHZ) 75 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 76 #else 77 #error Unknown oscillator frequency. 78 #endif 79 80 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 81 82 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ 83 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */ 84 85 #define CONFIG_SYS_IMMR 0xE0000000 86 87 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) 88 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 89 #endif 90 91 #define CONFIG_SYS_MEMTEST_START 0x00001000 92 #define CONFIG_SYS_MEMTEST_END 0x07f00000 93 94 /* Early revs of this board will lock up hard when attempting 95 * to access the PMC registers, unless a JTAG debugger is 96 * connected, or some resistor modifications are made. 97 */ 98 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 99 100 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 101 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 102 103 /* 104 * Device configurations 105 */ 106 107 /* Vitesse 7385 */ 108 109 #ifdef CONFIG_VSC7385_ENET 110 111 #define CONFIG_TSEC1 112 113 /* The flash address and size of the VSC7385 firmware image */ 114 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 115 #define CONFIG_VSC7385_IMAGE_SIZE 8192 116 117 #endif 118 119 /* 120 * DDR Setup 121 */ 122 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 123 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 124 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 125 126 /* 127 * Manually set up DDR parameters, as this board does not 128 * seem to have the SPD connected to I2C. 129 */ 130 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 131 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 132 | CSCONFIG_ODT_RD_NEVER \ 133 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 134 | CSCONFIG_ROW_BIT_13 \ 135 | CSCONFIG_COL_BIT_10) 136 /* 0x80010102 */ 137 138 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 139 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 140 | (0 << TIMING_CFG0_WRT_SHIFT) \ 141 | (0 << TIMING_CFG0_RRT_SHIFT) \ 142 | (0 << TIMING_CFG0_WWT_SHIFT) \ 143 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 144 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 145 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 146 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 147 /* 0x00220802 */ 148 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 149 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 150 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 151 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 152 | (10 << TIMING_CFG1_REFREC_SHIFT) \ 153 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 154 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 155 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 156 /* 0x3835a322 */ 157 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 158 | (5 << TIMING_CFG2_CPO_SHIFT) \ 159 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 160 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 161 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 162 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 163 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 164 /* 0x129048c6 */ /* P9-45,may need tuning */ 165 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 166 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 167 /* 0x05100500 */ 168 #if defined(CONFIG_DDR_2T_TIMING) 169 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 170 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 171 | SDRAM_CFG_DBW_32 \ 172 | SDRAM_CFG_2T_EN) 173 /* 0x43088000 */ 174 #else 175 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 176 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 177 | SDRAM_CFG_DBW_32) 178 /* 0x43080000 */ 179 #endif 180 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 181 /* set burst length to 8 for 32-bit data path */ 182 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 183 | (0x0632 << SDRAM_MODE_SD_SHIFT)) 184 /* 0x44480632 */ 185 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 186 187 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 188 /*0x02000000*/ 189 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 190 | DDRCDR_PZ_NOMZ \ 191 | DDRCDR_NZ_NOMZ \ 192 | DDRCDR_M_ODR) 193 194 /* 195 * FLASH on the Local Bus 196 */ 197 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 198 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 199 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 200 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 201 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 202 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 203 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 204 205 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 206 | BR_PS_16 /* 16 bit port */ \ 207 | BR_MS_GPCM /* MSEL = GPCM */ \ 208 | BR_V) /* valid */ 209 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 210 | OR_GPCM_XACS \ 211 | OR_GPCM_SCY_9 \ 212 | OR_GPCM_EHTR \ 213 | OR_GPCM_EAD) 214 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 215 /* window base at flash base */ 216 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 217 /* 16 MB window size */ 218 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 219 220 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 221 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 222 223 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 224 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 225 226 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 227 !defined(CONFIG_SPL_BUILD) 228 #define CONFIG_SYS_RAMBOOT 229 #endif 230 231 #define CONFIG_SYS_INIT_RAM_LOCK 1 232 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 233 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 234 235 #define CONFIG_SYS_GBL_DATA_OFFSET \ 236 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 237 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 238 239 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 240 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 241 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 242 243 /* 244 * Local Bus LCRR and LBCR regs 245 */ 246 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 247 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 248 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 249 | (0xFF << LBCR_BMT_SHIFT) \ 250 | 0xF) /* 0x0004ff0f */ 251 252 /* LB refresh timer prescal, 266MHz/32 */ 253 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 254 255 /* drivers/mtd/nand/nand.c */ 256 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) 257 #define CONFIG_SYS_NAND_BASE 0xFFF00000 258 #else 259 #define CONFIG_SYS_NAND_BASE 0xE2800000 260 #endif 261 262 #define CONFIG_MTD_DEVICE 263 #define CONFIG_MTD_PARTITION 264 #define CONFIG_CMD_MTDPARTS 265 #define MTDIDS_DEFAULT "nand0=e2800000.flash" 266 #define MTDPARTS_DEFAULT \ 267 "mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" 268 269 #define CONFIG_SYS_MAX_NAND_DEVICE 1 270 #define CONFIG_CMD_NAND 1 271 #define CONFIG_NAND_FSL_ELBC 1 272 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 273 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 274 275 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 276 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 277 | BR_PS_8 /* 8 bit port */ \ 278 | BR_MS_FCM /* MSEL = FCM */ \ 279 | BR_V) /* valid */ 280 #define CONFIG_SYS_NAND_OR_PRELIM \ 281 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 282 | OR_FCM_CSCT \ 283 | OR_FCM_CST \ 284 | OR_FCM_CHT \ 285 | OR_FCM_SCY_1 \ 286 | OR_FCM_TRLX \ 287 | OR_FCM_EHTR) 288 /* 0xFFFF8396 */ 289 290 #ifdef CONFIG_NAND 291 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 292 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 293 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 294 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 295 #else 296 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 297 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 298 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 299 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 300 #endif 301 302 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 303 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 304 305 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 306 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 307 308 /* local bus write LED / read status buffer (BCSR) mapping */ 309 #define CONFIG_SYS_BCSR_ADDR 0xFA000000 310 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 311 /* map at 0xFA000000 on LCS3 */ 312 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 313 | BR_PS_8 /* 8 bit port */ \ 314 | BR_MS_GPCM /* MSEL = GPCM */ \ 315 | BR_V) /* valid */ 316 /* 0xFA000801 */ 317 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 318 | OR_GPCM_CSNT \ 319 | OR_GPCM_ACS_DIV2 \ 320 | OR_GPCM_XACS \ 321 | OR_GPCM_SCY_15 \ 322 | OR_GPCM_TRLX_SET \ 323 | OR_GPCM_EHTR_SET \ 324 | OR_GPCM_EAD) 325 /* 0xFFFF8FF7 */ 326 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 327 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 328 329 /* Vitesse 7385 */ 330 331 #ifdef CONFIG_VSC7385_ENET 332 333 /* VSC7385 Base address on LCS2 */ 334 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 335 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 336 337 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 338 | BR_PS_8 /* 8 bit port */ \ 339 | BR_MS_GPCM /* MSEL = GPCM */ \ 340 | BR_V) /* valid */ 341 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 342 | OR_GPCM_CSNT \ 343 | OR_GPCM_XACS \ 344 | OR_GPCM_SCY_15 \ 345 | OR_GPCM_SETA \ 346 | OR_GPCM_TRLX_SET \ 347 | OR_GPCM_EHTR_SET \ 348 | OR_GPCM_EAD) 349 /* 0xFFFE09FF */ 350 351 /* Access window base at VSC7385 base */ 352 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 353 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 354 355 #endif 356 357 #define CONFIG_MPC83XX_GPIO 1 358 359 /* 360 * Serial Port 361 */ 362 #define CONFIG_CONS_INDEX 1 363 #define CONFIG_SYS_NS16550_SERIAL 364 #define CONFIG_SYS_NS16550_REG_SIZE 1 365 366 #define CONFIG_SYS_BAUDRATE_TABLE \ 367 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 368 369 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 370 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 371 372 /* I2C */ 373 #define CONFIG_SYS_I2C 374 #define CONFIG_SYS_I2C_FSL 375 #define CONFIG_SYS_FSL_I2C_SPEED 400000 376 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 377 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 378 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 379 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 380 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 381 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 382 383 /* 384 * General PCI 385 * Addresses are mapped 1-1. 386 */ 387 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 388 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 389 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 390 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 391 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 392 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 393 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 394 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 395 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 396 397 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 398 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 399 400 /* 401 * TSEC 402 */ 403 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 404 405 #define CONFIG_GMII /* MII PHY management */ 406 407 #ifdef CONFIG_TSEC1 408 #define CONFIG_HAS_ETH0 409 #define CONFIG_TSEC1_NAME "TSEC0" 410 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 411 #define TSEC1_PHY_ADDR 0x1c 412 #define TSEC1_FLAGS TSEC_GIGABIT 413 #define TSEC1_PHYIDX 0 414 #endif 415 416 #ifdef CONFIG_TSEC2 417 #define CONFIG_HAS_ETH1 418 #define CONFIG_TSEC2_NAME "TSEC1" 419 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 420 #define TSEC2_PHY_ADDR 4 421 #define TSEC2_FLAGS TSEC_GIGABIT 422 #define TSEC2_PHYIDX 0 423 #endif 424 425 /* Options are: TSEC[0-1] */ 426 #define CONFIG_ETHPRIME "TSEC1" 427 428 /* 429 * Configure on-board RTC 430 */ 431 #define CONFIG_RTC_DS1337 432 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 433 434 /* 435 * Environment 436 */ 437 #if defined(CONFIG_NAND) 438 #define CONFIG_ENV_IS_IN_NAND 1 439 #define CONFIG_ENV_OFFSET (512 * 1024) 440 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 441 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 442 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 443 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 444 #define CONFIG_ENV_OFFSET_REDUND \ 445 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 446 #elif !defined(CONFIG_SYS_RAMBOOT) 447 #define CONFIG_ENV_IS_IN_FLASH 1 448 #define CONFIG_ENV_ADDR \ 449 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 450 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 451 #define CONFIG_ENV_SIZE 0x2000 452 453 /* Address and size of Redundant Environment Sector */ 454 #else 455 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 456 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 457 #define CONFIG_ENV_SIZE 0x2000 458 #endif 459 460 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 461 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 462 463 /* 464 * BOOTP options 465 */ 466 #define CONFIG_BOOTP_BOOTFILESIZE 467 #define CONFIG_BOOTP_BOOTPATH 468 #define CONFIG_BOOTP_GATEWAY 469 #define CONFIG_BOOTP_HOSTNAME 470 471 /* 472 * Command line configuration. 473 */ 474 #define CONFIG_CMD_DATE 475 #define CONFIG_CMD_PCI 476 477 #define CONFIG_CMDLINE_EDITING 1 478 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 479 480 /* 481 * Miscellaneous configurable options 482 */ 483 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 484 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 485 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 486 487 /* Print Buffer Size */ 488 #define CONFIG_SYS_PBSIZE \ 489 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 490 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 491 /* Boot Argument Buffer Size */ 492 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 493 494 /* 495 * For booting Linux, the board info and command line data 496 * have to be in the first 256 MB of memory, since this is 497 * the maximum mapped by the Linux kernel during initialization. 498 */ 499 /* Initial Memory map for Linux*/ 500 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 501 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 502 503 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 504 505 #ifdef CONFIG_SYS_66MHZ 506 507 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 508 /* 0x62040000 */ 509 #define CONFIG_SYS_HRCW_LOW (\ 510 0x20000000 /* reserved, must be set */ |\ 511 HRCWL_DDRCM |\ 512 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 513 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 514 HRCWL_CSB_TO_CLKIN_2X1 |\ 515 HRCWL_CORE_TO_CSB_2X1) 516 517 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 518 519 #elif defined(CONFIG_SYS_33MHZ) 520 521 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 522 /* 0x65040000 */ 523 #define CONFIG_SYS_HRCW_LOW (\ 524 0x20000000 /* reserved, must be set */ |\ 525 HRCWL_DDRCM |\ 526 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 527 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 528 HRCWL_CSB_TO_CLKIN_5X1 |\ 529 HRCWL_CORE_TO_CSB_2X1) 530 531 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 532 533 #endif 534 535 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 536 HRCWH_PCI_HOST |\ 537 HRCWH_PCI1_ARBITER_ENABLE |\ 538 HRCWH_CORE_ENABLE |\ 539 HRCWH_BOOTSEQ_DISABLE |\ 540 HRCWH_SW_WATCHDOG_DISABLE |\ 541 HRCWH_TSEC1M_IN_RGMII |\ 542 HRCWH_TSEC2M_IN_RGMII |\ 543 HRCWH_BIG_ENDIAN) 544 545 #ifdef CONFIG_NAND 546 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 547 HRCWH_FROM_0XFFF00100 |\ 548 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 549 HRCWH_RL_EXT_NAND) 550 #else 551 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 552 HRCWH_FROM_0X00000100 |\ 553 HRCWH_ROM_LOC_LOCAL_16BIT |\ 554 HRCWH_RL_EXT_LEGACY) 555 #endif 556 557 /* System IO Config */ 558 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 559 /* Enable Internal USB Phy and GPIO on LCD Connector */ 560 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 561 562 #define CONFIG_SYS_HID0_INIT 0x000000000 563 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 564 HID0_ENABLE_INSTRUCTION_CACHE | \ 565 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 566 567 #define CONFIG_SYS_HID2 HID2_HBE 568 569 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 570 571 /* DDR @ 0x00000000 */ 572 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 573 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 574 | BATU_BL_256M \ 575 | BATU_VS \ 576 | BATU_VP) 577 578 /* PCI @ 0x80000000 */ 579 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 580 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 581 | BATU_BL_256M \ 582 | BATU_VS \ 583 | BATU_VP) 584 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 585 | BATL_PP_RW \ 586 | BATL_CACHEINHIBIT \ 587 | BATL_GUARDEDSTORAGE) 588 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 589 | BATU_BL_256M \ 590 | BATU_VS \ 591 | BATU_VP) 592 593 /* PCI2 not supported on 8313 */ 594 #define CONFIG_SYS_IBAT3L (0) 595 #define CONFIG_SYS_IBAT3U (0) 596 #define CONFIG_SYS_IBAT4L (0) 597 #define CONFIG_SYS_IBAT4U (0) 598 599 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 600 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 601 | BATL_PP_RW \ 602 | BATL_CACHEINHIBIT \ 603 | BATL_GUARDEDSTORAGE) 604 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 605 | BATU_BL_256M \ 606 | BATU_VS \ 607 | BATU_VP) 608 609 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 610 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 611 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 612 613 #define CONFIG_SYS_IBAT7L (0) 614 #define CONFIG_SYS_IBAT7U (0) 615 616 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 617 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 618 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 619 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 620 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 621 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 622 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 623 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 624 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 625 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 626 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 627 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 628 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 629 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 630 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 631 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 632 633 /* 634 * Environment Configuration 635 */ 636 #define CONFIG_ENV_OVERWRITE 637 638 #define CONFIG_NETDEV "eth1" 639 640 #define CONFIG_HOSTNAME mpc8313erdb 641 #define CONFIG_ROOTPATH "/nfs/root/path" 642 #define CONFIG_BOOTFILE "uImage" 643 /* U-Boot image on TFTP server */ 644 #define CONFIG_UBOOTPATH "u-boot.bin" 645 #define CONFIG_FDTFILE "mpc8313erdb.dtb" 646 647 /* default location for tftp and bootm */ 648 #define CONFIG_LOADADDR 800000 649 #define CONFIG_BAUDRATE 115200 650 651 #define CONFIG_EXTRA_ENV_SETTINGS \ 652 "netdev=" CONFIG_NETDEV "\0" \ 653 "ethprime=TSEC1\0" \ 654 "uboot=" CONFIG_UBOOTPATH "\0" \ 655 "tftpflash=tftpboot $loadaddr $uboot; " \ 656 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 657 " +$filesize; " \ 658 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 659 " +$filesize; " \ 660 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 661 " $filesize; " \ 662 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 663 " +$filesize; " \ 664 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 665 " $filesize\0" \ 666 "fdtaddr=780000\0" \ 667 "fdtfile=" CONFIG_FDTFILE "\0" \ 668 "console=ttyS0\0" \ 669 "setbootargs=setenv bootargs " \ 670 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 671 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 672 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 673 "$netdev:off " \ 674 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 675 676 #define CONFIG_NFSBOOTCOMMAND \ 677 "setenv rootdev /dev/nfs;" \ 678 "run setbootargs;" \ 679 "run setipargs;" \ 680 "tftp $loadaddr $bootfile;" \ 681 "tftp $fdtaddr $fdtfile;" \ 682 "bootm $loadaddr - $fdtaddr" 683 684 #define CONFIG_RAMBOOTCOMMAND \ 685 "setenv rootdev /dev/ram;" \ 686 "run setbootargs;" \ 687 "tftp $ramdiskaddr $ramdiskfile;" \ 688 "tftp $loadaddr $bootfile;" \ 689 "tftp $fdtaddr $fdtfile;" \ 690 "bootm $loadaddr $ramdiskaddr $fdtaddr" 691 692 #endif /* __CONFIG_H */ 693