1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 /* 23 * mpc8313epb board configuration file 24 */ 25 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* 30 * High Level Configuration Options 31 */ 32 #define CONFIG_E300 1 33 #define CONFIG_MPC83xx 1 34 #define CONFIG_MPC831x 1 35 #define CONFIG_MPC8313 1 36 #define CONFIG_MPC8313ERDB 1 37 38 #ifdef CONFIG_NAND 39 #define CONFIG_SPL 40 #define CONFIG_SPL_INIT_MINIMAL 41 #define CONFIG_SPL_SERIAL_SUPPORT 42 #define CONFIG_SPL_NAND_SUPPORT 43 #define CONFIG_SPL_NAND_MINIMAL 44 #define CONFIG_SPL_FLUSH_IMAGE 45 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 46 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 47 48 #ifdef CONFIG_SPL_BUILD 49 #define CONFIG_NS16550_MIN_FUNCTIONS 50 #endif 51 52 #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 53 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 54 #define CONFIG_SPL_MAX_SIZE (4 * 1024) 55 #define CONFIG_SPL_PAD_TO 0x4000 56 57 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 58 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 59 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 60 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 61 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 62 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 63 64 #ifdef CONFIG_SPL_BUILD 65 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 66 #endif 67 68 #endif /* CONFIG_NAND */ 69 70 #ifndef CONFIG_SYS_TEXT_BASE 71 #define CONFIG_SYS_TEXT_BASE 0xFE000000 72 #endif 73 74 #ifndef CONFIG_SYS_MONITOR_BASE 75 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 76 #endif 77 78 #define CONFIG_PCI 79 #define CONFIG_PCI_INDIRECT_BRIDGE 80 #define CONFIG_FSL_ELBC 1 81 82 #define CONFIG_MISC_INIT_R 83 84 /* 85 * On-board devices 86 * 87 * TSEC1 is VSC switch 88 * TSEC2 is SoC TSEC 89 */ 90 #define CONFIG_VSC7385_ENET 91 #define CONFIG_TSEC2 92 93 #ifdef CONFIG_SYS_66MHZ 94 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 95 #elif defined(CONFIG_SYS_33MHZ) 96 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 97 #else 98 #error Unknown oscillator frequency. 99 #endif 100 101 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 102 103 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ 104 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */ 105 106 #define CONFIG_SYS_IMMR 0xE0000000 107 108 #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) 109 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 110 #endif 111 112 #define CONFIG_SYS_MEMTEST_START 0x00001000 113 #define CONFIG_SYS_MEMTEST_END 0x07f00000 114 115 /* Early revs of this board will lock up hard when attempting 116 * to access the PMC registers, unless a JTAG debugger is 117 * connected, or some resistor modifications are made. 118 */ 119 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 120 121 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 122 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 123 124 /* 125 * Device configurations 126 */ 127 128 /* Vitesse 7385 */ 129 130 #ifdef CONFIG_VSC7385_ENET 131 132 #define CONFIG_TSEC1 133 134 /* The flash address and size of the VSC7385 firmware image */ 135 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 136 #define CONFIG_VSC7385_IMAGE_SIZE 8192 137 138 #endif 139 140 /* 141 * DDR Setup 142 */ 143 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 144 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 145 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 146 147 /* 148 * Manually set up DDR parameters, as this board does not 149 * seem to have the SPD connected to I2C. 150 */ 151 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 152 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 153 | CSCONFIG_ODT_RD_NEVER \ 154 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 155 | CSCONFIG_ROW_BIT_13 \ 156 | CSCONFIG_COL_BIT_10) 157 /* 0x80010102 */ 158 159 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 160 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 161 | (0 << TIMING_CFG0_WRT_SHIFT) \ 162 | (0 << TIMING_CFG0_RRT_SHIFT) \ 163 | (0 << TIMING_CFG0_WWT_SHIFT) \ 164 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 165 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 166 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 167 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 168 /* 0x00220802 */ 169 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 170 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 171 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 172 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 173 | (10 << TIMING_CFG1_REFREC_SHIFT) \ 174 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 175 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 176 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 177 /* 0x3835a322 */ 178 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 179 | (5 << TIMING_CFG2_CPO_SHIFT) \ 180 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 181 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 182 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 183 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 184 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 185 /* 0x129048c6 */ /* P9-45,may need tuning */ 186 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 187 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 188 /* 0x05100500 */ 189 #if defined(CONFIG_DDR_2T_TIMING) 190 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 191 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 192 | SDRAM_CFG_DBW_32 \ 193 | SDRAM_CFG_2T_EN) 194 /* 0x43088000 */ 195 #else 196 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 197 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 198 | SDRAM_CFG_DBW_32) 199 /* 0x43080000 */ 200 #endif 201 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 202 /* set burst length to 8 for 32-bit data path */ 203 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 204 | (0x0632 << SDRAM_MODE_SD_SHIFT)) 205 /* 0x44480632 */ 206 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 207 208 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 209 /*0x02000000*/ 210 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 211 | DDRCDR_PZ_NOMZ \ 212 | DDRCDR_NZ_NOMZ \ 213 | DDRCDR_M_ODR) 214 215 /* 216 * FLASH on the Local Bus 217 */ 218 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 219 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 220 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 221 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 222 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 223 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 224 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 225 226 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 227 | BR_PS_16 /* 16 bit port */ \ 228 | BR_MS_GPCM /* MSEL = GPCM */ \ 229 | BR_V) /* valid */ 230 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 231 | OR_GPCM_XACS \ 232 | OR_GPCM_SCY_9 \ 233 | OR_GPCM_EHTR \ 234 | OR_GPCM_EAD) 235 /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 236 /* window base at flash base */ 237 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 238 /* 16 MB window size */ 239 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 240 241 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 242 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 243 244 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 245 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 246 247 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 248 !defined(CONFIG_SPL_BUILD) 249 #define CONFIG_SYS_RAMBOOT 250 #endif 251 252 #define CONFIG_SYS_INIT_RAM_LOCK 1 253 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 254 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 255 256 #define CONFIG_SYS_GBL_DATA_OFFSET \ 257 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 258 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 259 260 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 261 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 262 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 263 264 /* 265 * Local Bus LCRR and LBCR regs 266 */ 267 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 268 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 269 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 270 | (0xFF << LBCR_BMT_SHIFT) \ 271 | 0xF) /* 0x0004ff0f */ 272 273 /* LB refresh timer prescal, 266MHz/32 */ 274 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 275 276 /* drivers/mtd/nand/nand.c */ 277 #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) 278 #define CONFIG_SYS_NAND_BASE 0xFFF00000 279 #else 280 #define CONFIG_SYS_NAND_BASE 0xE2800000 281 #endif 282 283 #define CONFIG_MTD_DEVICE 284 #define CONFIG_MTD_PARTITION 285 #define CONFIG_CMD_MTDPARTS 286 #define MTDIDS_DEFAULT "nand0=e2800000.flash" 287 #define MTDPARTS_DEFAULT \ 288 "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" 289 290 #define CONFIG_SYS_MAX_NAND_DEVICE 1 291 #define CONFIG_MTD_NAND_VERIFY_WRITE 292 #define CONFIG_CMD_NAND 1 293 #define CONFIG_NAND_FSL_ELBC 1 294 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 295 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 296 297 298 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 299 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 300 | BR_PS_8 /* 8 bit port */ \ 301 | BR_MS_FCM /* MSEL = FCM */ \ 302 | BR_V) /* valid */ 303 #define CONFIG_SYS_NAND_OR_PRELIM \ 304 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 305 | OR_FCM_CSCT \ 306 | OR_FCM_CST \ 307 | OR_FCM_CHT \ 308 | OR_FCM_SCY_1 \ 309 | OR_FCM_TRLX \ 310 | OR_FCM_EHTR) 311 /* 0xFFFF8396 */ 312 313 #ifdef CONFIG_NAND 314 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 315 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 316 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 317 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 318 #else 319 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 320 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 321 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 322 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 323 #endif 324 325 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 326 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 327 328 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 329 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 330 331 /* local bus write LED / read status buffer (BCSR) mapping */ 332 #define CONFIG_SYS_BCSR_ADDR 0xFA000000 333 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 334 /* map at 0xFA000000 on LCS3 */ 335 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 336 | BR_PS_8 /* 8 bit port */ \ 337 | BR_MS_GPCM /* MSEL = GPCM */ \ 338 | BR_V) /* valid */ 339 /* 0xFA000801 */ 340 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 341 | OR_GPCM_CSNT \ 342 | OR_GPCM_ACS_DIV2 \ 343 | OR_GPCM_XACS \ 344 | OR_GPCM_SCY_15 \ 345 | OR_GPCM_TRLX_SET \ 346 | OR_GPCM_EHTR_SET \ 347 | OR_GPCM_EAD) 348 /* 0xFFFF8FF7 */ 349 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 350 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 351 352 /* Vitesse 7385 */ 353 354 #ifdef CONFIG_VSC7385_ENET 355 356 /* VSC7385 Base address on LCS2 */ 357 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 358 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 359 360 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 361 | BR_PS_8 /* 8 bit port */ \ 362 | BR_MS_GPCM /* MSEL = GPCM */ \ 363 | BR_V) /* valid */ 364 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 365 | OR_GPCM_CSNT \ 366 | OR_GPCM_XACS \ 367 | OR_GPCM_SCY_15 \ 368 | OR_GPCM_SETA \ 369 | OR_GPCM_TRLX_SET \ 370 | OR_GPCM_EHTR_SET \ 371 | OR_GPCM_EAD) 372 /* 0xFFFE09FF */ 373 374 /* Access window base at VSC7385 base */ 375 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 376 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 377 378 #endif 379 380 /* pass open firmware flat tree */ 381 #define CONFIG_OF_LIBFDT 1 382 #define CONFIG_OF_BOARD_SETUP 1 383 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 384 385 #define CONFIG_MPC83XX_GPIO 1 386 #define CONFIG_CMD_GPIO 1 387 388 /* 389 * Serial Port 390 */ 391 #define CONFIG_CONS_INDEX 1 392 #define CONFIG_SYS_NS16550 393 #define CONFIG_SYS_NS16550_SERIAL 394 #define CONFIG_SYS_NS16550_REG_SIZE 1 395 396 #define CONFIG_SYS_BAUDRATE_TABLE \ 397 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 398 399 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 400 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 401 402 /* Use the HUSH parser */ 403 #define CONFIG_SYS_HUSH_PARSER 404 405 /* I2C */ 406 #define CONFIG_SYS_I2C 407 #define CONFIG_SYS_I2C_FSL 408 #define CONFIG_SYS_FSL_I2C_SPEED 400000 409 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 410 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 411 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 412 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 413 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 414 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 415 416 /* 417 * General PCI 418 * Addresses are mapped 1-1. 419 */ 420 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 421 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 422 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 423 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 424 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 425 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 426 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 427 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 428 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 429 430 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 431 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 432 433 /* 434 * TSEC 435 */ 436 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 437 438 #define CONFIG_GMII /* MII PHY management */ 439 440 #ifdef CONFIG_TSEC1 441 #define CONFIG_HAS_ETH0 442 #define CONFIG_TSEC1_NAME "TSEC0" 443 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 444 #define TSEC1_PHY_ADDR 0x1c 445 #define TSEC1_FLAGS TSEC_GIGABIT 446 #define TSEC1_PHYIDX 0 447 #endif 448 449 #ifdef CONFIG_TSEC2 450 #define CONFIG_HAS_ETH1 451 #define CONFIG_TSEC2_NAME "TSEC1" 452 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 453 #define TSEC2_PHY_ADDR 4 454 #define TSEC2_FLAGS TSEC_GIGABIT 455 #define TSEC2_PHYIDX 0 456 #endif 457 458 459 /* Options are: TSEC[0-1] */ 460 #define CONFIG_ETHPRIME "TSEC1" 461 462 /* 463 * Configure on-board RTC 464 */ 465 #define CONFIG_RTC_DS1337 466 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 467 468 /* 469 * Environment 470 */ 471 #if defined(CONFIG_NAND) 472 #define CONFIG_ENV_IS_IN_NAND 1 473 #define CONFIG_ENV_OFFSET (512 * 1024) 474 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 475 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 476 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 477 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 478 #define CONFIG_ENV_OFFSET_REDUND \ 479 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 480 #elif !defined(CONFIG_SYS_RAMBOOT) 481 #define CONFIG_ENV_IS_IN_FLASH 1 482 #define CONFIG_ENV_ADDR \ 483 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 484 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 485 #define CONFIG_ENV_SIZE 0x2000 486 487 /* Address and size of Redundant Environment Sector */ 488 #else 489 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 490 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 491 #define CONFIG_ENV_SIZE 0x2000 492 #endif 493 494 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 495 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 496 497 /* 498 * BOOTP options 499 */ 500 #define CONFIG_BOOTP_BOOTFILESIZE 501 #define CONFIG_BOOTP_BOOTPATH 502 #define CONFIG_BOOTP_GATEWAY 503 #define CONFIG_BOOTP_HOSTNAME 504 505 506 /* 507 * Command line configuration. 508 */ 509 #include <config_cmd_default.h> 510 511 #define CONFIG_CMD_PING 512 #define CONFIG_CMD_DHCP 513 #define CONFIG_CMD_I2C 514 #define CONFIG_CMD_MII 515 #define CONFIG_CMD_DATE 516 #define CONFIG_CMD_PCI 517 518 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND) 519 #undef CONFIG_CMD_SAVEENV 520 #undef CONFIG_CMD_LOADS 521 #endif 522 523 #define CONFIG_CMDLINE_EDITING 1 524 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 525 526 /* 527 * Miscellaneous configurable options 528 */ 529 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 530 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 531 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 532 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 533 534 /* Print Buffer Size */ 535 #define CONFIG_SYS_PBSIZE \ 536 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 537 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 538 /* Boot Argument Buffer Size */ 539 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 540 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 541 542 /* 543 * For booting Linux, the board info and command line data 544 * have to be in the first 256 MB of memory, since this is 545 * the maximum mapped by the Linux kernel during initialization. 546 */ 547 /* Initial Memory map for Linux*/ 548 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 549 550 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 551 552 #ifdef CONFIG_SYS_66MHZ 553 554 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 555 /* 0x62040000 */ 556 #define CONFIG_SYS_HRCW_LOW (\ 557 0x20000000 /* reserved, must be set */ |\ 558 HRCWL_DDRCM |\ 559 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 560 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 561 HRCWL_CSB_TO_CLKIN_2X1 |\ 562 HRCWL_CORE_TO_CSB_2X1) 563 564 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 565 566 #elif defined(CONFIG_SYS_33MHZ) 567 568 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 569 /* 0x65040000 */ 570 #define CONFIG_SYS_HRCW_LOW (\ 571 0x20000000 /* reserved, must be set */ |\ 572 HRCWL_DDRCM |\ 573 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 574 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 575 HRCWL_CSB_TO_CLKIN_5X1 |\ 576 HRCWL_CORE_TO_CSB_2X1) 577 578 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 579 580 #endif 581 582 #define CONFIG_SYS_HRCW_HIGH_BASE (\ 583 HRCWH_PCI_HOST |\ 584 HRCWH_PCI1_ARBITER_ENABLE |\ 585 HRCWH_CORE_ENABLE |\ 586 HRCWH_BOOTSEQ_DISABLE |\ 587 HRCWH_SW_WATCHDOG_DISABLE |\ 588 HRCWH_TSEC1M_IN_RGMII |\ 589 HRCWH_TSEC2M_IN_RGMII |\ 590 HRCWH_BIG_ENDIAN) 591 592 #ifdef CONFIG_NAND 593 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 594 HRCWH_FROM_0XFFF00100 |\ 595 HRCWH_ROM_LOC_NAND_SP_8BIT |\ 596 HRCWH_RL_EXT_NAND) 597 #else 598 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 599 HRCWH_FROM_0X00000100 |\ 600 HRCWH_ROM_LOC_LOCAL_16BIT |\ 601 HRCWH_RL_EXT_LEGACY) 602 #endif 603 604 /* System IO Config */ 605 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 606 /* Enable Internal USB Phy and GPIO on LCD Connector */ 607 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 608 609 #define CONFIG_SYS_HID0_INIT 0x000000000 610 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 611 HID0_ENABLE_INSTRUCTION_CACHE | \ 612 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 613 614 #define CONFIG_SYS_HID2 HID2_HBE 615 616 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 617 618 /* DDR @ 0x00000000 */ 619 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 620 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 621 | BATU_BL_256M \ 622 | BATU_VS \ 623 | BATU_VP) 624 625 /* PCI @ 0x80000000 */ 626 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 627 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 628 | BATU_BL_256M \ 629 | BATU_VS \ 630 | BATU_VP) 631 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 632 | BATL_PP_RW \ 633 | BATL_CACHEINHIBIT \ 634 | BATL_GUARDEDSTORAGE) 635 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 636 | BATU_BL_256M \ 637 | BATU_VS \ 638 | BATU_VP) 639 640 /* PCI2 not supported on 8313 */ 641 #define CONFIG_SYS_IBAT3L (0) 642 #define CONFIG_SYS_IBAT3U (0) 643 #define CONFIG_SYS_IBAT4L (0) 644 #define CONFIG_SYS_IBAT4U (0) 645 646 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 647 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 648 | BATL_PP_RW \ 649 | BATL_CACHEINHIBIT \ 650 | BATL_GUARDEDSTORAGE) 651 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 652 | BATU_BL_256M \ 653 | BATU_VS \ 654 | BATU_VP) 655 656 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 657 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 658 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 659 660 #define CONFIG_SYS_IBAT7L (0) 661 #define CONFIG_SYS_IBAT7U (0) 662 663 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 664 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 665 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 666 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 667 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 668 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 669 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 670 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 671 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 672 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 673 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 674 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 675 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 676 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 677 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 678 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 679 680 /* 681 * Environment Configuration 682 */ 683 #define CONFIG_ENV_OVERWRITE 684 685 #define CONFIG_NETDEV "eth1" 686 687 #define CONFIG_HOSTNAME mpc8313erdb 688 #define CONFIG_ROOTPATH "/nfs/root/path" 689 #define CONFIG_BOOTFILE "uImage" 690 /* U-Boot image on TFTP server */ 691 #define CONFIG_UBOOTPATH "u-boot.bin" 692 #define CONFIG_FDTFILE "mpc8313erdb.dtb" 693 694 /* default location for tftp and bootm */ 695 #define CONFIG_LOADADDR 800000 696 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 697 #define CONFIG_BAUDRATE 115200 698 699 #define CONFIG_EXTRA_ENV_SETTINGS \ 700 "netdev=" CONFIG_NETDEV "\0" \ 701 "ethprime=TSEC1\0" \ 702 "uboot=" CONFIG_UBOOTPATH "\0" \ 703 "tftpflash=tftpboot $loadaddr $uboot; " \ 704 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 705 " +$filesize; " \ 706 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 707 " +$filesize; " \ 708 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 709 " $filesize; " \ 710 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 711 " +$filesize; " \ 712 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 713 " $filesize\0" \ 714 "fdtaddr=780000\0" \ 715 "fdtfile=" CONFIG_FDTFILE "\0" \ 716 "console=ttyS0\0" \ 717 "setbootargs=setenv bootargs " \ 718 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 719 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 720 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 721 "$netdev:off " \ 722 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 723 724 #define CONFIG_NFSBOOTCOMMAND \ 725 "setenv rootdev /dev/nfs;" \ 726 "run setbootargs;" \ 727 "run setipargs;" \ 728 "tftp $loadaddr $bootfile;" \ 729 "tftp $fdtaddr $fdtfile;" \ 730 "bootm $loadaddr - $fdtaddr" 731 732 #define CONFIG_RAMBOOTCOMMAND \ 733 "setenv rootdev /dev/ram;" \ 734 "run setbootargs;" \ 735 "tftp $ramdiskaddr $ramdiskfile;" \ 736 "tftp $loadaddr $bootfile;" \ 737 "tftp $fdtaddr $fdtfile;" \ 738 "bootm $loadaddr $ramdiskaddr $fdtaddr" 739 740 #endif /* __CONFIG_H */ 741