196b8a054SScott Wood /* 2e8d3ca8bSScott Wood * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 396b8a054SScott Wood * 496b8a054SScott Wood * See file CREDITS for list of people who contributed to this 596b8a054SScott Wood * project. 696b8a054SScott Wood * 796b8a054SScott Wood * This program is free software; you can redistribute it and/or 896b8a054SScott Wood * modify it under the terms of the GNU General Public License as 996b8a054SScott Wood * published by the Free Software Foundation; either version 2 of 1096b8a054SScott Wood * the License, or (at your option) any later version. 1196b8a054SScott Wood * 1296b8a054SScott Wood * This program is distributed in the hope that it will be useful, 1396b8a054SScott Wood * but WITHOUT ANY WARRANTY; without even the implied warranty of 1496b8a054SScott Wood * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1596b8a054SScott Wood * GNU General Public License for more details. 1696b8a054SScott Wood * 1796b8a054SScott Wood * You should have received a copy of the GNU General Public License 1896b8a054SScott Wood * along with this program; if not, write to the Free Software 1996b8a054SScott Wood * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 2096b8a054SScott Wood * MA 02111-1307 USA 2196b8a054SScott Wood */ 2296b8a054SScott Wood /* 2396b8a054SScott Wood * mpc8313epb board configuration file 2496b8a054SScott Wood */ 2596b8a054SScott Wood 2696b8a054SScott Wood #ifndef __CONFIG_H 2796b8a054SScott Wood #define __CONFIG_H 2896b8a054SScott Wood 2996b8a054SScott Wood /* 3096b8a054SScott Wood * High Level Configuration Options 3196b8a054SScott Wood */ 3296b8a054SScott Wood #define CONFIG_E300 1 330f898604SPeter Tyser #define CONFIG_MPC83xx 1 342c7920afSPeter Tyser #define CONFIG_MPC831x 1 3596b8a054SScott Wood #define CONFIG_MPC8313 1 3696b8a054SScott Wood #define CONFIG_MPC8313ERDB 1 3796b8a054SScott Wood 38f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 39f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 40f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 41f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 42f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 43f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 44f1c574d4SScott Wood 45f1c574d4SScott Wood #ifdef CONFIG_NAND_U_BOOT 46f1c574d4SScott Wood #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 47f1c574d4SScott Wood #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 48f1c574d4SScott Wood #ifdef CONFIG_NAND_SPL 49f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 50f1c574d4SScott Wood #endif /* CONFIG_NAND_SPL */ 51f1c574d4SScott Wood #endif /* CONFIG_NAND_U_BOOT */ 52f1c574d4SScott Wood 532ae18241SWolfgang Denk #ifndef CONFIG_SYS_TEXT_BASE 542ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFE000000 552ae18241SWolfgang Denk #endif 562ae18241SWolfgang Denk 57f1c574d4SScott Wood #ifndef CONFIG_SYS_MONITOR_BASE 58f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 59f1c574d4SScott Wood #endif 60f1c574d4SScott Wood 6196b8a054SScott Wood #define CONFIG_PCI 620914f483SBecky Bruce #define CONFIG_FSL_ELBC 1 6396b8a054SScott Wood 6489c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 6589c7784eSTimur Tabi 6689c7784eSTimur Tabi /* 6789c7784eSTimur Tabi * On-board devices 684ce1e23bSYork Sun * 694ce1e23bSYork Sun * TSEC1 is VSC switch 704ce1e23bSYork Sun * TSEC2 is SoC TSEC 7189c7784eSTimur Tabi */ 7289c7784eSTimur Tabi #define CONFIG_VSC7385_ENET 734ce1e23bSYork Sun #define CONFIG_TSEC2 7489c7784eSTimur Tabi 756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 765c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 785c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 7996b8a054SScott Wood #else 8096b8a054SScott Wood #error Unknown oscillator frequency. 8196b8a054SScott Wood #endif 8296b8a054SScott Wood 8396b8a054SScott Wood #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 8496b8a054SScott Wood 850eaf8f9eSJoe Hershberger #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ 860eaf8f9eSJoe Hershberger #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */ 8796b8a054SScott Wood 886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 8996b8a054SScott Wood 90e4c09508SScott Wood #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 92e4c09508SScott Wood #endif 93e4c09508SScott Wood 946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00001000 956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x07f00000 9696b8a054SScott Wood 9796b8a054SScott Wood /* Early revs of this board will lock up hard when attempting 9896b8a054SScott Wood * to access the PMC registers, unless a JTAG debugger is 9996b8a054SScott Wood * connected, or some resistor modifications are made. 10096b8a054SScott Wood */ 1016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 10296b8a054SScott Wood 1036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 1046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 10596b8a054SScott Wood 10696b8a054SScott Wood /* 10789c7784eSTimur Tabi * Device configurations 10889c7784eSTimur Tabi */ 10989c7784eSTimur Tabi 11089c7784eSTimur Tabi /* Vitesse 7385 */ 11189c7784eSTimur Tabi 11289c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 11389c7784eSTimur Tabi 1144ce1e23bSYork Sun #define CONFIG_TSEC1 11589c7784eSTimur Tabi 11689c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 11789c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFE7FE000 11889c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 11989c7784eSTimur Tabi 12089c7784eSTimur Tabi #endif 12189c7784eSTimur Tabi 12289c7784eSTimur Tabi /* 12396b8a054SScott Wood * DDR Setup 12496b8a054SScott Wood */ 1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 12896b8a054SScott Wood 12996b8a054SScott Wood /* 13096b8a054SScott Wood * Manually set up DDR parameters, as this board does not 13196b8a054SScott Wood * seem to have the SPD connected to I2C. 13296b8a054SScott Wood */ 1336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 1342e651b24SJoe Hershberger #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 1352fef4020SJoe Hershberger | CSCONFIG_ODT_RD_NEVER \ 1362fef4020SJoe Hershberger | CSCONFIG_ODT_WR_ONLY_CURRENT \ 137261c07bcSJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 138261c07bcSJoe Hershberger | CSCONFIG_COL_BIT_10) 139e1d8ed2cSPoonam Aggrwal /* 0x80010102 */ 14096b8a054SScott Wood 1416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_3 0x00000000 1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 14396b8a054SScott Wood | (0 << TIMING_CFG0_WRT_SHIFT) \ 14496b8a054SScott Wood | (0 << TIMING_CFG0_RRT_SHIFT) \ 14596b8a054SScott Wood | (0 << TIMING_CFG0_WWT_SHIFT) \ 14696b8a054SScott Wood | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 14796b8a054SScott Wood | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 14896b8a054SScott Wood | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 14996b8a054SScott Wood | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 15096b8a054SScott Wood /* 0x00220802 */ 1516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 152e1d8ed2cSPoonam Aggrwal | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 15396b8a054SScott Wood | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 15496b8a054SScott Wood | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 155e1d8ed2cSPoonam Aggrwal | (10 << TIMING_CFG1_REFREC_SHIFT) \ 15696b8a054SScott Wood | (3 << TIMING_CFG1_WRREC_SHIFT) \ 15796b8a054SScott Wood | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 15896b8a054SScott Wood | (2 << TIMING_CFG1_WRTORD_SHIFT)) 159e1d8ed2cSPoonam Aggrwal /* 0x3835a322 */ 1606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 161e1d8ed2cSPoonam Aggrwal | (5 << TIMING_CFG2_CPO_SHIFT) \ 16296b8a054SScott Wood | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 16396b8a054SScott Wood | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 16496b8a054SScott Wood | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 16596b8a054SScott Wood | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 166e1d8ed2cSPoonam Aggrwal | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 167e1d8ed2cSPoonam Aggrwal /* 0x129048c6 */ /* P9-45,may need tuning */ 1686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 169e1d8ed2cSPoonam Aggrwal | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 170e1d8ed2cSPoonam Aggrwal /* 0x05100500 */ 17196b8a054SScott Wood #if defined(CONFIG_DDR_2T_TIMING) 1726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 173bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1742fef4020SJoe Hershberger | SDRAM_CFG_DBW_32 \ 1752fef4020SJoe Hershberger | SDRAM_CFG_2T_EN) 1762fef4020SJoe Hershberger /* 0x43088000 */ 17796b8a054SScott Wood #else 1786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 179bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1802fef4020SJoe Hershberger | SDRAM_CFG_DBW_32) 18196b8a054SScott Wood /* 0x43080000 */ 18296b8a054SScott Wood #endif 1836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG2 0x00401000 18496b8a054SScott Wood /* set burst length to 8 for 32-bit data path */ 1856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 186e1d8ed2cSPoonam Aggrwal | (0x0632 << SDRAM_MODE_SD_SHIFT)) 187e1d8ed2cSPoonam Aggrwal /* 0x44480632 */ 1886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x8000C000 18996b8a054SScott Wood 1906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 19196b8a054SScott Wood /*0x02000000*/ 1926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 19396b8a054SScott Wood | DDRCDR_PZ_NOMZ \ 19496b8a054SScott Wood | DDRCDR_NZ_NOMZ \ 19596b8a054SScott Wood | DDRCDR_M_ODR) 19696b8a054SScott Wood 19796b8a054SScott Wood /* 19896b8a054SScott Wood * FLASH on the Local Bus 19996b8a054SScott Wood */ 2006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 20100b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 2036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 2046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 2066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 20796b8a054SScott Wood 208261c07bcSJoe Hershberger #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 2097d6a0982SJoe Hershberger | BR_PS_16 /* 16 bit port */ \ 2107d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 211261c07bcSJoe Hershberger | BR_V) /* valid */ 2127d6a0982SJoe Hershberger #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 21396b8a054SScott Wood | OR_GPCM_XACS \ 21496b8a054SScott Wood | OR_GPCM_SCY_9 \ 21596b8a054SScott Wood | OR_GPCM_EHTR \ 21696b8a054SScott Wood | OR_GPCM_EAD) 21796b8a054SScott Wood /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 218261c07bcSJoe Hershberger /* window base at flash base */ 219261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2207d6a0982SJoe Hershberger /* 16 MB window size */ 2217d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 22296b8a054SScott Wood 2236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 2246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 22596b8a054SScott Wood 2266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 22896b8a054SScott Wood 229261c07bcSJoe Hershberger #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 230261c07bcSJoe Hershberger !defined(CONFIG_NAND_SPL) 2316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 23296b8a054SScott Wood #endif 23396b8a054SScott Wood 2346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 235261c07bcSJoe Hershberger #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 236553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 23796b8a054SScott Wood 238261c07bcSJoe Hershberger #define CONFIG_SYS_GBL_DATA_OFFSET \ 239261c07bcSJoe Hershberger (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 24196b8a054SScott Wood 2426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 2434a9932a4SKim Phillips #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 2446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 24596b8a054SScott Wood 24696b8a054SScott Wood /* 24796b8a054SScott Wood * Local Bus LCRR and LBCR regs 24896b8a054SScott Wood */ 249c7190f02SKim Phillips #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 250c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 2516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 25296b8a054SScott Wood | (0xFF << LBCR_BMT_SHIFT) \ 25396b8a054SScott Wood | 0xF) /* 0x0004ff0f */ 25496b8a054SScott Wood 255261c07bcSJoe Hershberger /* LB refresh timer prescal, 266MHz/32 */ 256261c07bcSJoe Hershberger #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 25796b8a054SScott Wood 2587817cb20SMarcel Ziswiler /* drivers/mtd/nand/nand.c */ 259e4c09508SScott Wood #ifdef CONFIG_NAND_SPL 2606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xFFF00000 261e4c09508SScott Wood #else 2626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xE2800000 263e4c09508SScott Wood #endif 264e4c09508SScott Wood 265e8d3ca8bSScott Wood #define CONFIG_MTD_DEVICE 266e8d3ca8bSScott Wood #define CONFIG_MTD_PARTITION 267e8d3ca8bSScott Wood #define CONFIG_CMD_MTDPARTS 268e8d3ca8bSScott Wood #define MTDIDS_DEFAULT "nand0=e2800000.flash" 269e8d3ca8bSScott Wood #define MTDPARTS_DEFAULT \ 270*c947c12eSScott Wood "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" 271e8d3ca8bSScott Wood 2726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_NAND_DEVICE 1 27396b8a054SScott Wood #define CONFIG_MTD_NAND_VERIFY_WRITE 274acdab5c3SScott Wood #define CONFIG_CMD_NAND 1 275acdab5c3SScott Wood #define CONFIG_NAND_FSL_ELBC 1 2766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 2777d6a0982SJoe Hershberger #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 27896b8a054SScott Wood 279e4c09508SScott Wood 2806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 2817d6a0982SJoe Hershberger | BR_DECC_CHK_GEN /* Use HW ECC */ \ 282261c07bcSJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 28396b8a054SScott Wood | BR_MS_FCM /* MSEL = FCM */ \ 28496b8a054SScott Wood | BR_V) /* valid */ 2857d6a0982SJoe Hershberger #define CONFIG_SYS_NAND_OR_PRELIM \ 2867d6a0982SJoe Hershberger (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 28796b8a054SScott Wood | OR_FCM_CSCT \ 28896b8a054SScott Wood | OR_FCM_CST \ 28996b8a054SScott Wood | OR_FCM_CHT \ 29096b8a054SScott Wood | OR_FCM_SCY_1 \ 29196b8a054SScott Wood | OR_FCM_TRLX \ 29296b8a054SScott Wood | OR_FCM_EHTR) 29396b8a054SScott Wood /* 0xFFFF8396 */ 294e4c09508SScott Wood 295e4c09508SScott Wood #ifdef CONFIG_NAND_U_BOOT 2966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 2986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 300e4c09508SScott Wood #else 3016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 3026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 3036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 3046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 305e4c09508SScott Wood #endif 306e4c09508SScott Wood 3076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 3087d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 30996b8a054SScott Wood 3106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 3116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 312e4c09508SScott Wood 3137d6a0982SJoe Hershberger /* local bus write LED / read status buffer (BCSR) mapping */ 3147d6a0982SJoe Hershberger #define CONFIG_SYS_BCSR_ADDR 0xFA000000 3157d6a0982SJoe Hershberger #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 3167d6a0982SJoe Hershberger /* map at 0xFA000000 on LCS3 */ 3177d6a0982SJoe Hershberger #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 3187d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 3197d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 3207d6a0982SJoe Hershberger | BR_V) /* valid */ 3217d6a0982SJoe Hershberger /* 0xFA000801 */ 3227d6a0982SJoe Hershberger #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 3237d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 3247d6a0982SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 3257d6a0982SJoe Hershberger | OR_GPCM_XACS \ 3267d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 3277d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 3287d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 3297d6a0982SJoe Hershberger | OR_GPCM_EAD) 3307d6a0982SJoe Hershberger /* 0xFFFF8FF7 */ 3317d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 3327d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 33396b8a054SScott Wood 33489c7784eSTimur Tabi /* Vitesse 7385 */ 33589c7784eSTimur Tabi 33689c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 33789c7784eSTimur Tabi 3387d6a0982SJoe Hershberger /* VSC7385 Base address on LCS2 */ 3397d6a0982SJoe Hershberger #define CONFIG_SYS_VSC7385_BASE 0xF0000000 3407d6a0982SJoe Hershberger #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 3417d6a0982SJoe Hershberger 3427d6a0982SJoe Hershberger #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 3437d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 3447d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 3457d6a0982SJoe Hershberger | BR_V) /* valid */ 3467d6a0982SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 3477d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 3487d6a0982SJoe Hershberger | OR_GPCM_XACS \ 3497d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 3507d6a0982SJoe Hershberger | OR_GPCM_SETA \ 3517d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 3527d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 3537d6a0982SJoe Hershberger | OR_GPCM_EAD) 3547d6a0982SJoe Hershberger /* 0xFFFE09FF */ 3557d6a0982SJoe Hershberger 356261c07bcSJoe Hershberger /* Access window base at VSC7385 base */ 357261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 3587d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 35989c7784eSTimur Tabi 36089c7784eSTimur Tabi #endif 36189c7784eSTimur Tabi 36296b8a054SScott Wood /* pass open firmware flat tree */ 36335cc4e48SKim Phillips #define CONFIG_OF_LIBFDT 1 36496b8a054SScott Wood #define CONFIG_OF_BOARD_SETUP 1 3655b8bc606SKim Phillips #define CONFIG_OF_STDOUT_VIA_ALIAS 1 36696b8a054SScott Wood 3670eaf8f9eSJoe Hershberger #define CONFIG_MPC83XX_GPIO 1 3680eaf8f9eSJoe Hershberger #define CONFIG_CMD_GPIO 1 3690eaf8f9eSJoe Hershberger 37096b8a054SScott Wood /* 37196b8a054SScott Wood * Serial Port 37296b8a054SScott Wood */ 37396b8a054SScott Wood #define CONFIG_CONS_INDEX 1 3746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 37796b8a054SScott Wood 3786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 37996b8a054SScott Wood {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 38096b8a054SScott Wood 3816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 3826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 38396b8a054SScott Wood 38496b8a054SScott Wood /* Use the HUSH parser */ 3856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 3866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 38796b8a054SScott Wood 38896b8a054SScott Wood /* I2C */ 38996b8a054SScott Wood #define CONFIG_HARD_I2C /* I2C with hardware support*/ 39096b8a054SScott Wood #define CONFIG_FSL_I2C 39196b8a054SScott Wood #define CONFIG_I2C_MULTI_BUS 3926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 3936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 3946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ 3956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 3966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 39796b8a054SScott Wood 39896b8a054SScott Wood /* 39996b8a054SScott Wood * General PCI 40096b8a054SScott Wood * Addresses are mapped 1-1. 40196b8a054SScott Wood */ 4026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 4036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 4046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 4056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 4066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 4076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 4086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 4096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 4106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 41196b8a054SScott Wood 41296b8a054SScott Wood #define CONFIG_PCI_PNP /* do pci plug-and-play */ 4136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 41496b8a054SScott Wood 41596b8a054SScott Wood /* 41689c7784eSTimur Tabi * TSEC 41796b8a054SScott Wood */ 41896b8a054SScott Wood #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 41996b8a054SScott Wood 42089c7784eSTimur Tabi #define CONFIG_GMII /* MII PHY management */ 42189c7784eSTimur Tabi 42289c7784eSTimur Tabi #ifdef CONFIG_TSEC1 42389c7784eSTimur Tabi #define CONFIG_HAS_ETH0 42489c7784eSTimur Tabi #define CONFIG_TSEC1_NAME "TSEC0" 4256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 42689c7784eSTimur Tabi #define TSEC1_PHY_ADDR 0x1c 42789c7784eSTimur Tabi #define TSEC1_FLAGS TSEC_GIGABIT 42889c7784eSTimur Tabi #define TSEC1_PHYIDX 0 42996b8a054SScott Wood #endif 43096b8a054SScott Wood 43189c7784eSTimur Tabi #ifdef CONFIG_TSEC2 43289c7784eSTimur Tabi #define CONFIG_HAS_ETH1 433255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 4346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 43596b8a054SScott Wood #define TSEC2_PHY_ADDR 4 4363a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 43796b8a054SScott Wood #define TSEC2_PHYIDX 0 43889c7784eSTimur Tabi #endif 43989c7784eSTimur Tabi 44096b8a054SScott Wood 44196b8a054SScott Wood /* Options are: TSEC[0-1] */ 44296b8a054SScott Wood #define CONFIG_ETHPRIME "TSEC1" 44396b8a054SScott Wood 44496b8a054SScott Wood /* 44596b8a054SScott Wood * Configure on-board RTC 44696b8a054SScott Wood */ 44796b8a054SScott Wood #define CONFIG_RTC_DS1337 4486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 44996b8a054SScott Wood 45096b8a054SScott Wood /* 45196b8a054SScott Wood * Environment 45296b8a054SScott Wood */ 453e4c09508SScott Wood #if defined(CONFIG_NAND_U_BOOT) 45451bfee19SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_NAND 1 4550e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET (512 * 1024) 4566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 4570e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 4580e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 4590e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 460261c07bcSJoe Hershberger #define CONFIG_ENV_OFFSET_REDUND \ 461261c07bcSJoe Hershberger (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 4626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif !defined(CONFIG_SYS_RAMBOOT) 4635a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 464261c07bcSJoe Hershberger #define CONFIG_ENV_ADDR \ 465261c07bcSJoe Hershberger (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4660e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 4670e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 46896b8a054SScott Wood 46996b8a054SScott Wood /* Address and size of Redundant Environment Sector */ 47096b8a054SScott Wood #else 47193f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 4726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4730e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 47496b8a054SScott Wood #endif 47596b8a054SScott Wood 47696b8a054SScott Wood #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 4776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 47896b8a054SScott Wood 4798ea5499aSJon Loeliger /* 480079a136cSJon Loeliger * BOOTP options 481079a136cSJon Loeliger */ 482079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 483079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTPATH 484079a136cSJon Loeliger #define CONFIG_BOOTP_GATEWAY 485079a136cSJon Loeliger #define CONFIG_BOOTP_HOSTNAME 486079a136cSJon Loeliger 487079a136cSJon Loeliger 488079a136cSJon Loeliger /* 4898ea5499aSJon Loeliger * Command line configuration. 4908ea5499aSJon Loeliger */ 4918ea5499aSJon Loeliger #include <config_cmd_default.h> 4928ea5499aSJon Loeliger 4938ea5499aSJon Loeliger #define CONFIG_CMD_PING 4948ea5499aSJon Loeliger #define CONFIG_CMD_DHCP 4958ea5499aSJon Loeliger #define CONFIG_CMD_I2C 4968ea5499aSJon Loeliger #define CONFIG_CMD_MII 4978ea5499aSJon Loeliger #define CONFIG_CMD_DATE 4988ea5499aSJon Loeliger #define CONFIG_CMD_PCI 4998ea5499aSJon Loeliger 5006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) 501bdab39d3SMike Frysinger #undef CONFIG_CMD_SAVEENV 5028ea5499aSJon Loeliger #undef CONFIG_CMD_LOADS 5038ea5499aSJon Loeliger #endif 50496b8a054SScott Wood 50596b8a054SScott Wood #define CONFIG_CMDLINE_EDITING 1 506a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 50796b8a054SScott Wood 50896b8a054SScott Wood /* 50996b8a054SScott Wood * Miscellaneous configurable options 51096b8a054SScott Wood */ 5116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 5126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 5136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 5146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 51596b8a054SScott Wood 516261c07bcSJoe Hershberger /* Print Buffer Size */ 517261c07bcSJoe Hershberger #define CONFIG_SYS_PBSIZE \ 518261c07bcSJoe Hershberger (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 5196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 520261c07bcSJoe Hershberger /* Boot Argument Buffer Size */ 521261c07bcSJoe Hershberger #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 5226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 52396b8a054SScott Wood 52496b8a054SScott Wood /* 52596b8a054SScott Wood * For booting Linux, the board info and command line data 5269f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 52796b8a054SScott Wood * the maximum mapped by the Linux kernel during initialization. 52896b8a054SScott Wood */ 529261c07bcSJoe Hershberger /* Initial Memory map for Linux*/ 530261c07bcSJoe Hershberger #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 53196b8a054SScott Wood 5326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 53396b8a054SScott Wood 5346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 53596b8a054SScott Wood 53696b8a054SScott Wood /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 53796b8a054SScott Wood /* 0x62040000 */ 5386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 53996b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 54096b8a054SScott Wood HRCWL_DDRCM |\ 54196b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 54296b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 54396b8a054SScott Wood HRCWL_CSB_TO_CLKIN_2X1 |\ 54496b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 54596b8a054SScott Wood 5466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 547e4c09508SScott Wood 5486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 54996b8a054SScott Wood 55096b8a054SScott Wood /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 55196b8a054SScott Wood /* 0x65040000 */ 5526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 55396b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 55496b8a054SScott Wood HRCWL_DDRCM |\ 55596b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 55696b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 55796b8a054SScott Wood HRCWL_CSB_TO_CLKIN_5X1 |\ 55896b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 55996b8a054SScott Wood 5606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 561e4c09508SScott Wood 56296b8a054SScott Wood #endif 56396b8a054SScott Wood 5646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH_BASE (\ 56596b8a054SScott Wood HRCWH_PCI_HOST |\ 56696b8a054SScott Wood HRCWH_PCI1_ARBITER_ENABLE |\ 56796b8a054SScott Wood HRCWH_CORE_ENABLE |\ 56896b8a054SScott Wood HRCWH_BOOTSEQ_DISABLE |\ 56996b8a054SScott Wood HRCWH_SW_WATCHDOG_DISABLE |\ 57096b8a054SScott Wood HRCWH_TSEC1M_IN_RGMII |\ 57196b8a054SScott Wood HRCWH_TSEC2M_IN_RGMII |\ 572e4c09508SScott Wood HRCWH_BIG_ENDIAN) 573e4c09508SScott Wood 574e4c09508SScott Wood #ifdef CONFIG_NAND_SPL 5756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 576e4c09508SScott Wood HRCWH_FROM_0XFFF00100 |\ 577e4c09508SScott Wood HRCWH_ROM_LOC_NAND_SP_8BIT |\ 578e4c09508SScott Wood HRCWH_RL_EXT_NAND) 579e4c09508SScott Wood #else 5806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 581e4c09508SScott Wood HRCWH_FROM_0X00000100 |\ 582e4c09508SScott Wood HRCWH_ROM_LOC_LOCAL_16BIT |\ 583e4c09508SScott Wood HRCWH_RL_EXT_LEGACY) 584e4c09508SScott Wood #endif 58596b8a054SScott Wood 58696b8a054SScott Wood /* System IO Config */ 5876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 5880eaf8f9eSJoe Hershberger /* Enable Internal USB Phy and GPIO on LCD Connector */ 5890eaf8f9eSJoe Hershberger #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 59096b8a054SScott Wood 5916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_INIT 0x000000000 5926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 5931a2e203bSKim Phillips HID0_ENABLE_INSTRUCTION_CACHE | \ 59496b8a054SScott Wood HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 59596b8a054SScott Wood 5966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 59796b8a054SScott Wood 59831d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 59931d82672SBecky Bruce 60096b8a054SScott Wood /* DDR @ 0x00000000 */ 60172cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 602261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 603261c07bcSJoe Hershberger | BATU_BL_256M \ 604261c07bcSJoe Hershberger | BATU_VS \ 605261c07bcSJoe Hershberger | BATU_VP) 60696b8a054SScott Wood 60796b8a054SScott Wood /* PCI @ 0x80000000 */ 60872cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 609261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 610261c07bcSJoe Hershberger | BATU_BL_256M \ 611261c07bcSJoe Hershberger | BATU_VS \ 612261c07bcSJoe Hershberger | BATU_VP) 613261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 61472cd4087SJoe Hershberger | BATL_PP_RW \ 615261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 616261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 617261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 618261c07bcSJoe Hershberger | BATU_BL_256M \ 619261c07bcSJoe Hershberger | BATU_VS \ 620261c07bcSJoe Hershberger | BATU_VP) 62196b8a054SScott Wood 62296b8a054SScott Wood /* PCI2 not supported on 8313 */ 6236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L (0) 6246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U (0) 6256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L (0) 6266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U (0) 62796b8a054SScott Wood 62896b8a054SScott Wood /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 629261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 63072cd4087SJoe Hershberger | BATL_PP_RW \ 631261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 632261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 633261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 634261c07bcSJoe Hershberger | BATU_BL_256M \ 635261c07bcSJoe Hershberger | BATU_VS \ 636261c07bcSJoe Hershberger | BATU_VP) 63796b8a054SScott Wood 63896b8a054SScott Wood /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 63972cd4087SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 6406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 64196b8a054SScott Wood 6426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L (0) 6436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U (0) 64496b8a054SScott Wood 6456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 6466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 6476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 6486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 6496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 6506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 6516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 6526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 6536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 6546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 6556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 6566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 6576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 6586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 6596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 6606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 66196b8a054SScott Wood 66296b8a054SScott Wood /* 66396b8a054SScott Wood * Environment Configuration 66496b8a054SScott Wood */ 66596b8a054SScott Wood #define CONFIG_ENV_OVERWRITE 66696b8a054SScott Wood 667261c07bcSJoe Hershberger #define CONFIG_NETDEV "eth1" 66896b8a054SScott Wood 66996b8a054SScott Wood #define CONFIG_HOSTNAME mpc8313erdb 6708b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfs/root/path" 671b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 672261c07bcSJoe Hershberger /* U-Boot image on TFTP server */ 673261c07bcSJoe Hershberger #define CONFIG_UBOOTPATH "u-boot.bin" 674261c07bcSJoe Hershberger #define CONFIG_FDTFILE "mpc8313erdb.dtb" 67596b8a054SScott Wood 676261c07bcSJoe Hershberger /* default location for tftp and bootm */ 677261c07bcSJoe Hershberger #define CONFIG_LOADADDR 800000 6787fd0bea2SKim Phillips #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 67996b8a054SScott Wood #define CONFIG_BAUDRATE 115200 68096b8a054SScott Wood 68196b8a054SScott Wood #define XMK_STR(x) #x 68296b8a054SScott Wood #define MK_STR(x) XMK_STR(x) 68396b8a054SScott Wood 68496b8a054SScott Wood #define CONFIG_EXTRA_ENV_SETTINGS \ 685261c07bcSJoe Hershberger "netdev=" CONFIG_NETDEV "\0" \ 68696b8a054SScott Wood "ethprime=TSEC1\0" \ 687261c07bcSJoe Hershberger "uboot=" CONFIG_UBOOTPATH "\0" \ 68896b8a054SScott Wood "tftpflash=tftpboot $loadaddr $uboot; " \ 68914d0a02aSWolfgang Denk "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 69014d0a02aSWolfgang Denk "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 69114d0a02aSWolfgang Denk "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\ 69214d0a02aSWolfgang Denk "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 69314d0a02aSWolfgang Denk "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\ 69479f516bcSKim Phillips "fdtaddr=780000\0" \ 695261c07bcSJoe Hershberger "fdtfile=" CONFIG_FDTFILE "\0" \ 69696b8a054SScott Wood "console=ttyS0\0" \ 69796b8a054SScott Wood "setbootargs=setenv bootargs " \ 69896b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 69996b8a054SScott Wood "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 700261c07bcSJoe Hershberger "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 701261c07bcSJoe Hershberger "$netdev:off " \ 70296b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 70396b8a054SScott Wood 70496b8a054SScott Wood #define CONFIG_NFSBOOTCOMMAND \ 70596b8a054SScott Wood "setenv rootdev /dev/nfs;" \ 70696b8a054SScott Wood "run setbootargs;" \ 70796b8a054SScott Wood "run setipargs;" \ 70896b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 70996b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 71096b8a054SScott Wood "bootm $loadaddr - $fdtaddr" 71196b8a054SScott Wood 71296b8a054SScott Wood #define CONFIG_RAMBOOTCOMMAND \ 71396b8a054SScott Wood "setenv rootdev /dev/ram;" \ 71496b8a054SScott Wood "run setbootargs;" \ 71596b8a054SScott Wood "tftp $ramdiskaddr $ramdiskfile;" \ 71696b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 71796b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 71896b8a054SScott Wood "bootm $loadaddr $ramdiskaddr $fdtaddr" 71996b8a054SScott Wood 72096b8a054SScott Wood #undef MK_STR 72196b8a054SScott Wood #undef XMK_STR 72296b8a054SScott Wood 72396b8a054SScott Wood #endif /* __CONFIG_H */ 724