196b8a054SScott Wood /* 2e8d3ca8bSScott Wood * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 396b8a054SScott Wood * 496b8a054SScott Wood * See file CREDITS for list of people who contributed to this 596b8a054SScott Wood * project. 696b8a054SScott Wood * 796b8a054SScott Wood * This program is free software; you can redistribute it and/or 896b8a054SScott Wood * modify it under the terms of the GNU General Public License as 996b8a054SScott Wood * published by the Free Software Foundation; either version 2 of 1096b8a054SScott Wood * the License, or (at your option) any later version. 1196b8a054SScott Wood * 1296b8a054SScott Wood * This program is distributed in the hope that it will be useful, 1396b8a054SScott Wood * but WITHOUT ANY WARRANTY; without even the implied warranty of 1496b8a054SScott Wood * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1596b8a054SScott Wood * GNU General Public License for more details. 1696b8a054SScott Wood * 1796b8a054SScott Wood * You should have received a copy of the GNU General Public License 1896b8a054SScott Wood * along with this program; if not, write to the Free Software 1996b8a054SScott Wood * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 2096b8a054SScott Wood * MA 02111-1307 USA 2196b8a054SScott Wood */ 2296b8a054SScott Wood /* 2396b8a054SScott Wood * mpc8313epb board configuration file 2496b8a054SScott Wood */ 2596b8a054SScott Wood 2696b8a054SScott Wood #ifndef __CONFIG_H 2796b8a054SScott Wood #define __CONFIG_H 2896b8a054SScott Wood 2996b8a054SScott Wood /* 3096b8a054SScott Wood * High Level Configuration Options 3196b8a054SScott Wood */ 3296b8a054SScott Wood #define CONFIG_E300 1 330f898604SPeter Tyser #define CONFIG_MPC83xx 1 342c7920afSPeter Tyser #define CONFIG_MPC831x 1 3596b8a054SScott Wood #define CONFIG_MPC8313 1 3696b8a054SScott Wood #define CONFIG_MPC8313ERDB 1 3796b8a054SScott Wood 38f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 39f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 40f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 41f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 42f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 43f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 44f1c574d4SScott Wood 45f1c574d4SScott Wood #ifdef CONFIG_NAND_U_BOOT 46f1c574d4SScott Wood #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 47f1c574d4SScott Wood #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 48f1c574d4SScott Wood #ifdef CONFIG_NAND_SPL 49f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 50f1c574d4SScott Wood #endif /* CONFIG_NAND_SPL */ 51f1c574d4SScott Wood #endif /* CONFIG_NAND_U_BOOT */ 52f1c574d4SScott Wood 532ae18241SWolfgang Denk #ifndef CONFIG_SYS_TEXT_BASE 542ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFE000000 552ae18241SWolfgang Denk #endif 562ae18241SWolfgang Denk 57f1c574d4SScott Wood #ifndef CONFIG_SYS_MONITOR_BASE 58f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 59f1c574d4SScott Wood #endif 60f1c574d4SScott Wood 6196b8a054SScott Wood #define CONFIG_PCI 620914f483SBecky Bruce #define CONFIG_FSL_ELBC 1 6396b8a054SScott Wood 6489c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 6589c7784eSTimur Tabi 6689c7784eSTimur Tabi /* 6789c7784eSTimur Tabi * On-board devices 684ce1e23bSYork Sun * 694ce1e23bSYork Sun * TSEC1 is VSC switch 704ce1e23bSYork Sun * TSEC2 is SoC TSEC 7189c7784eSTimur Tabi */ 7289c7784eSTimur Tabi #define CONFIG_VSC7385_ENET 734ce1e23bSYork Sun #define CONFIG_TSEC2 7489c7784eSTimur Tabi 756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 765c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 785c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 7996b8a054SScott Wood #else 8096b8a054SScott Wood #error Unknown oscillator frequency. 8196b8a054SScott Wood #endif 8296b8a054SScott Wood 8396b8a054SScott Wood #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 8496b8a054SScott Wood 8596b8a054SScott Wood #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 8696b8a054SScott Wood 876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 8896b8a054SScott Wood 89e4c09508SScott Wood #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 91e4c09508SScott Wood #endif 92e4c09508SScott Wood 936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00001000 946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x07f00000 9596b8a054SScott Wood 9696b8a054SScott Wood /* Early revs of this board will lock up hard when attempting 9796b8a054SScott Wood * to access the PMC registers, unless a JTAG debugger is 9896b8a054SScott Wood * connected, or some resistor modifications are made. 9996b8a054SScott Wood */ 1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 10196b8a054SScott Wood 1026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 1036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 10496b8a054SScott Wood 10596b8a054SScott Wood /* 10689c7784eSTimur Tabi * Device configurations 10789c7784eSTimur Tabi */ 10889c7784eSTimur Tabi 10989c7784eSTimur Tabi /* Vitesse 7385 */ 11089c7784eSTimur Tabi 11189c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 11289c7784eSTimur Tabi 1134ce1e23bSYork Sun #define CONFIG_TSEC1 11489c7784eSTimur Tabi 11589c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 11689c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFE7FE000 11789c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 11889c7784eSTimur Tabi 11989c7784eSTimur Tabi #endif 12089c7784eSTimur Tabi 12189c7784eSTimur Tabi /* 12296b8a054SScott Wood * DDR Setup 12396b8a054SScott Wood */ 1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 12796b8a054SScott Wood 12896b8a054SScott Wood /* 12996b8a054SScott Wood * Manually set up DDR parameters, as this board does not 13096b8a054SScott Wood * seem to have the SPD connected to I2C. 13196b8a054SScott Wood */ 1326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 1336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \ 134e1d8ed2cSPoonam Aggrwal | 0x00010000 /* TODO */ \ 13596b8a054SScott Wood | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) 136e1d8ed2cSPoonam Aggrwal /* 0x80010102 */ 13796b8a054SScott Wood 1386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_3 0x00000000 1396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 14096b8a054SScott Wood | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 14196b8a054SScott Wood | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 14296b8a054SScott Wood | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 14396b8a054SScott Wood | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 14496b8a054SScott Wood | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 14596b8a054SScott Wood | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 14696b8a054SScott Wood | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 14796b8a054SScott Wood /* 0x00220802 */ 1486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ 149e1d8ed2cSPoonam Aggrwal | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 15096b8a054SScott Wood | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ 15196b8a054SScott Wood | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 152e1d8ed2cSPoonam Aggrwal | (10 << TIMING_CFG1_REFREC_SHIFT ) \ 15396b8a054SScott Wood | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ 15496b8a054SScott Wood | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 15596b8a054SScott Wood | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 156e1d8ed2cSPoonam Aggrwal /* 0x3835a322 */ 1576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 158e1d8ed2cSPoonam Aggrwal | ( 5 << TIMING_CFG2_CPO_SHIFT ) \ 15996b8a054SScott Wood | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 16096b8a054SScott Wood | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 16196b8a054SScott Wood | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 16296b8a054SScott Wood | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 163e1d8ed2cSPoonam Aggrwal | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 164e1d8ed2cSPoonam Aggrwal /* 0x129048c6 */ /* P9-45,may need tuning */ 1656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 166e1d8ed2cSPoonam Aggrwal | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 167e1d8ed2cSPoonam Aggrwal /* 0x05100500 */ 16896b8a054SScott Wood #if defined(CONFIG_DDR_2T_TIMING) 1696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ 170bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 17196b8a054SScott Wood | SDRAM_CFG_2T_EN \ 17296b8a054SScott Wood | SDRAM_CFG_DBW_32 ) 17396b8a054SScott Wood #else 1746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ 175bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 17696b8a054SScott Wood | SDRAM_CFG_32_BE ) 17796b8a054SScott Wood /* 0x43080000 */ 17896b8a054SScott Wood #endif 1796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG2 0x00401000 18096b8a054SScott Wood /* set burst length to 8 for 32-bit data path */ 1816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ 182e1d8ed2cSPoonam Aggrwal | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) ) 183e1d8ed2cSPoonam Aggrwal /* 0x44480632 */ 1846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x8000C000 18596b8a054SScott Wood 1866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 18796b8a054SScott Wood /*0x02000000*/ 1886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \ 18996b8a054SScott Wood | DDRCDR_PZ_NOMZ \ 19096b8a054SScott Wood | DDRCDR_NZ_NOMZ \ 19196b8a054SScott Wood | DDRCDR_M_ODR ) 19296b8a054SScott Wood 19396b8a054SScott Wood /* 19496b8a054SScott Wood * FLASH on the Local Bus 19596b8a054SScott Wood */ 1966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 19700b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 1986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 1996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 2006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 20396b8a054SScott Wood 2046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ 20596b8a054SScott Wood (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 20696b8a054SScott Wood BR_V) /* valid */ 2076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NOR_OR_PRELIM ( 0xFF800000 /* 8 MByte */ \ 20896b8a054SScott Wood | OR_GPCM_XACS \ 20996b8a054SScott Wood | OR_GPCM_SCY_9 \ 21096b8a054SScott Wood | OR_GPCM_EHTR \ 21196b8a054SScott Wood | OR_GPCM_EAD ) 21296b8a054SScott Wood /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 2136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ 2146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ 21596b8a054SScott Wood 2166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 2176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 21896b8a054SScott Wood 2196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 22196b8a054SScott Wood 2226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_SPL) 2236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 22496b8a054SScott Wood #endif 22596b8a054SScott Wood 2266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 2276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 228553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 22996b8a054SScott Wood 23025ddd1fbSWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 23296b8a054SScott Wood 2336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 2344a9932a4SKim Phillips #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 2356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 23696b8a054SScott Wood 23796b8a054SScott Wood /* 23896b8a054SScott Wood * Local Bus LCRR and LBCR regs 23996b8a054SScott Wood */ 240c7190f02SKim Phillips #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 241c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 2426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \ 24396b8a054SScott Wood | (0xFF << LBCR_BMT_SHIFT) \ 24496b8a054SScott Wood | 0xF ) /* 0x0004ff0f */ 24596b8a054SScott Wood 2466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ 24796b8a054SScott Wood 2487817cb20SMarcel Ziswiler /* drivers/mtd/nand/nand.c */ 249e4c09508SScott Wood #ifdef CONFIG_NAND_SPL 2506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xFFF00000 251e4c09508SScott Wood #else 2526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xE2800000 253e4c09508SScott Wood #endif 254e4c09508SScott Wood 255e8d3ca8bSScott Wood #define CONFIG_MTD_DEVICE 256e8d3ca8bSScott Wood #define CONFIG_MTD_PARTITION 257e8d3ca8bSScott Wood #define CONFIG_CMD_MTDPARTS 258e8d3ca8bSScott Wood #define MTDIDS_DEFAULT "nand0=e2800000.flash" 259e8d3ca8bSScott Wood #define MTDPARTS_DEFAULT \ 260e8d3ca8bSScott Wood "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" 261e8d3ca8bSScott Wood 2626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_NAND_DEVICE 1 26396b8a054SScott Wood #define CONFIG_MTD_NAND_VERIFY_WRITE 264acdab5c3SScott Wood #define CONFIG_CMD_NAND 1 265acdab5c3SScott Wood #define CONFIG_NAND_FSL_ELBC 1 2666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 26796b8a054SScott Wood 268e4c09508SScott Wood 2696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ 27096b8a054SScott Wood | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 27196b8a054SScott Wood | BR_PS_8 /* Port Size = 8 bit */ \ 27296b8a054SScott Wood | BR_MS_FCM /* MSEL = FCM */ \ 27396b8a054SScott Wood | BR_V ) /* valid */ 2746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \ 27596b8a054SScott Wood | OR_FCM_CSCT \ 27696b8a054SScott Wood | OR_FCM_CST \ 27796b8a054SScott Wood | OR_FCM_CHT \ 27896b8a054SScott Wood | OR_FCM_SCY_1 \ 27996b8a054SScott Wood | OR_FCM_TRLX \ 28096b8a054SScott Wood | OR_FCM_EHTR ) 28196b8a054SScott Wood /* 0xFFFF8396 */ 282e4c09508SScott Wood 283e4c09508SScott Wood #ifdef CONFIG_NAND_U_BOOT 2846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 2866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 288e4c09508SScott Wood #else 2896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 2916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 293e4c09508SScott Wood #endif 294e4c09508SScott Wood 2956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 2966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 29796b8a054SScott Wood 2986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 2996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 300e4c09508SScott Wood 30196b8a054SScott Wood /* local bus read write buffer mapping */ 3026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ 3036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ 3046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xFA000000 3056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 30696b8a054SScott Wood 30789c7784eSTimur Tabi /* Vitesse 7385 */ 30889c7784eSTimur Tabi 3096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_VSC7385_BASE 0xF0000000 31089c7784eSTimur Tabi 31189c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 31289c7784eSTimur Tabi 3136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ 3146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ 3156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE/* Access window base at VSC7385 base */ 3166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ 31789c7784eSTimur Tabi 31889c7784eSTimur Tabi #endif 31989c7784eSTimur Tabi 32096b8a054SScott Wood /* pass open firmware flat tree */ 32135cc4e48SKim Phillips #define CONFIG_OF_LIBFDT 1 32296b8a054SScott Wood #define CONFIG_OF_BOARD_SETUP 1 3235b8bc606SKim Phillips #define CONFIG_OF_STDOUT_VIA_ALIAS 1 32496b8a054SScott Wood 32596b8a054SScott Wood /* 32696b8a054SScott Wood * Serial Port 32796b8a054SScott Wood */ 32896b8a054SScott Wood #define CONFIG_CONS_INDEX 1 3296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 33296b8a054SScott Wood 3336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 33496b8a054SScott Wood {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 33596b8a054SScott Wood 3366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 3376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 33896b8a054SScott Wood 33996b8a054SScott Wood /* Use the HUSH parser */ 3406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 3416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 34296b8a054SScott Wood 34396b8a054SScott Wood /* I2C */ 34496b8a054SScott Wood #define CONFIG_HARD_I2C /* I2C with hardware support*/ 34596b8a054SScott Wood #define CONFIG_FSL_I2C 34696b8a054SScott Wood #define CONFIG_I2C_MULTI_BUS 3476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 3486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 3496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 3506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 3516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 35296b8a054SScott Wood 35396b8a054SScott Wood /* 35496b8a054SScott Wood * General PCI 35596b8a054SScott Wood * Addresses are mapped 1-1. 35696b8a054SScott Wood */ 3576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 3596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 3606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 3616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 3626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 3646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 3656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 36696b8a054SScott Wood 36796b8a054SScott Wood #define CONFIG_PCI_PNP /* do pci plug-and-play */ 3686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 36996b8a054SScott Wood 37096b8a054SScott Wood /* 37189c7784eSTimur Tabi * TSEC 37296b8a054SScott Wood */ 37396b8a054SScott Wood #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 37496b8a054SScott Wood 37589c7784eSTimur Tabi #define CONFIG_GMII /* MII PHY management */ 37689c7784eSTimur Tabi 37789c7784eSTimur Tabi #ifdef CONFIG_TSEC1 37889c7784eSTimur Tabi #define CONFIG_HAS_ETH0 37989c7784eSTimur Tabi #define CONFIG_TSEC1_NAME "TSEC0" 3806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 38189c7784eSTimur Tabi #define TSEC1_PHY_ADDR 0x1c 38289c7784eSTimur Tabi #define TSEC1_FLAGS TSEC_GIGABIT 38389c7784eSTimur Tabi #define TSEC1_PHYIDX 0 38496b8a054SScott Wood #endif 38596b8a054SScott Wood 38689c7784eSTimur Tabi #ifdef CONFIG_TSEC2 38789c7784eSTimur Tabi #define CONFIG_HAS_ETH1 388255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 3896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 39096b8a054SScott Wood #define TSEC2_PHY_ADDR 4 3913a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 39296b8a054SScott Wood #define TSEC2_PHYIDX 0 39389c7784eSTimur Tabi #endif 39489c7784eSTimur Tabi 39596b8a054SScott Wood 39696b8a054SScott Wood /* Options are: TSEC[0-1] */ 39796b8a054SScott Wood #define CONFIG_ETHPRIME "TSEC1" 39896b8a054SScott Wood 39996b8a054SScott Wood /* 40096b8a054SScott Wood * Configure on-board RTC 40196b8a054SScott Wood */ 40296b8a054SScott Wood #define CONFIG_RTC_DS1337 4036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 40496b8a054SScott Wood 40596b8a054SScott Wood /* 40696b8a054SScott Wood * Environment 40796b8a054SScott Wood */ 408e4c09508SScott Wood #if defined(CONFIG_NAND_U_BOOT) 40951bfee19SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_NAND 1 4100e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET (512 * 1024) 4116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 4120e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 4130e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 4140e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 4150e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 4166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif !defined(CONFIG_SYS_RAMBOOT) 4175a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 4186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4190e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 4200e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 42196b8a054SScott Wood 42296b8a054SScott Wood /* Address and size of Redundant Environment Sector */ 42396b8a054SScott Wood #else 42493f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 4256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4260e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 42796b8a054SScott Wood #endif 42896b8a054SScott Wood 42996b8a054SScott Wood #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 4306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 43196b8a054SScott Wood 4328ea5499aSJon Loeliger /* 433079a136cSJon Loeliger * BOOTP options 434079a136cSJon Loeliger */ 435079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 436079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTPATH 437079a136cSJon Loeliger #define CONFIG_BOOTP_GATEWAY 438079a136cSJon Loeliger #define CONFIG_BOOTP_HOSTNAME 439079a136cSJon Loeliger 440079a136cSJon Loeliger 441079a136cSJon Loeliger /* 4428ea5499aSJon Loeliger * Command line configuration. 4438ea5499aSJon Loeliger */ 4448ea5499aSJon Loeliger #include <config_cmd_default.h> 4458ea5499aSJon Loeliger 4468ea5499aSJon Loeliger #define CONFIG_CMD_PING 4478ea5499aSJon Loeliger #define CONFIG_CMD_DHCP 4488ea5499aSJon Loeliger #define CONFIG_CMD_I2C 4498ea5499aSJon Loeliger #define CONFIG_CMD_MII 4508ea5499aSJon Loeliger #define CONFIG_CMD_DATE 4518ea5499aSJon Loeliger #define CONFIG_CMD_PCI 4528ea5499aSJon Loeliger 4536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) 454bdab39d3SMike Frysinger #undef CONFIG_CMD_SAVEENV 4558ea5499aSJon Loeliger #undef CONFIG_CMD_LOADS 4568ea5499aSJon Loeliger #endif 45796b8a054SScott Wood 45896b8a054SScott Wood #define CONFIG_CMDLINE_EDITING 1 459a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 46096b8a054SScott Wood 46196b8a054SScott Wood /* 46296b8a054SScott Wood * Miscellaneous configurable options 46396b8a054SScott Wood */ 4646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 4656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 4666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 4676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 46896b8a054SScott Wood 4696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 4706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 4716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 4726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 47396b8a054SScott Wood 47496b8a054SScott Wood /* 47596b8a054SScott Wood * For booting Linux, the board info and command line data 4769f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 47796b8a054SScott Wood * the maximum mapped by the Linux kernel during initialization. 47896b8a054SScott Wood */ 4799f530d59SIra W. Snyder #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 48096b8a054SScott Wood 4816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 48296b8a054SScott Wood 4836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 48496b8a054SScott Wood 48596b8a054SScott Wood /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 48696b8a054SScott Wood /* 0x62040000 */ 4876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 48896b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 48996b8a054SScott Wood HRCWL_DDRCM |\ 49096b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 49196b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 49296b8a054SScott Wood HRCWL_CSB_TO_CLKIN_2X1 |\ 49396b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 49496b8a054SScott Wood 4956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 496e4c09508SScott Wood 4976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 49896b8a054SScott Wood 49996b8a054SScott Wood /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 50096b8a054SScott Wood /* 0x65040000 */ 5016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 50296b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 50396b8a054SScott Wood HRCWL_DDRCM |\ 50496b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 50596b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 50696b8a054SScott Wood HRCWL_CSB_TO_CLKIN_5X1 |\ 50796b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 50896b8a054SScott Wood 5096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 510e4c09508SScott Wood 51196b8a054SScott Wood #endif 51296b8a054SScott Wood 5136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH_BASE (\ 51496b8a054SScott Wood HRCWH_PCI_HOST |\ 51596b8a054SScott Wood HRCWH_PCI1_ARBITER_ENABLE |\ 51696b8a054SScott Wood HRCWH_CORE_ENABLE |\ 51796b8a054SScott Wood HRCWH_BOOTSEQ_DISABLE |\ 51896b8a054SScott Wood HRCWH_SW_WATCHDOG_DISABLE |\ 51996b8a054SScott Wood HRCWH_TSEC1M_IN_RGMII |\ 52096b8a054SScott Wood HRCWH_TSEC2M_IN_RGMII |\ 521e4c09508SScott Wood HRCWH_BIG_ENDIAN) 522e4c09508SScott Wood 523e4c09508SScott Wood #ifdef CONFIG_NAND_SPL 5246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 525e4c09508SScott Wood HRCWH_FROM_0XFFF00100 |\ 526e4c09508SScott Wood HRCWH_ROM_LOC_NAND_SP_8BIT |\ 527e4c09508SScott Wood HRCWH_RL_EXT_NAND) 528e4c09508SScott Wood #else 5296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 530e4c09508SScott Wood HRCWH_FROM_0X00000100 |\ 531e4c09508SScott Wood HRCWH_ROM_LOC_LOCAL_16BIT |\ 532e4c09508SScott Wood HRCWH_RL_EXT_LEGACY) 533e4c09508SScott Wood #endif 53496b8a054SScott Wood 53596b8a054SScott Wood /* System IO Config */ 5366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 537f986325dSRon Madrid #define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */ 53896b8a054SScott Wood 5396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_INIT 0x000000000 5406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 5411a2e203bSKim Phillips HID0_ENABLE_INSTRUCTION_CACHE | \ 54296b8a054SScott Wood HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 54396b8a054SScott Wood 5446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 54596b8a054SScott Wood 54631d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 54731d82672SBecky Bruce 54896b8a054SScott Wood /* DDR @ 0x00000000 */ 5496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) 5506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 55196b8a054SScott Wood 55296b8a054SScott Wood /* PCI @ 0x80000000 */ 5536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) 5546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 5556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 5566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 55796b8a054SScott Wood 55896b8a054SScott Wood /* PCI2 not supported on 8313 */ 5596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L (0) 5606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U (0) 5616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L (0) 5626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U (0) 56396b8a054SScott Wood 56496b8a054SScott Wood /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 5656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 5666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 56796b8a054SScott Wood 56896b8a054SScott Wood /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 569c1230980SScott Wood #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) 5706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 57196b8a054SScott Wood 5726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L (0) 5736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U (0) 57496b8a054SScott Wood 5756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 5766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 5776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 5786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 5796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 5806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 5816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 5826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 5836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 5846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 5856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 5866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 5876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 5886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 5896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 5906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 59196b8a054SScott Wood 59296b8a054SScott Wood /* 59396b8a054SScott Wood * Environment Configuration 59496b8a054SScott Wood */ 59596b8a054SScott Wood #define CONFIG_ENV_OVERWRITE 59696b8a054SScott Wood 59796b8a054SScott Wood #define CONFIG_NETDEV eth1 59896b8a054SScott Wood 59996b8a054SScott Wood #define CONFIG_HOSTNAME mpc8313erdb 6008b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfs/root/path" 601*b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 60296b8a054SScott Wood #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 60396b8a054SScott Wood #define CONFIG_FDTFILE mpc8313erdb.dtb 60496b8a054SScott Wood 60579f516bcSKim Phillips #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 6067fd0bea2SKim Phillips #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 60796b8a054SScott Wood #define CONFIG_BAUDRATE 115200 60896b8a054SScott Wood 60996b8a054SScott Wood #define XMK_STR(x) #x 61096b8a054SScott Wood #define MK_STR(x) XMK_STR(x) 61196b8a054SScott Wood 61296b8a054SScott Wood #define CONFIG_EXTRA_ENV_SETTINGS \ 61396b8a054SScott Wood "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 61496b8a054SScott Wood "ethprime=TSEC1\0" \ 61596b8a054SScott Wood "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 61696b8a054SScott Wood "tftpflash=tftpboot $loadaddr $uboot; " \ 61714d0a02aSWolfgang Denk "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 61814d0a02aSWolfgang Denk "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 61914d0a02aSWolfgang Denk "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 62014d0a02aSWolfgang Denk "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 62114d0a02aSWolfgang Denk "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 62279f516bcSKim Phillips "fdtaddr=780000\0" \ 62396b8a054SScott Wood "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 62496b8a054SScott Wood "console=ttyS0\0" \ 62596b8a054SScott Wood "setbootargs=setenv bootargs " \ 62696b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 62796b8a054SScott Wood "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 62896b8a054SScott Wood "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 62996b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 63096b8a054SScott Wood 63196b8a054SScott Wood #define CONFIG_NFSBOOTCOMMAND \ 63296b8a054SScott Wood "setenv rootdev /dev/nfs;" \ 63396b8a054SScott Wood "run setbootargs;" \ 63496b8a054SScott Wood "run setipargs;" \ 63596b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 63696b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 63796b8a054SScott Wood "bootm $loadaddr - $fdtaddr" 63896b8a054SScott Wood 63996b8a054SScott Wood #define CONFIG_RAMBOOTCOMMAND \ 64096b8a054SScott Wood "setenv rootdev /dev/ram;" \ 64196b8a054SScott Wood "run setbootargs;" \ 64296b8a054SScott Wood "tftp $ramdiskaddr $ramdiskfile;" \ 64396b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 64496b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 64596b8a054SScott Wood "bootm $loadaddr $ramdiskaddr $fdtaddr" 64696b8a054SScott Wood 64796b8a054SScott Wood #undef MK_STR 64896b8a054SScott Wood #undef XMK_STR 64996b8a054SScott Wood 65096b8a054SScott Wood #endif /* __CONFIG_H */ 651