196b8a054SScott Wood /* 296b8a054SScott Wood * Copyright (C) Freescale Semiconductor, Inc. 2006. 396b8a054SScott Wood * 496b8a054SScott Wood * See file CREDITS for list of people who contributed to this 596b8a054SScott Wood * project. 696b8a054SScott Wood * 796b8a054SScott Wood * This program is free software; you can redistribute it and/or 896b8a054SScott Wood * modify it under the terms of the GNU General Public License as 996b8a054SScott Wood * published by the Free Software Foundation; either version 2 of 1096b8a054SScott Wood * the License, or (at your option) any later version. 1196b8a054SScott Wood * 1296b8a054SScott Wood * This program is distributed in the hope that it will be useful, 1396b8a054SScott Wood * but WITHOUT ANY WARRANTY; without even the implied warranty of 1496b8a054SScott Wood * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1596b8a054SScott Wood * GNU General Public License for more details. 1696b8a054SScott Wood * 1796b8a054SScott Wood * You should have received a copy of the GNU General Public License 1896b8a054SScott Wood * along with this program; if not, write to the Free Software 1996b8a054SScott Wood * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 2096b8a054SScott Wood * MA 02111-1307 USA 2196b8a054SScott Wood */ 2296b8a054SScott Wood /* 2396b8a054SScott Wood * mpc8313epb board configuration file 2496b8a054SScott Wood */ 2596b8a054SScott Wood 2696b8a054SScott Wood #ifndef __CONFIG_H 2796b8a054SScott Wood #define __CONFIG_H 2896b8a054SScott Wood 2996b8a054SScott Wood /* 3096b8a054SScott Wood * High Level Configuration Options 3196b8a054SScott Wood */ 3296b8a054SScott Wood #define CONFIG_E300 1 3396b8a054SScott Wood #define CONFIG_MPC83XX 1 3496b8a054SScott Wood #define CONFIG_MPC831X 1 3596b8a054SScott Wood #define CONFIG_MPC8313 1 3696b8a054SScott Wood #define CONFIG_MPC8313ERDB 1 3796b8a054SScott Wood 3896b8a054SScott Wood #define CONFIG_PCI 3996b8a054SScott Wood #define CONFIG_83XX_GENERIC_PCI 4096b8a054SScott Wood 4189c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 4289c7784eSTimur Tabi 4389c7784eSTimur Tabi /* 4489c7784eSTimur Tabi * On-board devices 454ce1e23bSYork Sun * 464ce1e23bSYork Sun * TSEC1 is VSC switch 474ce1e23bSYork Sun * TSEC2 is SoC TSEC 4889c7784eSTimur Tabi */ 4989c7784eSTimur Tabi #define CONFIG_VSC7385_ENET 504ce1e23bSYork Sun #define CONFIG_TSEC2 5189c7784eSTimur Tabi 5296b8a054SScott Wood #ifdef CFG_66MHZ 535c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 5496b8a054SScott Wood #elif defined(CFG_33MHZ) 555c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 5696b8a054SScott Wood #else 5796b8a054SScott Wood #error Unknown oscillator frequency. 5896b8a054SScott Wood #endif 5996b8a054SScott Wood 6096b8a054SScott Wood #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 6196b8a054SScott Wood 6296b8a054SScott Wood #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 6396b8a054SScott Wood 6496b8a054SScott Wood #define CFG_IMMR 0xE0000000 6596b8a054SScott Wood 6696b8a054SScott Wood #define CFG_MEMTEST_START 0x00001000 6796b8a054SScott Wood #define CFG_MEMTEST_END 0x07f00000 6896b8a054SScott Wood 6996b8a054SScott Wood /* Early revs of this board will lock up hard when attempting 7096b8a054SScott Wood * to access the PMC registers, unless a JTAG debugger is 7196b8a054SScott Wood * connected, or some resistor modifications are made. 7296b8a054SScott Wood */ 7396b8a054SScott Wood #define CFG_8313ERDB_BROKEN_PMC 1 7496b8a054SScott Wood 7596b8a054SScott Wood #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 7696b8a054SScott Wood #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 7796b8a054SScott Wood 7896b8a054SScott Wood /* 7989c7784eSTimur Tabi * Device configurations 8089c7784eSTimur Tabi */ 8189c7784eSTimur Tabi 8289c7784eSTimur Tabi /* Vitesse 7385 */ 8389c7784eSTimur Tabi 8489c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 8589c7784eSTimur Tabi 864ce1e23bSYork Sun #define CONFIG_TSEC1 8789c7784eSTimur Tabi 8889c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 8989c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFE7FE000 9089c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 9189c7784eSTimur Tabi 9289c7784eSTimur Tabi #endif 9389c7784eSTimur Tabi 9489c7784eSTimur Tabi /* 9596b8a054SScott Wood * DDR Setup 9696b8a054SScott Wood */ 9796b8a054SScott Wood #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 9896b8a054SScott Wood #define CFG_SDRAM_BASE CFG_DDR_BASE 9996b8a054SScott Wood #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 10096b8a054SScott Wood 10196b8a054SScott Wood /* 10296b8a054SScott Wood * Manually set up DDR parameters, as this board does not 10396b8a054SScott Wood * seem to have the SPD connected to I2C. 10496b8a054SScott Wood */ 10596b8a054SScott Wood #define CFG_DDR_SIZE 128 /* MB */ 106e1d8ed2cSPoonam Aggrwal #define CFG_DDR_CONFIG ( CSCONFIG_EN \ 107e1d8ed2cSPoonam Aggrwal | 0x00010000 /* TODO */ \ 10896b8a054SScott Wood | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) 109e1d8ed2cSPoonam Aggrwal /* 0x80010102 */ 11096b8a054SScott Wood 11196b8a054SScott Wood #define CFG_DDR_TIMING_3 0x00000000 11296b8a054SScott Wood #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 11396b8a054SScott Wood | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 11496b8a054SScott Wood | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 11596b8a054SScott Wood | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 11696b8a054SScott Wood | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 11796b8a054SScott Wood | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 11896b8a054SScott Wood | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 11996b8a054SScott Wood | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 12096b8a054SScott Wood /* 0x00220802 */ 12196b8a054SScott Wood #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ 122e1d8ed2cSPoonam Aggrwal | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 12396b8a054SScott Wood | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ 12496b8a054SScott Wood | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 125e1d8ed2cSPoonam Aggrwal | (10 << TIMING_CFG1_REFREC_SHIFT ) \ 12696b8a054SScott Wood | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ 12796b8a054SScott Wood | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 12896b8a054SScott Wood | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 129e1d8ed2cSPoonam Aggrwal /* 0x3835a322 */ 130e1d8ed2cSPoonam Aggrwal #define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 131e1d8ed2cSPoonam Aggrwal | ( 5 << TIMING_CFG2_CPO_SHIFT ) \ 13296b8a054SScott Wood | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 13396b8a054SScott Wood | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 13496b8a054SScott Wood | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 13596b8a054SScott Wood | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 136e1d8ed2cSPoonam Aggrwal | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 137e1d8ed2cSPoonam Aggrwal /* 0x129048c6 */ /* P9-45,may need tuning */ 138e1d8ed2cSPoonam Aggrwal #define CFG_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 139e1d8ed2cSPoonam Aggrwal | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 140e1d8ed2cSPoonam Aggrwal /* 0x05100500 */ 14196b8a054SScott Wood #if defined(CONFIG_DDR_2T_TIMING) 14296b8a054SScott Wood #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ 143bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 14496b8a054SScott Wood | SDRAM_CFG_2T_EN \ 14596b8a054SScott Wood | SDRAM_CFG_DBW_32 ) 14696b8a054SScott Wood #else 14796b8a054SScott Wood #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ 148bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 14996b8a054SScott Wood | SDRAM_CFG_32_BE ) 15096b8a054SScott Wood /* 0x43080000 */ 15196b8a054SScott Wood #endif 15296b8a054SScott Wood #define CFG_SDRAM_CFG2 0x00401000; 15396b8a054SScott Wood /* set burst length to 8 for 32-bit data path */ 154e1d8ed2cSPoonam Aggrwal #define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ 155e1d8ed2cSPoonam Aggrwal | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) ) 156e1d8ed2cSPoonam Aggrwal /* 0x44480632 */ 15796b8a054SScott Wood #define CFG_DDR_MODE_2 0x8000C000; 15896b8a054SScott Wood 15996b8a054SScott Wood #define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 16096b8a054SScott Wood /*0x02000000*/ 16196b8a054SScott Wood #define CFG_DDRCDR_VALUE ( DDRCDR_EN \ 16296b8a054SScott Wood | DDRCDR_PZ_NOMZ \ 16396b8a054SScott Wood | DDRCDR_NZ_NOMZ \ 16496b8a054SScott Wood | DDRCDR_M_ODR ) 16596b8a054SScott Wood 16696b8a054SScott Wood /* 16796b8a054SScott Wood * FLASH on the Local Bus 16896b8a054SScott Wood */ 16996b8a054SScott Wood #define CFG_FLASH_CFI /* use the Common Flash Interface */ 17096b8a054SScott Wood #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 17196b8a054SScott Wood #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ 17296b8a054SScott Wood #define CFG_FLASH_SIZE 8 /* flash size in MB */ 17396b8a054SScott Wood #define CFG_FLASH_EMPTY_INFO /* display empty sectors */ 17496b8a054SScott Wood #define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 17596b8a054SScott Wood 17696b8a054SScott Wood #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ 17796b8a054SScott Wood (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 17896b8a054SScott Wood BR_V) /* valid */ 17996b8a054SScott Wood #define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \ 18096b8a054SScott Wood | OR_GPCM_XACS \ 18196b8a054SScott Wood | OR_GPCM_SCY_9 \ 18296b8a054SScott Wood | OR_GPCM_EHTR \ 18396b8a054SScott Wood | OR_GPCM_EAD ) 18496b8a054SScott Wood /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 18596b8a054SScott Wood #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ 18696b8a054SScott Wood #define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ 18796b8a054SScott Wood 18896b8a054SScott Wood #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 18996b8a054SScott Wood #define CFG_MAX_FLASH_SECT 135 /* sectors per device */ 19096b8a054SScott Wood 19196b8a054SScott Wood #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 19296b8a054SScott Wood #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 19396b8a054SScott Wood 19496b8a054SScott Wood #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 19596b8a054SScott Wood 19696b8a054SScott Wood #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 19796b8a054SScott Wood #define CFG_RAMBOOT 19896b8a054SScott Wood #endif 19996b8a054SScott Wood 20096b8a054SScott Wood #define CFG_INIT_RAM_LOCK 1 20196b8a054SScott Wood #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 20296b8a054SScott Wood #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 20396b8a054SScott Wood 20496b8a054SScott Wood #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 20596b8a054SScott Wood #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 20696b8a054SScott Wood #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 20796b8a054SScott Wood 208b2893e1fSTimur Tabi /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ 20996b8a054SScott Wood #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 21096b8a054SScott Wood #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 21196b8a054SScott Wood 21296b8a054SScott Wood /* 21396b8a054SScott Wood * Local Bus LCRR and LBCR regs 21496b8a054SScott Wood */ 2154ce1e23bSYork Sun #define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4 21696b8a054SScott Wood #define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ 21796b8a054SScott Wood | (0xFF << LBCR_BMT_SHIFT) \ 21896b8a054SScott Wood | 0xF ) /* 0x0004ff0f */ 21996b8a054SScott Wood 22096b8a054SScott Wood #define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ 22196b8a054SScott Wood 2227817cb20SMarcel Ziswiler /* drivers/mtd/nand/nand.c */ 22396b8a054SScott Wood #define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ 22496b8a054SScott Wood #define CFG_MAX_NAND_DEVICE 1 22596b8a054SScott Wood #define NAND_MAX_CHIPS 1 22696b8a054SScott Wood #define CONFIG_MTD_NAND_VERIFY_WRITE 227*acdab5c3SScott Wood #define CONFIG_CMD_NAND 1 228*acdab5c3SScott Wood #define CONFIG_NAND_FSL_ELBC 1 22996b8a054SScott Wood 23096b8a054SScott Wood #define CFG_BR1_PRELIM ( CFG_NAND_BASE \ 23196b8a054SScott Wood | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 23296b8a054SScott Wood | BR_PS_8 /* Port Size = 8 bit */ \ 23396b8a054SScott Wood | BR_MS_FCM /* MSEL = FCM */ \ 23496b8a054SScott Wood | BR_V ) /* valid */ 23596b8a054SScott Wood #define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ 23696b8a054SScott Wood | OR_FCM_CSCT \ 23796b8a054SScott Wood | OR_FCM_CST \ 23896b8a054SScott Wood | OR_FCM_CHT \ 23996b8a054SScott Wood | OR_FCM_SCY_1 \ 24096b8a054SScott Wood | OR_FCM_TRLX \ 24196b8a054SScott Wood | OR_FCM_EHTR ) 24296b8a054SScott Wood /* 0xFFFF8396 */ 24396b8a054SScott Wood #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE 24496b8a054SScott Wood #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 24596b8a054SScott Wood 24696b8a054SScott Wood /* local bus read write buffer mapping */ 24796b8a054SScott Wood #define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ 24896b8a054SScott Wood #define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ 24996b8a054SScott Wood #define CFG_LBLAWBAR3_PRELIM 0xFA000000 25096b8a054SScott Wood #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 25196b8a054SScott Wood 25289c7784eSTimur Tabi /* Vitesse 7385 */ 25389c7784eSTimur Tabi 25489c7784eSTimur Tabi #define CFG_VSC7385_BASE 0xF0000000 25589c7784eSTimur Tabi 25689c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 25789c7784eSTimur Tabi 25889c7784eSTimur Tabi #define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ 25989c7784eSTimur Tabi #define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ 26089c7784eSTimur Tabi #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */ 26189c7784eSTimur Tabi #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ 26289c7784eSTimur Tabi 26389c7784eSTimur Tabi #endif 26489c7784eSTimur Tabi 26596b8a054SScott Wood /* pass open firmware flat tree */ 26635cc4e48SKim Phillips #define CONFIG_OF_LIBFDT 1 26796b8a054SScott Wood #define CONFIG_OF_BOARD_SETUP 1 2685b8bc606SKim Phillips #define CONFIG_OF_STDOUT_VIA_ALIAS 1 26996b8a054SScott Wood 27096b8a054SScott Wood /* 27196b8a054SScott Wood * Serial Port 27296b8a054SScott Wood */ 27396b8a054SScott Wood #define CONFIG_CONS_INDEX 1 27496b8a054SScott Wood #define CFG_NS16550 27596b8a054SScott Wood #define CFG_NS16550_SERIAL 27696b8a054SScott Wood #define CFG_NS16550_REG_SIZE 1 27796b8a054SScott Wood #define CFG_NS16550_CLK get_bus_freq(0) 27896b8a054SScott Wood 27996b8a054SScott Wood #define CFG_BAUDRATE_TABLE \ 28096b8a054SScott Wood {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 28196b8a054SScott Wood 28296b8a054SScott Wood #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 28396b8a054SScott Wood #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 28496b8a054SScott Wood 28596b8a054SScott Wood /* Use the HUSH parser */ 28696b8a054SScott Wood #define CFG_HUSH_PARSER 28796b8a054SScott Wood #define CFG_PROMPT_HUSH_PS2 "> " 28896b8a054SScott Wood 28996b8a054SScott Wood /* I2C */ 29096b8a054SScott Wood #define CONFIG_HARD_I2C /* I2C with hardware support*/ 29196b8a054SScott Wood #define CONFIG_FSL_I2C 29296b8a054SScott Wood #define CONFIG_I2C_MULTI_BUS 29396b8a054SScott Wood #define CONFIG_I2C_CMD_TREE 29496b8a054SScott Wood #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 29596b8a054SScott Wood #define CFG_I2C_SLAVE 0x7F 296cdd917a4SWolfgang Denk #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 29796b8a054SScott Wood #define CFG_I2C_OFFSET 0x3000 29896b8a054SScott Wood #define CFG_I2C2_OFFSET 0x3100 29996b8a054SScott Wood 30096b8a054SScott Wood /* 30196b8a054SScott Wood * General PCI 30296b8a054SScott Wood * Addresses are mapped 1-1. 30396b8a054SScott Wood */ 30496b8a054SScott Wood #define CFG_PCI1_MEM_BASE 0x80000000 30596b8a054SScott Wood #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 30696b8a054SScott Wood #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 30796b8a054SScott Wood #define CFG_PCI1_MMIO_BASE 0x90000000 30896b8a054SScott Wood #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 30996b8a054SScott Wood #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 31096b8a054SScott Wood #define CFG_PCI1_IO_BASE 0x00000000 31196b8a054SScott Wood #define CFG_PCI1_IO_PHYS 0xE2000000 31296b8a054SScott Wood #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 31396b8a054SScott Wood 31496b8a054SScott Wood #define CONFIG_PCI_PNP /* do pci plug-and-play */ 31596b8a054SScott Wood #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 31696b8a054SScott Wood 31796b8a054SScott Wood /* 31889c7784eSTimur Tabi * TSEC 31996b8a054SScott Wood */ 32096b8a054SScott Wood #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 32196b8a054SScott Wood 32289c7784eSTimur Tabi #define CONFIG_NET_MULTI 32389c7784eSTimur Tabi #define CONFIG_GMII /* MII PHY management */ 32489c7784eSTimur Tabi 32589c7784eSTimur Tabi #ifdef CONFIG_TSEC1 32689c7784eSTimur Tabi #define CONFIG_HAS_ETH0 32789c7784eSTimur Tabi #define CONFIG_TSEC1_NAME "TSEC0" 32889c7784eSTimur Tabi #define CFG_TSEC1_OFFSET 0x24000 32989c7784eSTimur Tabi #define TSEC1_PHY_ADDR 0x1c 33089c7784eSTimur Tabi #define TSEC1_FLAGS TSEC_GIGABIT 33189c7784eSTimur Tabi #define TSEC1_PHYIDX 0 33296b8a054SScott Wood #endif 33396b8a054SScott Wood 33489c7784eSTimur Tabi #ifdef CONFIG_TSEC2 33589c7784eSTimur Tabi #define CONFIG_HAS_ETH1 336255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 33789c7784eSTimur Tabi #define CFG_TSEC2_OFFSET 0x25000 33896b8a054SScott Wood #define TSEC2_PHY_ADDR 4 3393a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 34096b8a054SScott Wood #define TSEC2_PHYIDX 0 34189c7784eSTimur Tabi #endif 34289c7784eSTimur Tabi 34396b8a054SScott Wood 34496b8a054SScott Wood /* Options are: TSEC[0-1] */ 34596b8a054SScott Wood #define CONFIG_ETHPRIME "TSEC1" 34696b8a054SScott Wood 34796b8a054SScott Wood /* 34896b8a054SScott Wood * Configure on-board RTC 34996b8a054SScott Wood */ 35096b8a054SScott Wood #define CONFIG_RTC_DS1337 35196b8a054SScott Wood #define CFG_I2C_RTC_ADDR 0x68 35296b8a054SScott Wood 35396b8a054SScott Wood /* 35496b8a054SScott Wood * Environment 35596b8a054SScott Wood */ 35696b8a054SScott Wood #ifndef CFG_RAMBOOT 35796b8a054SScott Wood #define CFG_ENV_IS_IN_FLASH 1 358b2893e1fSTimur Tabi #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 35996b8a054SScott Wood #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 36096b8a054SScott Wood #define CFG_ENV_SIZE 0x2000 36196b8a054SScott Wood 36296b8a054SScott Wood /* Address and size of Redundant Environment Sector */ 36396b8a054SScott Wood #else 36496b8a054SScott Wood #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 36596b8a054SScott Wood #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 36696b8a054SScott Wood #define CFG_ENV_SIZE 0x2000 36796b8a054SScott Wood #endif 36896b8a054SScott Wood 36996b8a054SScott Wood #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 37096b8a054SScott Wood #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 37196b8a054SScott Wood 3728ea5499aSJon Loeliger /* 373079a136cSJon Loeliger * BOOTP options 374079a136cSJon Loeliger */ 375079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 376079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTPATH 377079a136cSJon Loeliger #define CONFIG_BOOTP_GATEWAY 378079a136cSJon Loeliger #define CONFIG_BOOTP_HOSTNAME 379079a136cSJon Loeliger 380079a136cSJon Loeliger 381079a136cSJon Loeliger /* 3828ea5499aSJon Loeliger * Command line configuration. 3838ea5499aSJon Loeliger */ 3848ea5499aSJon Loeliger #include <config_cmd_default.h> 3858ea5499aSJon Loeliger 3868ea5499aSJon Loeliger #define CONFIG_CMD_PING 3878ea5499aSJon Loeliger #define CONFIG_CMD_DHCP 3888ea5499aSJon Loeliger #define CONFIG_CMD_I2C 3898ea5499aSJon Loeliger #define CONFIG_CMD_MII 3908ea5499aSJon Loeliger #define CONFIG_CMD_DATE 3918ea5499aSJon Loeliger #define CONFIG_CMD_PCI 3928ea5499aSJon Loeliger 3938ea5499aSJon Loeliger #if defined(CFG_RAMBOOT) 3948ea5499aSJon Loeliger #undef CONFIG_CMD_ENV 3958ea5499aSJon Loeliger #undef CONFIG_CMD_LOADS 3968ea5499aSJon Loeliger #endif 39796b8a054SScott Wood 39896b8a054SScott Wood #define CONFIG_CMDLINE_EDITING 1 39996b8a054SScott Wood 40096b8a054SScott Wood 40196b8a054SScott Wood /* 40296b8a054SScott Wood * Miscellaneous configurable options 40396b8a054SScott Wood */ 40496b8a054SScott Wood #define CFG_LONGHELP /* undef to save memory */ 40596b8a054SScott Wood #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 40696b8a054SScott Wood #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 40796b8a054SScott Wood #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 40896b8a054SScott Wood 40996b8a054SScott Wood #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 41096b8a054SScott Wood #define CFG_MAXARGS 16 /* max number of command args */ 41196b8a054SScott Wood #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 41296b8a054SScott Wood #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 41396b8a054SScott Wood 41496b8a054SScott Wood /* 41596b8a054SScott Wood * For booting Linux, the board info and command line data 41696b8a054SScott Wood * have to be in the first 8 MB of memory, since this is 41796b8a054SScott Wood * the maximum mapped by the Linux kernel during initialization. 41896b8a054SScott Wood */ 41996b8a054SScott Wood #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 42096b8a054SScott Wood 42196b8a054SScott Wood #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 42296b8a054SScott Wood 42396b8a054SScott Wood #ifdef CFG_66MHZ 42496b8a054SScott Wood 42596b8a054SScott Wood /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 42696b8a054SScott Wood /* 0x62040000 */ 42796b8a054SScott Wood #define CFG_HRCW_LOW (\ 42896b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 42996b8a054SScott Wood HRCWL_DDRCM |\ 43096b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 43196b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 43296b8a054SScott Wood HRCWL_CSB_TO_CLKIN_2X1 |\ 43396b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 43496b8a054SScott Wood 43596b8a054SScott Wood #elif defined(CFG_33MHZ) 43696b8a054SScott Wood 43796b8a054SScott Wood /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 43896b8a054SScott Wood /* 0x65040000 */ 43996b8a054SScott Wood #define CFG_HRCW_LOW (\ 44096b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 44196b8a054SScott Wood HRCWL_DDRCM |\ 44296b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 44396b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 44496b8a054SScott Wood HRCWL_CSB_TO_CLKIN_5X1 |\ 44596b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 44696b8a054SScott Wood 44796b8a054SScott Wood #endif 44896b8a054SScott Wood 44996b8a054SScott Wood /* 0xa0606c00 */ 45096b8a054SScott Wood #define CFG_HRCW_HIGH (\ 45196b8a054SScott Wood HRCWH_PCI_HOST |\ 45296b8a054SScott Wood HRCWH_PCI1_ARBITER_ENABLE |\ 45396b8a054SScott Wood HRCWH_CORE_ENABLE |\ 45496b8a054SScott Wood HRCWH_FROM_0X00000100 |\ 45596b8a054SScott Wood HRCWH_BOOTSEQ_DISABLE |\ 45696b8a054SScott Wood HRCWH_SW_WATCHDOG_DISABLE |\ 45796b8a054SScott Wood HRCWH_ROM_LOC_LOCAL_16BIT |\ 45896b8a054SScott Wood HRCWH_RL_EXT_LEGACY |\ 45996b8a054SScott Wood HRCWH_TSEC1M_IN_RGMII |\ 46096b8a054SScott Wood HRCWH_TSEC2M_IN_RGMII |\ 46196b8a054SScott Wood HRCWH_BIG_ENDIAN |\ 46296b8a054SScott Wood HRCWH_LALE_NORMAL) 46396b8a054SScott Wood 46496b8a054SScott Wood /* System IO Config */ 46596b8a054SScott Wood #define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 46696b8a054SScott Wood #define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ 46796b8a054SScott Wood 46896b8a054SScott Wood #define CFG_HID0_INIT 0x000000000 46996b8a054SScott Wood #define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 47096b8a054SScott Wood HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 47196b8a054SScott Wood 47296b8a054SScott Wood #define CFG_HID2 HID2_HBE 47396b8a054SScott Wood 47431d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 47531d82672SBecky Bruce 47696b8a054SScott Wood /* DDR @ 0x00000000 */ 47796b8a054SScott Wood #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) 47896b8a054SScott Wood #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 47996b8a054SScott Wood 48096b8a054SScott Wood /* PCI @ 0x80000000 */ 48196b8a054SScott Wood #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10) 48296b8a054SScott Wood #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 48396b8a054SScott Wood #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 48496b8a054SScott Wood #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 48596b8a054SScott Wood 48696b8a054SScott Wood /* PCI2 not supported on 8313 */ 48796b8a054SScott Wood #define CFG_IBAT3L (0) 48896b8a054SScott Wood #define CFG_IBAT3U (0) 48996b8a054SScott Wood #define CFG_IBAT4L (0) 49096b8a054SScott Wood #define CFG_IBAT4U (0) 49196b8a054SScott Wood 49296b8a054SScott Wood /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 49396b8a054SScott Wood #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 49496b8a054SScott Wood #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 49596b8a054SScott Wood 49696b8a054SScott Wood /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 49796b8a054SScott Wood #define CFG_IBAT6L (0xF0000000 | BATL_PP_10) 49896b8a054SScott Wood #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 49996b8a054SScott Wood 50096b8a054SScott Wood #define CFG_IBAT7L (0) 50196b8a054SScott Wood #define CFG_IBAT7U (0) 50296b8a054SScott Wood 50396b8a054SScott Wood #define CFG_DBAT0L CFG_IBAT0L 50496b8a054SScott Wood #define CFG_DBAT0U CFG_IBAT0U 50596b8a054SScott Wood #define CFG_DBAT1L CFG_IBAT1L 50696b8a054SScott Wood #define CFG_DBAT1U CFG_IBAT1U 50796b8a054SScott Wood #define CFG_DBAT2L CFG_IBAT2L 50896b8a054SScott Wood #define CFG_DBAT2U CFG_IBAT2U 50996b8a054SScott Wood #define CFG_DBAT3L CFG_IBAT3L 51096b8a054SScott Wood #define CFG_DBAT3U CFG_IBAT3U 51196b8a054SScott Wood #define CFG_DBAT4L CFG_IBAT4L 51296b8a054SScott Wood #define CFG_DBAT4U CFG_IBAT4U 51396b8a054SScott Wood #define CFG_DBAT5L CFG_IBAT5L 51496b8a054SScott Wood #define CFG_DBAT5U CFG_IBAT5U 51596b8a054SScott Wood #define CFG_DBAT6L CFG_IBAT6L 51696b8a054SScott Wood #define CFG_DBAT6U CFG_IBAT6U 51796b8a054SScott Wood #define CFG_DBAT7L CFG_IBAT7L 51896b8a054SScott Wood #define CFG_DBAT7U CFG_IBAT7U 51996b8a054SScott Wood 52096b8a054SScott Wood /* 52196b8a054SScott Wood * Internal Definitions 52296b8a054SScott Wood * 52396b8a054SScott Wood * Boot Flags 52496b8a054SScott Wood */ 52596b8a054SScott Wood #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 52696b8a054SScott Wood #define BOOTFLAG_WARM 0x02 /* Software reboot */ 52796b8a054SScott Wood 52896b8a054SScott Wood /* 52996b8a054SScott Wood * Environment Configuration 53096b8a054SScott Wood */ 53196b8a054SScott Wood #define CONFIG_ENV_OVERWRITE 53296b8a054SScott Wood 53396b8a054SScott Wood #define CONFIG_ETHADDR 00:E0:0C:00:95:01 53496b8a054SScott Wood #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 53596b8a054SScott Wood 53696b8a054SScott Wood #define CONFIG_IPADDR 10.0.0.2 53796b8a054SScott Wood #define CONFIG_SERVERIP 10.0.0.1 53896b8a054SScott Wood #define CONFIG_GATEWAYIP 10.0.0.1 53996b8a054SScott Wood #define CONFIG_NETMASK 255.0.0.0 54096b8a054SScott Wood #define CONFIG_NETDEV eth1 54196b8a054SScott Wood 54296b8a054SScott Wood #define CONFIG_HOSTNAME mpc8313erdb 54396b8a054SScott Wood #define CONFIG_ROOTPATH /nfs/root/path 54496b8a054SScott Wood #define CONFIG_BOOTFILE uImage 54596b8a054SScott Wood #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 54696b8a054SScott Wood #define CONFIG_FDTFILE mpc8313erdb.dtb 54796b8a054SScott Wood 548b2115757SKim Phillips #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ 54996b8a054SScott Wood #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 55096b8a054SScott Wood #define CONFIG_BAUDRATE 115200 55196b8a054SScott Wood 55296b8a054SScott Wood #define XMK_STR(x) #x 55396b8a054SScott Wood #define MK_STR(x) XMK_STR(x) 55496b8a054SScott Wood 55596b8a054SScott Wood #define CONFIG_EXTRA_ENV_SETTINGS \ 55696b8a054SScott Wood "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 55796b8a054SScott Wood "ethprime=TSEC1\0" \ 55896b8a054SScott Wood "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 55996b8a054SScott Wood "tftpflash=tftpboot $loadaddr $uboot; " \ 56096b8a054SScott Wood "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 56196b8a054SScott Wood "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 56296b8a054SScott Wood "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 56396b8a054SScott Wood "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 56496b8a054SScott Wood "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 56596b8a054SScott Wood "fdtaddr=400000\0" \ 56696b8a054SScott Wood "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 56796b8a054SScott Wood "console=ttyS0\0" \ 56896b8a054SScott Wood "setbootargs=setenv bootargs " \ 56996b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 57096b8a054SScott Wood "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 57196b8a054SScott Wood "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 57296b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 57396b8a054SScott Wood 57496b8a054SScott Wood #define CONFIG_NFSBOOTCOMMAND \ 57596b8a054SScott Wood "setenv rootdev /dev/nfs;" \ 57696b8a054SScott Wood "run setbootargs;" \ 57796b8a054SScott Wood "run setipargs;" \ 57896b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 57996b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 58096b8a054SScott Wood "bootm $loadaddr - $fdtaddr" 58196b8a054SScott Wood 58296b8a054SScott Wood #define CONFIG_RAMBOOTCOMMAND \ 58396b8a054SScott Wood "setenv rootdev /dev/ram;" \ 58496b8a054SScott Wood "run setbootargs;" \ 58596b8a054SScott Wood "tftp $ramdiskaddr $ramdiskfile;" \ 58696b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 58796b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 58896b8a054SScott Wood "bootm $loadaddr $ramdiskaddr $fdtaddr" 58996b8a054SScott Wood 59096b8a054SScott Wood #undef MK_STR 59196b8a054SScott Wood #undef XMK_STR 59296b8a054SScott Wood 59396b8a054SScott Wood #endif /* __CONFIG_H */ 594