183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 296b8a054SScott Wood /* 3e8d3ca8bSScott Wood * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 496b8a054SScott Wood */ 596b8a054SScott Wood /* 696b8a054SScott Wood * mpc8313epb board configuration file 796b8a054SScott Wood */ 896b8a054SScott Wood 996b8a054SScott Wood #ifndef __CONFIG_H 1096b8a054SScott Wood #define __CONFIG_H 1196b8a054SScott Wood 1296b8a054SScott Wood /* 1396b8a054SScott Wood * High Level Configuration Options 1496b8a054SScott Wood */ 1596b8a054SScott Wood #define CONFIG_E300 1 162c7920afSPeter Tyser #define CONFIG_MPC831x 1 1796b8a054SScott Wood #define CONFIG_MPC8313 1 1896b8a054SScott Wood #define CONFIG_MPC8313ERDB 1 1996b8a054SScott Wood 2022f4442dSScott Wood #ifdef CONFIG_NAND 2122f4442dSScott Wood #define CONFIG_SPL_INIT_MINIMAL 2222f4442dSScott Wood #define CONFIG_SPL_FLUSH_IMAGE 2322f4442dSScott Wood #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 2422f4442dSScott Wood #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 2522f4442dSScott Wood 2622f4442dSScott Wood #ifdef CONFIG_SPL_BUILD 2722f4442dSScott Wood #define CONFIG_NS16550_MIN_FUNCTIONS 2822f4442dSScott Wood #endif 2922f4442dSScott Wood 3022f4442dSScott Wood #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 3122f4442dSScott Wood #define CONFIG_SPL_MAX_SIZE (4 * 1024) 326113d3f2SBenoît Thébaudeau #define CONFIG_SPL_PAD_TO 0x4000 3322f4442dSScott Wood 34f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 35f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 36f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 37f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 38f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 39f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 40f1c574d4SScott Wood 4122f4442dSScott Wood #ifdef CONFIG_SPL_BUILD 42f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 4322f4442dSScott Wood #endif 4422f4442dSScott Wood 4522f4442dSScott Wood #endif /* CONFIG_NAND */ 46f1c574d4SScott Wood 47f1c574d4SScott Wood #ifndef CONFIG_SYS_MONITOR_BASE 48f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 49f1c574d4SScott Wood #endif 50f1c574d4SScott Wood 51842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 520914f483SBecky Bruce #define CONFIG_FSL_ELBC 1 5396b8a054SScott Wood 5489c7784eSTimur Tabi /* 5589c7784eSTimur Tabi * On-board devices 564ce1e23bSYork Sun * 574ce1e23bSYork Sun * TSEC1 is VSC switch 584ce1e23bSYork Sun * TSEC2 is SoC TSEC 5989c7784eSTimur Tabi */ 6089c7784eSTimur Tabi #define CONFIG_VSC7385_ENET 614ce1e23bSYork Sun #define CONFIG_TSEC2 6289c7784eSTimur Tabi 636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 645c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 665c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 6796b8a054SScott Wood #else 6896b8a054SScott Wood #error Unknown oscillator frequency. 6996b8a054SScott Wood #endif 7096b8a054SScott Wood 7196b8a054SScott Wood #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 7296b8a054SScott Wood 736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 7496b8a054SScott Wood 7522f4442dSScott Wood #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) 766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 77e4c09508SScott Wood #endif 78e4c09508SScott Wood 796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00001000 806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x07f00000 8196b8a054SScott Wood 8296b8a054SScott Wood /* Early revs of this board will lock up hard when attempting 8396b8a054SScott Wood * to access the PMC registers, unless a JTAG debugger is 8496b8a054SScott Wood * connected, or some resistor modifications are made. 8596b8a054SScott Wood */ 866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 8796b8a054SScott Wood 886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 9096b8a054SScott Wood 9196b8a054SScott Wood /* 9289c7784eSTimur Tabi * Device configurations 9389c7784eSTimur Tabi */ 9489c7784eSTimur Tabi 9589c7784eSTimur Tabi /* Vitesse 7385 */ 9689c7784eSTimur Tabi 9789c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 9889c7784eSTimur Tabi 994ce1e23bSYork Sun #define CONFIG_TSEC1 10089c7784eSTimur Tabi 10189c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 10289c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFE7FE000 10389c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 10489c7784eSTimur Tabi 10589c7784eSTimur Tabi #endif 10689c7784eSTimur Tabi 10789c7784eSTimur Tabi /* 10896b8a054SScott Wood * DDR Setup 10996b8a054SScott Wood */ 1106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 11396b8a054SScott Wood 11496b8a054SScott Wood /* 11596b8a054SScott Wood * Manually set up DDR parameters, as this board does not 11696b8a054SScott Wood * seem to have the SPD connected to I2C. 11796b8a054SScott Wood */ 1186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 1192e651b24SJoe Hershberger #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 1202fef4020SJoe Hershberger | CSCONFIG_ODT_RD_NEVER \ 1212fef4020SJoe Hershberger | CSCONFIG_ODT_WR_ONLY_CURRENT \ 122261c07bcSJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 123261c07bcSJoe Hershberger | CSCONFIG_COL_BIT_10) 124e1d8ed2cSPoonam Aggrwal /* 0x80010102 */ 12596b8a054SScott Wood 1266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_3 0x00000000 1276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 12896b8a054SScott Wood | (0 << TIMING_CFG0_WRT_SHIFT) \ 12996b8a054SScott Wood | (0 << TIMING_CFG0_RRT_SHIFT) \ 13096b8a054SScott Wood | (0 << TIMING_CFG0_WWT_SHIFT) \ 13196b8a054SScott Wood | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 13296b8a054SScott Wood | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 13396b8a054SScott Wood | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 13496b8a054SScott Wood | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 13596b8a054SScott Wood /* 0x00220802 */ 1366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 137e1d8ed2cSPoonam Aggrwal | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 13896b8a054SScott Wood | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 13996b8a054SScott Wood | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 140e1d8ed2cSPoonam Aggrwal | (10 << TIMING_CFG1_REFREC_SHIFT) \ 14196b8a054SScott Wood | (3 << TIMING_CFG1_WRREC_SHIFT) \ 14296b8a054SScott Wood | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 14396b8a054SScott Wood | (2 << TIMING_CFG1_WRTORD_SHIFT)) 144e1d8ed2cSPoonam Aggrwal /* 0x3835a322 */ 1456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 146e1d8ed2cSPoonam Aggrwal | (5 << TIMING_CFG2_CPO_SHIFT) \ 14796b8a054SScott Wood | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 14896b8a054SScott Wood | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 14996b8a054SScott Wood | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 15096b8a054SScott Wood | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 151e1d8ed2cSPoonam Aggrwal | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 152e1d8ed2cSPoonam Aggrwal /* 0x129048c6 */ /* P9-45,may need tuning */ 1536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 154e1d8ed2cSPoonam Aggrwal | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 155e1d8ed2cSPoonam Aggrwal /* 0x05100500 */ 15696b8a054SScott Wood #if defined(CONFIG_DDR_2T_TIMING) 1576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 158bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1592fef4020SJoe Hershberger | SDRAM_CFG_DBW_32 \ 1602fef4020SJoe Hershberger | SDRAM_CFG_2T_EN) 1612fef4020SJoe Hershberger /* 0x43088000 */ 16296b8a054SScott Wood #else 1636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 164bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1652fef4020SJoe Hershberger | SDRAM_CFG_DBW_32) 16696b8a054SScott Wood /* 0x43080000 */ 16796b8a054SScott Wood #endif 1686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG2 0x00401000 16996b8a054SScott Wood /* set burst length to 8 for 32-bit data path */ 1706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 171e1d8ed2cSPoonam Aggrwal | (0x0632 << SDRAM_MODE_SD_SHIFT)) 172e1d8ed2cSPoonam Aggrwal /* 0x44480632 */ 1736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x8000C000 17496b8a054SScott Wood 1756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 17696b8a054SScott Wood /*0x02000000*/ 1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 17896b8a054SScott Wood | DDRCDR_PZ_NOMZ \ 17996b8a054SScott Wood | DDRCDR_NZ_NOMZ \ 18096b8a054SScott Wood | DDRCDR_M_ODR) 18196b8a054SScott Wood 18296b8a054SScott Wood /* 18396b8a054SScott Wood * FLASH on the Local Bus 18496b8a054SScott Wood */ 1856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 18600b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 1876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 1886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 1896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 1906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 1916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 19296b8a054SScott Wood 193261c07bcSJoe Hershberger #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 1947d6a0982SJoe Hershberger | BR_PS_16 /* 16 bit port */ \ 1957d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 196261c07bcSJoe Hershberger | BR_V) /* valid */ 1977d6a0982SJoe Hershberger #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 19896b8a054SScott Wood | OR_GPCM_XACS \ 19996b8a054SScott Wood | OR_GPCM_SCY_9 \ 20096b8a054SScott Wood | OR_GPCM_EHTR \ 20196b8a054SScott Wood | OR_GPCM_EAD) 20296b8a054SScott Wood /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 203261c07bcSJoe Hershberger /* window base at flash base */ 204261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2057d6a0982SJoe Hershberger /* 16 MB window size */ 2067d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 20796b8a054SScott Wood 2086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 2096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 21096b8a054SScott Wood 2116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 21396b8a054SScott Wood 214261c07bcSJoe Hershberger #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 21522f4442dSScott Wood !defined(CONFIG_SPL_BUILD) 2166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 21796b8a054SScott Wood #endif 21896b8a054SScott Wood 2196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 220261c07bcSJoe Hershberger #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 221553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 22296b8a054SScott Wood 223261c07bcSJoe Hershberger #define CONFIG_SYS_GBL_DATA_OFFSET \ 224261c07bcSJoe Hershberger (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 22696b8a054SScott Wood 2276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 22816c8c170SKevin Hao #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 2296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 23096b8a054SScott Wood 23196b8a054SScott Wood /* 23296b8a054SScott Wood * Local Bus LCRR and LBCR regs 23396b8a054SScott Wood */ 234c7190f02SKim Phillips #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 235c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 2366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 23796b8a054SScott Wood | (0xFF << LBCR_BMT_SHIFT) \ 23896b8a054SScott Wood | 0xF) /* 0x0004ff0f */ 23996b8a054SScott Wood 240261c07bcSJoe Hershberger /* LB refresh timer prescal, 266MHz/32 */ 241261c07bcSJoe Hershberger #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 24296b8a054SScott Wood 243*a430fa06SMiquel Raynal /* drivers/mtd/nand/raw/nand.c */ 24422f4442dSScott Wood #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) 2456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xFFF00000 246e4c09508SScott Wood #else 2476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xE2800000 248e4c09508SScott Wood #endif 249e4c09508SScott Wood 250e8d3ca8bSScott Wood #define CONFIG_MTD_PARTITION 251e8d3ca8bSScott Wood 2526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_NAND_DEVICE 1 253acdab5c3SScott Wood #define CONFIG_NAND_FSL_ELBC 1 2546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 2557d6a0982SJoe Hershberger #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 25696b8a054SScott Wood 2576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 2587d6a0982SJoe Hershberger | BR_DECC_CHK_GEN /* Use HW ECC */ \ 259261c07bcSJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 26096b8a054SScott Wood | BR_MS_FCM /* MSEL = FCM */ \ 26196b8a054SScott Wood | BR_V) /* valid */ 2627d6a0982SJoe Hershberger #define CONFIG_SYS_NAND_OR_PRELIM \ 2637d6a0982SJoe Hershberger (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 26496b8a054SScott Wood | OR_FCM_CSCT \ 26596b8a054SScott Wood | OR_FCM_CST \ 26696b8a054SScott Wood | OR_FCM_CHT \ 26796b8a054SScott Wood | OR_FCM_SCY_1 \ 26896b8a054SScott Wood | OR_FCM_TRLX \ 26996b8a054SScott Wood | OR_FCM_EHTR) 27096b8a054SScott Wood /* 0xFFFF8396 */ 271e4c09508SScott Wood 27222f4442dSScott Wood #ifdef CONFIG_NAND 2736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 2756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 277e4c09508SScott Wood #else 2786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 2806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 282e4c09508SScott Wood #endif 283e4c09508SScott Wood 2846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 2857d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 28696b8a054SScott Wood 2876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 2886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 289e4c09508SScott Wood 2907d6a0982SJoe Hershberger /* local bus write LED / read status buffer (BCSR) mapping */ 2917d6a0982SJoe Hershberger #define CONFIG_SYS_BCSR_ADDR 0xFA000000 2927d6a0982SJoe Hershberger #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 2937d6a0982SJoe Hershberger /* map at 0xFA000000 on LCS3 */ 2947d6a0982SJoe Hershberger #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 2957d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 2967d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 2977d6a0982SJoe Hershberger | BR_V) /* valid */ 2987d6a0982SJoe Hershberger /* 0xFA000801 */ 2997d6a0982SJoe Hershberger #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 3007d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 3017d6a0982SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 3027d6a0982SJoe Hershberger | OR_GPCM_XACS \ 3037d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 3047d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 3057d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 3067d6a0982SJoe Hershberger | OR_GPCM_EAD) 3077d6a0982SJoe Hershberger /* 0xFFFF8FF7 */ 3087d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 3097d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 31096b8a054SScott Wood 31189c7784eSTimur Tabi /* Vitesse 7385 */ 31289c7784eSTimur Tabi 31389c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 31489c7784eSTimur Tabi 3157d6a0982SJoe Hershberger /* VSC7385 Base address on LCS2 */ 3167d6a0982SJoe Hershberger #define CONFIG_SYS_VSC7385_BASE 0xF0000000 3177d6a0982SJoe Hershberger #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 3187d6a0982SJoe Hershberger 3197d6a0982SJoe Hershberger #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 3207d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 3217d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 3227d6a0982SJoe Hershberger | BR_V) /* valid */ 3237d6a0982SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 3247d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 3257d6a0982SJoe Hershberger | OR_GPCM_XACS \ 3267d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 3277d6a0982SJoe Hershberger | OR_GPCM_SETA \ 3287d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 3297d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 3307d6a0982SJoe Hershberger | OR_GPCM_EAD) 3317d6a0982SJoe Hershberger /* 0xFFFE09FF */ 3327d6a0982SJoe Hershberger 333261c07bcSJoe Hershberger /* Access window base at VSC7385 base */ 334261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 3357d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 33689c7784eSTimur Tabi 33789c7784eSTimur Tabi #endif 33889c7784eSTimur Tabi 3390eaf8f9eSJoe Hershberger #define CONFIG_MPC83XX_GPIO 1 3400eaf8f9eSJoe Hershberger 34196b8a054SScott Wood /* 34296b8a054SScott Wood * Serial Port 34396b8a054SScott Wood */ 3446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 34696b8a054SScott Wood 3476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 34896b8a054SScott Wood {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 34996b8a054SScott Wood 3506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 3516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 35296b8a054SScott Wood 35396b8a054SScott Wood /* I2C */ 35400f792e0SHeiko Schocher #define CONFIG_SYS_I2C 35500f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 35600f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 35700f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 35800f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 35900f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 400000 36000f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 36100f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 36200f792e0SHeiko Schocher #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 36396b8a054SScott Wood 36496b8a054SScott Wood /* 36596b8a054SScott Wood * General PCI 36696b8a054SScott Wood * Addresses are mapped 1-1. 36796b8a054SScott Wood */ 3686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 3706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 3716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 3726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 3736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 3756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 3766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 37796b8a054SScott Wood 3786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 37996b8a054SScott Wood 38096b8a054SScott Wood /* 38189c7784eSTimur Tabi * TSEC 38296b8a054SScott Wood */ 38396b8a054SScott Wood 38489c7784eSTimur Tabi #define CONFIG_GMII /* MII PHY management */ 38589c7784eSTimur Tabi 38689c7784eSTimur Tabi #ifdef CONFIG_TSEC1 38789c7784eSTimur Tabi #define CONFIG_HAS_ETH0 38889c7784eSTimur Tabi #define CONFIG_TSEC1_NAME "TSEC0" 3896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 39089c7784eSTimur Tabi #define TSEC1_PHY_ADDR 0x1c 39189c7784eSTimur Tabi #define TSEC1_FLAGS TSEC_GIGABIT 39289c7784eSTimur Tabi #define TSEC1_PHYIDX 0 39396b8a054SScott Wood #endif 39496b8a054SScott Wood 39589c7784eSTimur Tabi #ifdef CONFIG_TSEC2 39689c7784eSTimur Tabi #define CONFIG_HAS_ETH1 397255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 3986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 39996b8a054SScott Wood #define TSEC2_PHY_ADDR 4 4003a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 40196b8a054SScott Wood #define TSEC2_PHYIDX 0 40289c7784eSTimur Tabi #endif 40389c7784eSTimur Tabi 40496b8a054SScott Wood /* Options are: TSEC[0-1] */ 40596b8a054SScott Wood #define CONFIG_ETHPRIME "TSEC1" 40696b8a054SScott Wood 40796b8a054SScott Wood /* 40896b8a054SScott Wood * Configure on-board RTC 40996b8a054SScott Wood */ 41096b8a054SScott Wood #define CONFIG_RTC_DS1337 4116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 41296b8a054SScott Wood 41396b8a054SScott Wood /* 41496b8a054SScott Wood * Environment 41596b8a054SScott Wood */ 41622f4442dSScott Wood #if defined(CONFIG_NAND) 4170e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET (512 * 1024) 4186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 4190e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 4200e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 4210e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 422261c07bcSJoe Hershberger #define CONFIG_ENV_OFFSET_REDUND \ 423261c07bcSJoe Hershberger (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 4246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif !defined(CONFIG_SYS_RAMBOOT) 425261c07bcSJoe Hershberger #define CONFIG_ENV_ADDR \ 426261c07bcSJoe Hershberger (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4270e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 4280e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 42996b8a054SScott Wood 43096b8a054SScott Wood /* Address and size of Redundant Environment Sector */ 43196b8a054SScott Wood #else 4326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4330e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 43496b8a054SScott Wood #endif 43596b8a054SScott Wood 43696b8a054SScott Wood #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 4376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 43896b8a054SScott Wood 4398ea5499aSJon Loeliger /* 440079a136cSJon Loeliger * BOOTP options 441079a136cSJon Loeliger */ 442079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 443079a136cSJon Loeliger 444079a136cSJon Loeliger /* 4458ea5499aSJon Loeliger * Command line configuration. 4468ea5499aSJon Loeliger */ 4478ea5499aSJon Loeliger 44896b8a054SScott Wood /* 44996b8a054SScott Wood * Miscellaneous configurable options 45096b8a054SScott Wood */ 4516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 4526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 45396b8a054SScott Wood 454261c07bcSJoe Hershberger /* Boot Argument Buffer Size */ 455261c07bcSJoe Hershberger #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 45696b8a054SScott Wood 45796b8a054SScott Wood /* 45896b8a054SScott Wood * For booting Linux, the board info and command line data 4599f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 46096b8a054SScott Wood * the maximum mapped by the Linux kernel during initialization. 46196b8a054SScott Wood */ 462261c07bcSJoe Hershberger /* Initial Memory map for Linux*/ 463261c07bcSJoe Hershberger #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 46463865278SKevin Hao #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 46596b8a054SScott Wood 4666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 46796b8a054SScott Wood 4686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 46996b8a054SScott Wood 47096b8a054SScott Wood /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 47196b8a054SScott Wood /* 0x62040000 */ 4726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 47396b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 47496b8a054SScott Wood HRCWL_DDRCM |\ 47596b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 47696b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 47796b8a054SScott Wood HRCWL_CSB_TO_CLKIN_2X1 |\ 47896b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 47996b8a054SScott Wood 4806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 481e4c09508SScott Wood 4826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 48396b8a054SScott Wood 48496b8a054SScott Wood /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 48596b8a054SScott Wood /* 0x65040000 */ 4866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 48796b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 48896b8a054SScott Wood HRCWL_DDRCM |\ 48996b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 49096b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 49196b8a054SScott Wood HRCWL_CSB_TO_CLKIN_5X1 |\ 49296b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 49396b8a054SScott Wood 4946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 495e4c09508SScott Wood 49696b8a054SScott Wood #endif 49796b8a054SScott Wood 4986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH_BASE (\ 49996b8a054SScott Wood HRCWH_PCI_HOST |\ 50096b8a054SScott Wood HRCWH_PCI1_ARBITER_ENABLE |\ 50196b8a054SScott Wood HRCWH_CORE_ENABLE |\ 50296b8a054SScott Wood HRCWH_BOOTSEQ_DISABLE |\ 50396b8a054SScott Wood HRCWH_SW_WATCHDOG_DISABLE |\ 50496b8a054SScott Wood HRCWH_TSEC1M_IN_RGMII |\ 50596b8a054SScott Wood HRCWH_TSEC2M_IN_RGMII |\ 506e4c09508SScott Wood HRCWH_BIG_ENDIAN) 507e4c09508SScott Wood 50822f4442dSScott Wood #ifdef CONFIG_NAND 5096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 510e4c09508SScott Wood HRCWH_FROM_0XFFF00100 |\ 511e4c09508SScott Wood HRCWH_ROM_LOC_NAND_SP_8BIT |\ 512e4c09508SScott Wood HRCWH_RL_EXT_NAND) 513e4c09508SScott Wood #else 5146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 515e4c09508SScott Wood HRCWH_FROM_0X00000100 |\ 516e4c09508SScott Wood HRCWH_ROM_LOC_LOCAL_16BIT |\ 517e4c09508SScott Wood HRCWH_RL_EXT_LEGACY) 518e4c09508SScott Wood #endif 51996b8a054SScott Wood 52096b8a054SScott Wood /* System IO Config */ 5216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 5220eaf8f9eSJoe Hershberger /* Enable Internal USB Phy and GPIO on LCD Connector */ 5230eaf8f9eSJoe Hershberger #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 52496b8a054SScott Wood 5256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_INIT 0x000000000 5266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 5271a2e203bSKim Phillips HID0_ENABLE_INSTRUCTION_CACHE | \ 52896b8a054SScott Wood HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 52996b8a054SScott Wood 5306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 53196b8a054SScott Wood 53231d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 53331d82672SBecky Bruce 53496b8a054SScott Wood /* DDR @ 0x00000000 */ 53572cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 536261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 537261c07bcSJoe Hershberger | BATU_BL_256M \ 538261c07bcSJoe Hershberger | BATU_VS \ 539261c07bcSJoe Hershberger | BATU_VP) 54096b8a054SScott Wood 54196b8a054SScott Wood /* PCI @ 0x80000000 */ 54272cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 543261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 544261c07bcSJoe Hershberger | BATU_BL_256M \ 545261c07bcSJoe Hershberger | BATU_VS \ 546261c07bcSJoe Hershberger | BATU_VP) 547261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 54872cd4087SJoe Hershberger | BATL_PP_RW \ 549261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 550261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 551261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 552261c07bcSJoe Hershberger | BATU_BL_256M \ 553261c07bcSJoe Hershberger | BATU_VS \ 554261c07bcSJoe Hershberger | BATU_VP) 55596b8a054SScott Wood 55696b8a054SScott Wood /* PCI2 not supported on 8313 */ 5576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L (0) 5586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U (0) 5596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L (0) 5606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U (0) 56196b8a054SScott Wood 56296b8a054SScott Wood /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 563261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 56472cd4087SJoe Hershberger | BATL_PP_RW \ 565261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 566261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 567261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 568261c07bcSJoe Hershberger | BATU_BL_256M \ 569261c07bcSJoe Hershberger | BATU_VS \ 570261c07bcSJoe Hershberger | BATU_VP) 57196b8a054SScott Wood 57296b8a054SScott Wood /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 57372cd4087SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 5746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 57596b8a054SScott Wood 5766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L (0) 5776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U (0) 57896b8a054SScott Wood 5796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 5806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 5816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 5826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 5836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 5846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 5856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 5866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 5876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 5886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 5896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 5906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 5916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 5926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 5936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 5946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 59596b8a054SScott Wood 59696b8a054SScott Wood /* 59796b8a054SScott Wood * Environment Configuration 59896b8a054SScott Wood */ 59996b8a054SScott Wood #define CONFIG_ENV_OVERWRITE 60096b8a054SScott Wood 601261c07bcSJoe Hershberger #define CONFIG_NETDEV "eth1" 60296b8a054SScott Wood 6035bc0543dSMario Six #define CONFIG_HOSTNAME "mpc8313erdb" 6048b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfs/root/path" 605b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 606261c07bcSJoe Hershberger /* U-Boot image on TFTP server */ 607261c07bcSJoe Hershberger #define CONFIG_UBOOTPATH "u-boot.bin" 608261c07bcSJoe Hershberger #define CONFIG_FDTFILE "mpc8313erdb.dtb" 60996b8a054SScott Wood 610261c07bcSJoe Hershberger /* default location for tftp and bootm */ 611261c07bcSJoe Hershberger #define CONFIG_LOADADDR 800000 61296b8a054SScott Wood 61396b8a054SScott Wood #define CONFIG_EXTRA_ENV_SETTINGS \ 614261c07bcSJoe Hershberger "netdev=" CONFIG_NETDEV "\0" \ 61596b8a054SScott Wood "ethprime=TSEC1\0" \ 616261c07bcSJoe Hershberger "uboot=" CONFIG_UBOOTPATH "\0" \ 61796b8a054SScott Wood "tftpflash=tftpboot $loadaddr $uboot; " \ 6185368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 6195368c55dSMarek Vasut " +$filesize; " \ 6205368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 6215368c55dSMarek Vasut " +$filesize; " \ 6225368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 6235368c55dSMarek Vasut " $filesize; " \ 6245368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 6255368c55dSMarek Vasut " +$filesize; " \ 6265368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 6275368c55dSMarek Vasut " $filesize\0" \ 62879f516bcSKim Phillips "fdtaddr=780000\0" \ 629261c07bcSJoe Hershberger "fdtfile=" CONFIG_FDTFILE "\0" \ 63096b8a054SScott Wood "console=ttyS0\0" \ 63196b8a054SScott Wood "setbootargs=setenv bootargs " \ 63296b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 63396b8a054SScott Wood "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 634261c07bcSJoe Hershberger "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 635261c07bcSJoe Hershberger "$netdev:off " \ 63696b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 63796b8a054SScott Wood 63896b8a054SScott Wood #define CONFIG_NFSBOOTCOMMAND \ 63996b8a054SScott Wood "setenv rootdev /dev/nfs;" \ 64096b8a054SScott Wood "run setbootargs;" \ 64196b8a054SScott Wood "run setipargs;" \ 64296b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 64396b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 64496b8a054SScott Wood "bootm $loadaddr - $fdtaddr" 64596b8a054SScott Wood 64696b8a054SScott Wood #define CONFIG_RAMBOOTCOMMAND \ 64796b8a054SScott Wood "setenv rootdev /dev/ram;" \ 64896b8a054SScott Wood "run setbootargs;" \ 64996b8a054SScott Wood "tftp $ramdiskaddr $ramdiskfile;" \ 65096b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 65196b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 65296b8a054SScott Wood "bootm $loadaddr $ramdiskaddr $fdtaddr" 65396b8a054SScott Wood 65496b8a054SScott Wood #endif /* __CONFIG_H */ 655