1*96b8a054SScott Wood /* 2*96b8a054SScott Wood * Copyright (C) Freescale Semiconductor, Inc. 2006. 3*96b8a054SScott Wood * 4*96b8a054SScott Wood * See file CREDITS for list of people who contributed to this 5*96b8a054SScott Wood * project. 6*96b8a054SScott Wood * 7*96b8a054SScott Wood * This program is free software; you can redistribute it and/or 8*96b8a054SScott Wood * modify it under the terms of the GNU General Public License as 9*96b8a054SScott Wood * published by the Free Software Foundation; either version 2 of 10*96b8a054SScott Wood * the License, or (at your option) any later version. 11*96b8a054SScott Wood * 12*96b8a054SScott Wood * This program is distributed in the hope that it will be useful, 13*96b8a054SScott Wood * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*96b8a054SScott Wood * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*96b8a054SScott Wood * GNU General Public License for more details. 16*96b8a054SScott Wood * 17*96b8a054SScott Wood * You should have received a copy of the GNU General Public License 18*96b8a054SScott Wood * along with this program; if not, write to the Free Software 19*96b8a054SScott Wood * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20*96b8a054SScott Wood * MA 02111-1307 USA 21*96b8a054SScott Wood * 22*96b8a054SScott Wood * History 23*96b8a054SScott Wood * 20061201: Wilson Lo (Wilson.Lo@freescale.com) 24*96b8a054SScott Wood * Initialized 25*96b8a054SScott Wood * 20061210: Tanya Jiang (tanya.jiang@freescale.com) 26*96b8a054SScott Wood * Code Cleanup 27*96b8a054SScott Wood * 20070410: Scott Wood <scottwood@freescale.com> 28*96b8a054SScott Wood * More cleanup 29*96b8a054SScott Wood */ 30*96b8a054SScott Wood /* 31*96b8a054SScott Wood * mpc8313epb board configuration file 32*96b8a054SScott Wood */ 33*96b8a054SScott Wood 34*96b8a054SScott Wood #ifndef __CONFIG_H 35*96b8a054SScott Wood #define __CONFIG_H 36*96b8a054SScott Wood 37*96b8a054SScott Wood /* 38*96b8a054SScott Wood * High Level Configuration Options 39*96b8a054SScott Wood */ 40*96b8a054SScott Wood #define CONFIG_E300 1 41*96b8a054SScott Wood #define CONFIG_MPC83XX 1 42*96b8a054SScott Wood #define CONFIG_MPC831X 1 43*96b8a054SScott Wood #define CONFIG_MPC8313 1 44*96b8a054SScott Wood #define CONFIG_MPC8313ERDB 1 45*96b8a054SScott Wood 46*96b8a054SScott Wood #define CONFIG_PCI 47*96b8a054SScott Wood #define CONFIG_83XX_GENERIC_PCI 48*96b8a054SScott Wood 49*96b8a054SScott Wood #ifdef CFG_66MHZ 50*96b8a054SScott Wood #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 51*96b8a054SScott Wood #elif defined(CFG_33MHZ) 52*96b8a054SScott Wood #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 53*96b8a054SScott Wood #else 54*96b8a054SScott Wood #error Unknown oscillator frequency. 55*96b8a054SScott Wood #endif 56*96b8a054SScott Wood 57*96b8a054SScott Wood #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 58*96b8a054SScott Wood 59*96b8a054SScott Wood #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 60*96b8a054SScott Wood 61*96b8a054SScott Wood #define CFG_IMMR 0xE0000000 62*96b8a054SScott Wood 63*96b8a054SScott Wood #define CFG_MEMTEST_START 0x00001000 64*96b8a054SScott Wood #define CFG_MEMTEST_END 0x07f00000 65*96b8a054SScott Wood 66*96b8a054SScott Wood /* Early revs of this board will lock up hard when attempting 67*96b8a054SScott Wood * to access the PMC registers, unless a JTAG debugger is 68*96b8a054SScott Wood * connected, or some resistor modifications are made. 69*96b8a054SScott Wood */ 70*96b8a054SScott Wood #define CFG_8313ERDB_BROKEN_PMC 1 71*96b8a054SScott Wood 72*96b8a054SScott Wood #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 73*96b8a054SScott Wood #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 74*96b8a054SScott Wood 75*96b8a054SScott Wood /* 76*96b8a054SScott Wood * DDR Setup 77*96b8a054SScott Wood */ 78*96b8a054SScott Wood #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 79*96b8a054SScott Wood #define CFG_SDRAM_BASE CFG_DDR_BASE 80*96b8a054SScott Wood #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 81*96b8a054SScott Wood 82*96b8a054SScott Wood /* 83*96b8a054SScott Wood * Manually set up DDR parameters, as this board does not 84*96b8a054SScott Wood * seem to have the SPD connected to I2C. 85*96b8a054SScott Wood */ 86*96b8a054SScott Wood #define CFG_DDR_SIZE 128 /* MB */ 87*96b8a054SScott Wood #define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP \ 88*96b8a054SScott Wood | 0x00040000 /* TODO */ \ 89*96b8a054SScott Wood | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) 90*96b8a054SScott Wood /* 0x80840102 */ 91*96b8a054SScott Wood 92*96b8a054SScott Wood #define CFG_DDR_TIMING_3 0x00000000 93*96b8a054SScott Wood #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 94*96b8a054SScott Wood | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 95*96b8a054SScott Wood | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 96*96b8a054SScott Wood | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 97*96b8a054SScott Wood | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 98*96b8a054SScott Wood | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 99*96b8a054SScott Wood | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 100*96b8a054SScott Wood | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 101*96b8a054SScott Wood /* 0x00220802 */ 102*96b8a054SScott Wood #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ 103*96b8a054SScott Wood | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 104*96b8a054SScott Wood | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ 105*96b8a054SScott Wood | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 106*96b8a054SScott Wood | (13 << TIMING_CFG1_REFREC_SHIFT ) \ 107*96b8a054SScott Wood | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ 108*96b8a054SScott Wood | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 109*96b8a054SScott Wood | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 110*96b8a054SScott Wood /* 0x3935d322 */ 111*96b8a054SScott Wood #define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 112*96b8a054SScott Wood | (31 << TIMING_CFG2_CPO_SHIFT ) \ 113*96b8a054SScott Wood | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 114*96b8a054SScott Wood | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 115*96b8a054SScott Wood | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 116*96b8a054SScott Wood | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 117*96b8a054SScott Wood | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 118*96b8a054SScott Wood /* 0x0f9048ca */ /* P9-45,may need tuning */ 119*96b8a054SScott Wood #define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 120*96b8a054SScott Wood | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 121*96b8a054SScott Wood /* 0x03200064 */ 122*96b8a054SScott Wood #if defined(CONFIG_DDR_2T_TIMING) 123*96b8a054SScott Wood #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ 124*96b8a054SScott Wood | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ 125*96b8a054SScott Wood | SDRAM_CFG_2T_EN \ 126*96b8a054SScott Wood | SDRAM_CFG_DBW_32 ) 127*96b8a054SScott Wood #else 128*96b8a054SScott Wood #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ 129*96b8a054SScott Wood | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ 130*96b8a054SScott Wood | SDRAM_CFG_32_BE ) 131*96b8a054SScott Wood /* 0x43080000 */ 132*96b8a054SScott Wood #endif 133*96b8a054SScott Wood #define CFG_SDRAM_CFG2 0x00401000; 134*96b8a054SScott Wood /* set burst length to 8 for 32-bit data path */ 135*96b8a054SScott Wood #define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \ 136*96b8a054SScott Wood | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) 137*96b8a054SScott Wood /* 0x44400232 */ 138*96b8a054SScott Wood #define CFG_DDR_MODE_2 0x8000C000; 139*96b8a054SScott Wood 140*96b8a054SScott Wood #define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 141*96b8a054SScott Wood /*0x02000000*/ 142*96b8a054SScott Wood #define CFG_DDRCDR_VALUE ( DDRCDR_EN \ 143*96b8a054SScott Wood | DDRCDR_PZ_NOMZ \ 144*96b8a054SScott Wood | DDRCDR_NZ_NOMZ \ 145*96b8a054SScott Wood | DDRCDR_M_ODR ) 146*96b8a054SScott Wood 147*96b8a054SScott Wood /* 148*96b8a054SScott Wood * FLASH on the Local Bus 149*96b8a054SScott Wood */ 150*96b8a054SScott Wood #define CFG_FLASH_CFI /* use the Common Flash Interface */ 151*96b8a054SScott Wood #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 152*96b8a054SScott Wood #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ 153*96b8a054SScott Wood #define CFG_FLASH_SIZE 8 /* flash size in MB */ 154*96b8a054SScott Wood #define CFG_FLASH_EMPTY_INFO /* display empty sectors */ 155*96b8a054SScott Wood #define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 156*96b8a054SScott Wood 157*96b8a054SScott Wood #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ 158*96b8a054SScott Wood (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 159*96b8a054SScott Wood BR_V) /* valid */ 160*96b8a054SScott Wood #define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \ 161*96b8a054SScott Wood | OR_GPCM_XACS \ 162*96b8a054SScott Wood | OR_GPCM_SCY_9 \ 163*96b8a054SScott Wood | OR_GPCM_EHTR \ 164*96b8a054SScott Wood | OR_GPCM_EAD ) 165*96b8a054SScott Wood /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 166*96b8a054SScott Wood #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ 167*96b8a054SScott Wood #define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ 168*96b8a054SScott Wood 169*96b8a054SScott Wood #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 170*96b8a054SScott Wood #define CFG_MAX_FLASH_SECT 135 /* sectors per device */ 171*96b8a054SScott Wood 172*96b8a054SScott Wood #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 173*96b8a054SScott Wood #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 174*96b8a054SScott Wood 175*96b8a054SScott Wood #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 176*96b8a054SScott Wood 177*96b8a054SScott Wood #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 178*96b8a054SScott Wood #define CFG_RAMBOOT 179*96b8a054SScott Wood #endif 180*96b8a054SScott Wood 181*96b8a054SScott Wood #define CFG_INIT_RAM_LOCK 1 182*96b8a054SScott Wood #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 183*96b8a054SScott Wood #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 184*96b8a054SScott Wood 185*96b8a054SScott Wood #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 186*96b8a054SScott Wood #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 187*96b8a054SScott Wood #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 188*96b8a054SScott Wood 189*96b8a054SScott Wood #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 190*96b8a054SScott Wood #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 191*96b8a054SScott Wood 192*96b8a054SScott Wood /* 193*96b8a054SScott Wood * Local Bus LCRR and LBCR regs 194*96b8a054SScott Wood */ 195*96b8a054SScott Wood #define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */ 196*96b8a054SScott Wood #define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ 197*96b8a054SScott Wood | (0xFF << LBCR_BMT_SHIFT) \ 198*96b8a054SScott Wood | 0xF ) /* 0x0004ff0f */ 199*96b8a054SScott Wood 200*96b8a054SScott Wood #define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ 201*96b8a054SScott Wood 202*96b8a054SScott Wood /* drivers/nand/nand.c */ 203*96b8a054SScott Wood #define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ 204*96b8a054SScott Wood #define CFG_MAX_NAND_DEVICE 1 205*96b8a054SScott Wood #define NAND_MAX_CHIPS 1 206*96b8a054SScott Wood #define CONFIG_MTD_NAND_VERIFY_WRITE 207*96b8a054SScott Wood 208*96b8a054SScott Wood #define CFG_BR1_PRELIM ( CFG_NAND_BASE \ 209*96b8a054SScott Wood | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 210*96b8a054SScott Wood | BR_PS_8 /* Port Size = 8 bit */ \ 211*96b8a054SScott Wood | BR_MS_FCM /* MSEL = FCM */ \ 212*96b8a054SScott Wood | BR_V ) /* valid */ 213*96b8a054SScott Wood #define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ 214*96b8a054SScott Wood | OR_FCM_CSCT \ 215*96b8a054SScott Wood | OR_FCM_CST \ 216*96b8a054SScott Wood | OR_FCM_CHT \ 217*96b8a054SScott Wood | OR_FCM_SCY_1 \ 218*96b8a054SScott Wood | OR_FCM_TRLX \ 219*96b8a054SScott Wood | OR_FCM_EHTR ) 220*96b8a054SScott Wood /* 0xFFFF8396 */ 221*96b8a054SScott Wood #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE 222*96b8a054SScott Wood #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 223*96b8a054SScott Wood 224*96b8a054SScott Wood #define CFG_VSC7385_BASE 0xF0000000 225*96b8a054SScott Wood 226*96b8a054SScott Wood #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 227*96b8a054SScott Wood #define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ 228*96b8a054SScott Wood #define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ 229*96b8a054SScott Wood #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */ 230*96b8a054SScott Wood #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ 231*96b8a054SScott Wood 232*96b8a054SScott Wood /* local bus read write buffer mapping */ 233*96b8a054SScott Wood #define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ 234*96b8a054SScott Wood #define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ 235*96b8a054SScott Wood #define CFG_LBLAWBAR3_PRELIM 0xFA000000 236*96b8a054SScott Wood #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 237*96b8a054SScott Wood 238*96b8a054SScott Wood /* pass open firmware flat tree */ 239*96b8a054SScott Wood #define CONFIG_OF_FLAT_TREE 1 240*96b8a054SScott Wood #define CONFIG_OF_BOARD_SETUP 1 241*96b8a054SScott Wood 242*96b8a054SScott Wood /* maximum size of the flat tree (8K) */ 243*96b8a054SScott Wood #define OF_FLAT_TREE_MAX_SIZE 8192 244*96b8a054SScott Wood 245*96b8a054SScott Wood #define OF_CPU "PowerPC,8313@0" 246*96b8a054SScott Wood #define OF_SOC "soc8313@e0000000" 247*96b8a054SScott Wood #define OF_TBCLK (bd->bi_busfreq / 4) 248*96b8a054SScott Wood #define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500" 249*96b8a054SScott Wood 250*96b8a054SScott Wood /* 251*96b8a054SScott Wood * Serial Port 252*96b8a054SScott Wood */ 253*96b8a054SScott Wood #define CONFIG_CONS_INDEX 1 254*96b8a054SScott Wood #define CFG_NS16550 255*96b8a054SScott Wood #define CFG_NS16550_SERIAL 256*96b8a054SScott Wood #define CFG_NS16550_REG_SIZE 1 257*96b8a054SScott Wood #define CFG_NS16550_CLK get_bus_freq(0) 258*96b8a054SScott Wood 259*96b8a054SScott Wood #define CFG_BAUDRATE_TABLE \ 260*96b8a054SScott Wood {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 261*96b8a054SScott Wood 262*96b8a054SScott Wood #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 263*96b8a054SScott Wood #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 264*96b8a054SScott Wood 265*96b8a054SScott Wood /* Use the HUSH parser */ 266*96b8a054SScott Wood #define CFG_HUSH_PARSER 267*96b8a054SScott Wood #define CFG_PROMPT_HUSH_PS2 "> " 268*96b8a054SScott Wood 269*96b8a054SScott Wood /* I2C */ 270*96b8a054SScott Wood #define CONFIG_HARD_I2C /* I2C with hardware support*/ 271*96b8a054SScott Wood #define CONFIG_FSL_I2C 272*96b8a054SScott Wood #define CONFIG_I2C_MULTI_BUS 273*96b8a054SScott Wood #define CONFIG_I2C_CMD_TREE 274*96b8a054SScott Wood #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 275*96b8a054SScott Wood #define CFG_I2C_SLAVE 0x7F 276*96b8a054SScott Wood #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 277*96b8a054SScott Wood #define CFG_I2C_OFFSET 0x3000 278*96b8a054SScott Wood #define CFG_I2C2_OFFSET 0x3100 279*96b8a054SScott Wood 280*96b8a054SScott Wood /* TSEC */ 281*96b8a054SScott Wood #define CFG_TSEC1_OFFSET 0x24000 282*96b8a054SScott Wood #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) 283*96b8a054SScott Wood #define CFG_TSEC2_OFFSET 0x25000 284*96b8a054SScott Wood #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) 285*96b8a054SScott Wood #define CONFIG_NET_MULTI 286*96b8a054SScott Wood 287*96b8a054SScott Wood /* 288*96b8a054SScott Wood * General PCI 289*96b8a054SScott Wood * Addresses are mapped 1-1. 290*96b8a054SScott Wood */ 291*96b8a054SScott Wood #define CFG_PCI1_MEM_BASE 0x80000000 292*96b8a054SScott Wood #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 293*96b8a054SScott Wood #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 294*96b8a054SScott Wood #define CFG_PCI1_MMIO_BASE 0x90000000 295*96b8a054SScott Wood #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 296*96b8a054SScott Wood #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 297*96b8a054SScott Wood #define CFG_PCI1_IO_BASE 0x00000000 298*96b8a054SScott Wood #define CFG_PCI1_IO_PHYS 0xE2000000 299*96b8a054SScott Wood #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 300*96b8a054SScott Wood 301*96b8a054SScott Wood #define CONFIG_PCI_PNP /* do pci plug-and-play */ 302*96b8a054SScott Wood #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 303*96b8a054SScott Wood 304*96b8a054SScott Wood /* 305*96b8a054SScott Wood * TSEC configuration 306*96b8a054SScott Wood */ 307*96b8a054SScott Wood #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 308*96b8a054SScott Wood 309*96b8a054SScott Wood #ifndef CONFIG_NET_MULTI 310*96b8a054SScott Wood #define CONFIG_NET_MULTI 1 311*96b8a054SScott Wood #endif 312*96b8a054SScott Wood 313*96b8a054SScott Wood #define CONFIG_GMII 1 /* MII PHY management */ 314*96b8a054SScott Wood #define CONFIG_MPC83XX_TSEC1 1 315*96b8a054SScott Wood 316*96b8a054SScott Wood #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" 317*96b8a054SScott Wood #define CONFIG_MPC83XX_TSEC2 1 318*96b8a054SScott Wood #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" 319*96b8a054SScott Wood #define TSEC1_PHY_ADDR 0x1c 320*96b8a054SScott Wood #define TSEC2_PHY_ADDR 4 321*96b8a054SScott Wood #define TSEC1_PHYIDX 0 322*96b8a054SScott Wood #define TSEC2_PHYIDX 0 323*96b8a054SScott Wood 324*96b8a054SScott Wood /* Options are: TSEC[0-1] */ 325*96b8a054SScott Wood #define CONFIG_ETHPRIME "TSEC1" 326*96b8a054SScott Wood 327*96b8a054SScott Wood /* 328*96b8a054SScott Wood * Configure on-board RTC 329*96b8a054SScott Wood */ 330*96b8a054SScott Wood #define CONFIG_RTC_DS1337 331*96b8a054SScott Wood #define CFG_I2C_RTC_ADDR 0x68 332*96b8a054SScott Wood 333*96b8a054SScott Wood /* 334*96b8a054SScott Wood * Environment 335*96b8a054SScott Wood */ 336*96b8a054SScott Wood #ifndef CFG_RAMBOOT 337*96b8a054SScott Wood #define CFG_ENV_IS_IN_FLASH 1 338*96b8a054SScott Wood #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 339*96b8a054SScott Wood #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 340*96b8a054SScott Wood #define CFG_ENV_SIZE 0x2000 341*96b8a054SScott Wood 342*96b8a054SScott Wood /* Address and size of Redundant Environment Sector */ 343*96b8a054SScott Wood #else 344*96b8a054SScott Wood #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 345*96b8a054SScott Wood #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 346*96b8a054SScott Wood #define CFG_ENV_SIZE 0x2000 347*96b8a054SScott Wood #endif 348*96b8a054SScott Wood 349*96b8a054SScott Wood #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 350*96b8a054SScott Wood #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 351*96b8a054SScott Wood 352*96b8a054SScott Wood #define CFG_BASE_COMMANDS ( CONFIG_CMD_DFL \ 353*96b8a054SScott Wood | CFG_CMD_PING \ 354*96b8a054SScott Wood | CFG_CMD_DHCP \ 355*96b8a054SScott Wood | CFG_CMD_I2C \ 356*96b8a054SScott Wood | CFG_CMD_MII \ 357*96b8a054SScott Wood | CFG_CMD_DATE \ 358*96b8a054SScott Wood | CFG_CMD_PCI) 359*96b8a054SScott Wood 360*96b8a054SScott Wood #define CONFIG_CMDLINE_EDITING 1 361*96b8a054SScott Wood 362*96b8a054SScott Wood #define CFG_RAMBOOT_COMMANDS (CFG_BASE_COMMANDS & \ 363*96b8a054SScott Wood ~(CFG_CMD_ENV | CFG_CMD_LOADS)) 364*96b8a054SScott Wood 365*96b8a054SScott Wood #if defined(CFG_RAMBOOT) 366*96b8a054SScott Wood #define CONFIG_COMMANDS CFG_RAMBOOT_COMMANDS 367*96b8a054SScott Wood #else 368*96b8a054SScott Wood #define CONFIG_COMMANDS CFG_BASE_COMMANDS 369*96b8a054SScott Wood #endif 370*96b8a054SScott Wood 371*96b8a054SScott Wood #include <cmd_confdefs.h> 372*96b8a054SScott Wood 373*96b8a054SScott Wood /* 374*96b8a054SScott Wood * Miscellaneous configurable options 375*96b8a054SScott Wood */ 376*96b8a054SScott Wood #define CFG_LONGHELP /* undef to save memory */ 377*96b8a054SScott Wood #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 378*96b8a054SScott Wood #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 379*96b8a054SScott Wood #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 380*96b8a054SScott Wood 381*96b8a054SScott Wood #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 382*96b8a054SScott Wood #define CFG_MAXARGS 16 /* max number of command args */ 383*96b8a054SScott Wood #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 384*96b8a054SScott Wood #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 385*96b8a054SScott Wood 386*96b8a054SScott Wood /* 387*96b8a054SScott Wood * For booting Linux, the board info and command line data 388*96b8a054SScott Wood * have to be in the first 8 MB of memory, since this is 389*96b8a054SScott Wood * the maximum mapped by the Linux kernel during initialization. 390*96b8a054SScott Wood */ 391*96b8a054SScott Wood #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 392*96b8a054SScott Wood 393*96b8a054SScott Wood /* Cache Configuration */ 394*96b8a054SScott Wood #define CFG_DCACHE_SIZE 16384 395*96b8a054SScott Wood #define CFG_CACHELINE_SIZE 32 396*96b8a054SScott Wood #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 397*96b8a054SScott Wood 398*96b8a054SScott Wood #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 399*96b8a054SScott Wood 400*96b8a054SScott Wood #ifdef CFG_66MHZ 401*96b8a054SScott Wood 402*96b8a054SScott Wood /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 403*96b8a054SScott Wood /* 0x62040000 */ 404*96b8a054SScott Wood #define CFG_HRCW_LOW (\ 405*96b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 406*96b8a054SScott Wood HRCWL_DDRCM |\ 407*96b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 408*96b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 409*96b8a054SScott Wood HRCWL_CSB_TO_CLKIN_2X1 |\ 410*96b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 411*96b8a054SScott Wood 412*96b8a054SScott Wood #elif defined(CFG_33MHZ) 413*96b8a054SScott Wood 414*96b8a054SScott Wood /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 415*96b8a054SScott Wood /* 0x65040000 */ 416*96b8a054SScott Wood #define CFG_HRCW_LOW (\ 417*96b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 418*96b8a054SScott Wood HRCWL_DDRCM |\ 419*96b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 420*96b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 421*96b8a054SScott Wood HRCWL_CSB_TO_CLKIN_5X1 |\ 422*96b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 423*96b8a054SScott Wood 424*96b8a054SScott Wood #endif 425*96b8a054SScott Wood 426*96b8a054SScott Wood /* 0xa0606c00 */ 427*96b8a054SScott Wood #define CFG_HRCW_HIGH (\ 428*96b8a054SScott Wood HRCWH_PCI_HOST |\ 429*96b8a054SScott Wood HRCWH_PCI1_ARBITER_ENABLE |\ 430*96b8a054SScott Wood HRCWH_CORE_ENABLE |\ 431*96b8a054SScott Wood HRCWH_FROM_0X00000100 |\ 432*96b8a054SScott Wood HRCWH_BOOTSEQ_DISABLE |\ 433*96b8a054SScott Wood HRCWH_SW_WATCHDOG_DISABLE |\ 434*96b8a054SScott Wood HRCWH_ROM_LOC_LOCAL_16BIT |\ 435*96b8a054SScott Wood HRCWH_RL_EXT_LEGACY |\ 436*96b8a054SScott Wood HRCWH_TSEC1M_IN_RGMII |\ 437*96b8a054SScott Wood HRCWH_TSEC2M_IN_RGMII |\ 438*96b8a054SScott Wood HRCWH_BIG_ENDIAN |\ 439*96b8a054SScott Wood HRCWH_LALE_NORMAL) 440*96b8a054SScott Wood 441*96b8a054SScott Wood /* System IO Config */ 442*96b8a054SScott Wood #define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 443*96b8a054SScott Wood #define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ 444*96b8a054SScott Wood 445*96b8a054SScott Wood #define CFG_HID0_INIT 0x000000000 446*96b8a054SScott Wood #define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 447*96b8a054SScott Wood HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 448*96b8a054SScott Wood 449*96b8a054SScott Wood #define CFG_HID2 HID2_HBE 450*96b8a054SScott Wood 451*96b8a054SScott Wood /* DDR @ 0x00000000 */ 452*96b8a054SScott Wood #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) 453*96b8a054SScott Wood #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 454*96b8a054SScott Wood 455*96b8a054SScott Wood /* PCI @ 0x80000000 */ 456*96b8a054SScott Wood #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10) 457*96b8a054SScott Wood #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 458*96b8a054SScott Wood #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 459*96b8a054SScott Wood #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 460*96b8a054SScott Wood 461*96b8a054SScott Wood /* PCI2 not supported on 8313 */ 462*96b8a054SScott Wood #define CFG_IBAT3L (0) 463*96b8a054SScott Wood #define CFG_IBAT3U (0) 464*96b8a054SScott Wood #define CFG_IBAT4L (0) 465*96b8a054SScott Wood #define CFG_IBAT4U (0) 466*96b8a054SScott Wood 467*96b8a054SScott Wood /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 468*96b8a054SScott Wood #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 469*96b8a054SScott Wood #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 470*96b8a054SScott Wood 471*96b8a054SScott Wood /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 472*96b8a054SScott Wood #define CFG_IBAT6L (0xF0000000 | BATL_PP_10) 473*96b8a054SScott Wood #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 474*96b8a054SScott Wood 475*96b8a054SScott Wood #define CFG_IBAT7L (0) 476*96b8a054SScott Wood #define CFG_IBAT7U (0) 477*96b8a054SScott Wood 478*96b8a054SScott Wood #define CFG_DBAT0L CFG_IBAT0L 479*96b8a054SScott Wood #define CFG_DBAT0U CFG_IBAT0U 480*96b8a054SScott Wood #define CFG_DBAT1L CFG_IBAT1L 481*96b8a054SScott Wood #define CFG_DBAT1U CFG_IBAT1U 482*96b8a054SScott Wood #define CFG_DBAT2L CFG_IBAT2L 483*96b8a054SScott Wood #define CFG_DBAT2U CFG_IBAT2U 484*96b8a054SScott Wood #define CFG_DBAT3L CFG_IBAT3L 485*96b8a054SScott Wood #define CFG_DBAT3U CFG_IBAT3U 486*96b8a054SScott Wood #define CFG_DBAT4L CFG_IBAT4L 487*96b8a054SScott Wood #define CFG_DBAT4U CFG_IBAT4U 488*96b8a054SScott Wood #define CFG_DBAT5L CFG_IBAT5L 489*96b8a054SScott Wood #define CFG_DBAT5U CFG_IBAT5U 490*96b8a054SScott Wood #define CFG_DBAT6L CFG_IBAT6L 491*96b8a054SScott Wood #define CFG_DBAT6U CFG_IBAT6U 492*96b8a054SScott Wood #define CFG_DBAT7L CFG_IBAT7L 493*96b8a054SScott Wood #define CFG_DBAT7U CFG_IBAT7U 494*96b8a054SScott Wood 495*96b8a054SScott Wood /* 496*96b8a054SScott Wood * Internal Definitions 497*96b8a054SScott Wood * 498*96b8a054SScott Wood * Boot Flags 499*96b8a054SScott Wood */ 500*96b8a054SScott Wood #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 501*96b8a054SScott Wood #define BOOTFLAG_WARM 0x02 /* Software reboot */ 502*96b8a054SScott Wood 503*96b8a054SScott Wood /* 504*96b8a054SScott Wood * Environment Configuration 505*96b8a054SScott Wood */ 506*96b8a054SScott Wood #define CONFIG_ENV_OVERWRITE 507*96b8a054SScott Wood 508*96b8a054SScott Wood #define CONFIG_ETHADDR 00:E0:0C:00:95:01 509*96b8a054SScott Wood #define CONFIG_HAS_ETH1 510*96b8a054SScott Wood #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 511*96b8a054SScott Wood 512*96b8a054SScott Wood #define CONFIG_IPADDR 10.0.0.2 513*96b8a054SScott Wood #define CONFIG_SERVERIP 10.0.0.1 514*96b8a054SScott Wood #define CONFIG_GATEWAYIP 10.0.0.1 515*96b8a054SScott Wood #define CONFIG_NETMASK 255.0.0.0 516*96b8a054SScott Wood #define CONFIG_NETDEV eth1 517*96b8a054SScott Wood 518*96b8a054SScott Wood #define CONFIG_HOSTNAME mpc8313erdb 519*96b8a054SScott Wood #define CONFIG_ROOTPATH /nfs/root/path 520*96b8a054SScott Wood #define CONFIG_BOOTFILE uImage 521*96b8a054SScott Wood #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 522*96b8a054SScott Wood #define CONFIG_FDTFILE mpc8313erdb.dtb 523*96b8a054SScott Wood 524*96b8a054SScott Wood #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 525*96b8a054SScott Wood #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 526*96b8a054SScott Wood #define CONFIG_BAUDRATE 115200 527*96b8a054SScott Wood 528*96b8a054SScott Wood #define XMK_STR(x) #x 529*96b8a054SScott Wood #define MK_STR(x) XMK_STR(x) 530*96b8a054SScott Wood 531*96b8a054SScott Wood #define CONFIG_EXTRA_ENV_SETTINGS \ 532*96b8a054SScott Wood "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 533*96b8a054SScott Wood "ethprime=TSEC1\0" \ 534*96b8a054SScott Wood "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 535*96b8a054SScott Wood "tftpflash=tftpboot $loadaddr $uboot; " \ 536*96b8a054SScott Wood "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 537*96b8a054SScott Wood "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 538*96b8a054SScott Wood "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 539*96b8a054SScott Wood "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 540*96b8a054SScott Wood "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 541*96b8a054SScott Wood "fdtaddr=400000\0" \ 542*96b8a054SScott Wood "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 543*96b8a054SScott Wood "console=ttyS0\0" \ 544*96b8a054SScott Wood "setbootargs=setenv bootargs " \ 545*96b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 546*96b8a054SScott Wood "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 547*96b8a054SScott Wood "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 548*96b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 549*96b8a054SScott Wood 550*96b8a054SScott Wood #define CONFIG_NFSBOOTCOMMAND \ 551*96b8a054SScott Wood "setenv rootdev /dev/nfs;" \ 552*96b8a054SScott Wood "run setbootargs;" \ 553*96b8a054SScott Wood "run setipargs;" \ 554*96b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 555*96b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 556*96b8a054SScott Wood "bootm $loadaddr - $fdtaddr" 557*96b8a054SScott Wood 558*96b8a054SScott Wood #define CONFIG_RAMBOOTCOMMAND \ 559*96b8a054SScott Wood "setenv rootdev /dev/ram;" \ 560*96b8a054SScott Wood "run setbootargs;" \ 561*96b8a054SScott Wood "tftp $ramdiskaddr $ramdiskfile;" \ 562*96b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 563*96b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 564*96b8a054SScott Wood "bootm $loadaddr $ramdiskaddr $fdtaddr" 565*96b8a054SScott Wood 566*96b8a054SScott Wood #undef MK_STR 567*96b8a054SScott Wood #undef XMK_STR 568*96b8a054SScott Wood 569*96b8a054SScott Wood #endif /* __CONFIG_H */ 570