196b8a054SScott Wood /* 2e8d3ca8bSScott Wood * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 396b8a054SScott Wood * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 596b8a054SScott Wood */ 696b8a054SScott Wood /* 796b8a054SScott Wood * mpc8313epb board configuration file 896b8a054SScott Wood */ 996b8a054SScott Wood 1096b8a054SScott Wood #ifndef __CONFIG_H 1196b8a054SScott Wood #define __CONFIG_H 1296b8a054SScott Wood 13fdfaa29eSKim Phillips #define CONFIG_DISPLAY_BOARDINFO 14fdfaa29eSKim Phillips 1596b8a054SScott Wood /* 1696b8a054SScott Wood * High Level Configuration Options 1796b8a054SScott Wood */ 1896b8a054SScott Wood #define CONFIG_E300 1 192c7920afSPeter Tyser #define CONFIG_MPC831x 1 2096b8a054SScott Wood #define CONFIG_MPC8313 1 2196b8a054SScott Wood #define CONFIG_MPC8313ERDB 1 2296b8a054SScott Wood 2322f4442dSScott Wood #ifdef CONFIG_NAND 2422f4442dSScott Wood #define CONFIG_SPL_INIT_MINIMAL 2522f4442dSScott Wood #define CONFIG_SPL_SERIAL_SUPPORT 2622f4442dSScott Wood #define CONFIG_SPL_NAND_SUPPORT 2722f4442dSScott Wood #define CONFIG_SPL_FLUSH_IMAGE 2822f4442dSScott Wood #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 2922f4442dSScott Wood #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 3022f4442dSScott Wood 3122f4442dSScott Wood #ifdef CONFIG_SPL_BUILD 3222f4442dSScott Wood #define CONFIG_NS16550_MIN_FUNCTIONS 3322f4442dSScott Wood #endif 3422f4442dSScott Wood 3522f4442dSScott Wood #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 3622f4442dSScott Wood #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 3722f4442dSScott Wood #define CONFIG_SPL_MAX_SIZE (4 * 1024) 386113d3f2SBenoît Thébaudeau #define CONFIG_SPL_PAD_TO 0x4000 3922f4442dSScott Wood 40f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 41f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 42f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 43f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 44f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 45f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 46f1c574d4SScott Wood 4722f4442dSScott Wood #ifdef CONFIG_SPL_BUILD 48f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 4922f4442dSScott Wood #endif 5022f4442dSScott Wood 5122f4442dSScott Wood #endif /* CONFIG_NAND */ 52f1c574d4SScott Wood 532ae18241SWolfgang Denk #ifndef CONFIG_SYS_TEXT_BASE 542ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFE000000 552ae18241SWolfgang Denk #endif 562ae18241SWolfgang Denk 57f1c574d4SScott Wood #ifndef CONFIG_SYS_MONITOR_BASE 58f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 59f1c574d4SScott Wood #endif 60f1c574d4SScott Wood 6196b8a054SScott Wood #define CONFIG_PCI 62842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 630914f483SBecky Bruce #define CONFIG_FSL_ELBC 1 6496b8a054SScott Wood 6589c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 6689c7784eSTimur Tabi 6789c7784eSTimur Tabi /* 6889c7784eSTimur Tabi * On-board devices 694ce1e23bSYork Sun * 704ce1e23bSYork Sun * TSEC1 is VSC switch 714ce1e23bSYork Sun * TSEC2 is SoC TSEC 7289c7784eSTimur Tabi */ 7389c7784eSTimur Tabi #define CONFIG_VSC7385_ENET 744ce1e23bSYork Sun #define CONFIG_TSEC2 7589c7784eSTimur Tabi 766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 775c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 795c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 8096b8a054SScott Wood #else 8196b8a054SScott Wood #error Unknown oscillator frequency. 8296b8a054SScott Wood #endif 8396b8a054SScott Wood 8496b8a054SScott Wood #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 8596b8a054SScott Wood 860eaf8f9eSJoe Hershberger #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ 870eaf8f9eSJoe Hershberger #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */ 8896b8a054SScott Wood 896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 9096b8a054SScott Wood 9122f4442dSScott Wood #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) 926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 93e4c09508SScott Wood #endif 94e4c09508SScott Wood 956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00001000 966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x07f00000 9796b8a054SScott Wood 9896b8a054SScott Wood /* Early revs of this board will lock up hard when attempting 9996b8a054SScott Wood * to access the PMC registers, unless a JTAG debugger is 10096b8a054SScott Wood * connected, or some resistor modifications are made. 10196b8a054SScott Wood */ 1026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 10396b8a054SScott Wood 1046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 10696b8a054SScott Wood 10796b8a054SScott Wood /* 10889c7784eSTimur Tabi * Device configurations 10989c7784eSTimur Tabi */ 11089c7784eSTimur Tabi 11189c7784eSTimur Tabi /* Vitesse 7385 */ 11289c7784eSTimur Tabi 11389c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 11489c7784eSTimur Tabi 1154ce1e23bSYork Sun #define CONFIG_TSEC1 11689c7784eSTimur Tabi 11789c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 11889c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFE7FE000 11989c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 12089c7784eSTimur Tabi 12189c7784eSTimur Tabi #endif 12289c7784eSTimur Tabi 12389c7784eSTimur Tabi /* 12496b8a054SScott Wood * DDR Setup 12596b8a054SScott Wood */ 1266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 12996b8a054SScott Wood 13096b8a054SScott Wood /* 13196b8a054SScott Wood * Manually set up DDR parameters, as this board does not 13296b8a054SScott Wood * seem to have the SPD connected to I2C. 13396b8a054SScott Wood */ 1346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 1352e651b24SJoe Hershberger #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 1362fef4020SJoe Hershberger | CSCONFIG_ODT_RD_NEVER \ 1372fef4020SJoe Hershberger | CSCONFIG_ODT_WR_ONLY_CURRENT \ 138261c07bcSJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 139261c07bcSJoe Hershberger | CSCONFIG_COL_BIT_10) 140e1d8ed2cSPoonam Aggrwal /* 0x80010102 */ 14196b8a054SScott Wood 1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_3 0x00000000 1436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 14496b8a054SScott Wood | (0 << TIMING_CFG0_WRT_SHIFT) \ 14596b8a054SScott Wood | (0 << TIMING_CFG0_RRT_SHIFT) \ 14696b8a054SScott Wood | (0 << TIMING_CFG0_WWT_SHIFT) \ 14796b8a054SScott Wood | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 14896b8a054SScott Wood | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 14996b8a054SScott Wood | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 15096b8a054SScott Wood | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 15196b8a054SScott Wood /* 0x00220802 */ 1526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 153e1d8ed2cSPoonam Aggrwal | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 15496b8a054SScott Wood | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 15596b8a054SScott Wood | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 156e1d8ed2cSPoonam Aggrwal | (10 << TIMING_CFG1_REFREC_SHIFT) \ 15796b8a054SScott Wood | (3 << TIMING_CFG1_WRREC_SHIFT) \ 15896b8a054SScott Wood | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 15996b8a054SScott Wood | (2 << TIMING_CFG1_WRTORD_SHIFT)) 160e1d8ed2cSPoonam Aggrwal /* 0x3835a322 */ 1616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 162e1d8ed2cSPoonam Aggrwal | (5 << TIMING_CFG2_CPO_SHIFT) \ 16396b8a054SScott Wood | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 16496b8a054SScott Wood | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 16596b8a054SScott Wood | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 16696b8a054SScott Wood | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 167e1d8ed2cSPoonam Aggrwal | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 168e1d8ed2cSPoonam Aggrwal /* 0x129048c6 */ /* P9-45,may need tuning */ 1696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 170e1d8ed2cSPoonam Aggrwal | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 171e1d8ed2cSPoonam Aggrwal /* 0x05100500 */ 17296b8a054SScott Wood #if defined(CONFIG_DDR_2T_TIMING) 1736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 174bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1752fef4020SJoe Hershberger | SDRAM_CFG_DBW_32 \ 1762fef4020SJoe Hershberger | SDRAM_CFG_2T_EN) 1772fef4020SJoe Hershberger /* 0x43088000 */ 17896b8a054SScott Wood #else 1796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 180bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1812fef4020SJoe Hershberger | SDRAM_CFG_DBW_32) 18296b8a054SScott Wood /* 0x43080000 */ 18396b8a054SScott Wood #endif 1846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG2 0x00401000 18596b8a054SScott Wood /* set burst length to 8 for 32-bit data path */ 1866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 187e1d8ed2cSPoonam Aggrwal | (0x0632 << SDRAM_MODE_SD_SHIFT)) 188e1d8ed2cSPoonam Aggrwal /* 0x44480632 */ 1896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x8000C000 19096b8a054SScott Wood 1916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 19296b8a054SScott Wood /*0x02000000*/ 1936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 19496b8a054SScott Wood | DDRCDR_PZ_NOMZ \ 19596b8a054SScott Wood | DDRCDR_NZ_NOMZ \ 19696b8a054SScott Wood | DDRCDR_M_ODR) 19796b8a054SScott Wood 19896b8a054SScott Wood /* 19996b8a054SScott Wood * FLASH on the Local Bus 20096b8a054SScott Wood */ 2016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 20200b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 2036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 2046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 2076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 20896b8a054SScott Wood 209261c07bcSJoe Hershberger #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 2107d6a0982SJoe Hershberger | BR_PS_16 /* 16 bit port */ \ 2117d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 212261c07bcSJoe Hershberger | BR_V) /* valid */ 2137d6a0982SJoe Hershberger #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 21496b8a054SScott Wood | OR_GPCM_XACS \ 21596b8a054SScott Wood | OR_GPCM_SCY_9 \ 21696b8a054SScott Wood | OR_GPCM_EHTR \ 21796b8a054SScott Wood | OR_GPCM_EAD) 21896b8a054SScott Wood /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 219261c07bcSJoe Hershberger /* window base at flash base */ 220261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2217d6a0982SJoe Hershberger /* 16 MB window size */ 2227d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 22396b8a054SScott Wood 2246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 2256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 22696b8a054SScott Wood 2276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 22996b8a054SScott Wood 230261c07bcSJoe Hershberger #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 23122f4442dSScott Wood !defined(CONFIG_SPL_BUILD) 2326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 23396b8a054SScott Wood #endif 23496b8a054SScott Wood 2356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 236261c07bcSJoe Hershberger #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 237553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 23896b8a054SScott Wood 239261c07bcSJoe Hershberger #define CONFIG_SYS_GBL_DATA_OFFSET \ 240261c07bcSJoe Hershberger (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 24296b8a054SScott Wood 2436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 24416c8c170SKevin Hao #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 2456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 24696b8a054SScott Wood 24796b8a054SScott Wood /* 24896b8a054SScott Wood * Local Bus LCRR and LBCR regs 24996b8a054SScott Wood */ 250c7190f02SKim Phillips #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 251c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 2526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 25396b8a054SScott Wood | (0xFF << LBCR_BMT_SHIFT) \ 25496b8a054SScott Wood | 0xF) /* 0x0004ff0f */ 25596b8a054SScott Wood 256261c07bcSJoe Hershberger /* LB refresh timer prescal, 266MHz/32 */ 257261c07bcSJoe Hershberger #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 25896b8a054SScott Wood 2597817cb20SMarcel Ziswiler /* drivers/mtd/nand/nand.c */ 26022f4442dSScott Wood #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) 2616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xFFF00000 262e4c09508SScott Wood #else 2636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xE2800000 264e4c09508SScott Wood #endif 265e4c09508SScott Wood 266e8d3ca8bSScott Wood #define CONFIG_MTD_DEVICE 267e8d3ca8bSScott Wood #define CONFIG_MTD_PARTITION 268e8d3ca8bSScott Wood #define CONFIG_CMD_MTDPARTS 269e8d3ca8bSScott Wood #define MTDIDS_DEFAULT "nand0=e2800000.flash" 270e8d3ca8bSScott Wood #define MTDPARTS_DEFAULT \ 271*63865278SKevin Hao "mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" 272e8d3ca8bSScott Wood 2736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_NAND_DEVICE 1 274acdab5c3SScott Wood #define CONFIG_CMD_NAND 1 275acdab5c3SScott Wood #define CONFIG_NAND_FSL_ELBC 1 2766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 2777d6a0982SJoe Hershberger #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 27896b8a054SScott Wood 2796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 2807d6a0982SJoe Hershberger | BR_DECC_CHK_GEN /* Use HW ECC */ \ 281261c07bcSJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 28296b8a054SScott Wood | BR_MS_FCM /* MSEL = FCM */ \ 28396b8a054SScott Wood | BR_V) /* valid */ 2847d6a0982SJoe Hershberger #define CONFIG_SYS_NAND_OR_PRELIM \ 2857d6a0982SJoe Hershberger (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 28696b8a054SScott Wood | OR_FCM_CSCT \ 28796b8a054SScott Wood | OR_FCM_CST \ 28896b8a054SScott Wood | OR_FCM_CHT \ 28996b8a054SScott Wood | OR_FCM_SCY_1 \ 29096b8a054SScott Wood | OR_FCM_TRLX \ 29196b8a054SScott Wood | OR_FCM_EHTR) 29296b8a054SScott Wood /* 0xFFFF8396 */ 293e4c09508SScott Wood 29422f4442dSScott Wood #ifdef CONFIG_NAND 2956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 2976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 299e4c09508SScott Wood #else 3006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 3016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 3026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 3036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 304e4c09508SScott Wood #endif 305e4c09508SScott Wood 3066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 3077d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 30896b8a054SScott Wood 3096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 3106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 311e4c09508SScott Wood 3127d6a0982SJoe Hershberger /* local bus write LED / read status buffer (BCSR) mapping */ 3137d6a0982SJoe Hershberger #define CONFIG_SYS_BCSR_ADDR 0xFA000000 3147d6a0982SJoe Hershberger #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 3157d6a0982SJoe Hershberger /* map at 0xFA000000 on LCS3 */ 3167d6a0982SJoe Hershberger #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 3177d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 3187d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 3197d6a0982SJoe Hershberger | BR_V) /* valid */ 3207d6a0982SJoe Hershberger /* 0xFA000801 */ 3217d6a0982SJoe Hershberger #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 3227d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 3237d6a0982SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 3247d6a0982SJoe Hershberger | OR_GPCM_XACS \ 3257d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 3267d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 3277d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 3287d6a0982SJoe Hershberger | OR_GPCM_EAD) 3297d6a0982SJoe Hershberger /* 0xFFFF8FF7 */ 3307d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 3317d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 33296b8a054SScott Wood 33389c7784eSTimur Tabi /* Vitesse 7385 */ 33489c7784eSTimur Tabi 33589c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 33689c7784eSTimur Tabi 3377d6a0982SJoe Hershberger /* VSC7385 Base address on LCS2 */ 3387d6a0982SJoe Hershberger #define CONFIG_SYS_VSC7385_BASE 0xF0000000 3397d6a0982SJoe Hershberger #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 3407d6a0982SJoe Hershberger 3417d6a0982SJoe Hershberger #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 3427d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 3437d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 3447d6a0982SJoe Hershberger | BR_V) /* valid */ 3457d6a0982SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 3467d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 3477d6a0982SJoe Hershberger | OR_GPCM_XACS \ 3487d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 3497d6a0982SJoe Hershberger | OR_GPCM_SETA \ 3507d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 3517d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 3527d6a0982SJoe Hershberger | OR_GPCM_EAD) 3537d6a0982SJoe Hershberger /* 0xFFFE09FF */ 3547d6a0982SJoe Hershberger 355261c07bcSJoe Hershberger /* Access window base at VSC7385 base */ 356261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 3577d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 35889c7784eSTimur Tabi 35989c7784eSTimur Tabi #endif 36089c7784eSTimur Tabi 3610eaf8f9eSJoe Hershberger #define CONFIG_MPC83XX_GPIO 1 3620eaf8f9eSJoe Hershberger 36396b8a054SScott Wood /* 36496b8a054SScott Wood * Serial Port 36596b8a054SScott Wood */ 36696b8a054SScott Wood #define CONFIG_CONS_INDEX 1 3676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 36996b8a054SScott Wood 3706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 37196b8a054SScott Wood {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 37296b8a054SScott Wood 3736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 3746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 37596b8a054SScott Wood 37696b8a054SScott Wood /* I2C */ 37700f792e0SHeiko Schocher #define CONFIG_SYS_I2C 37800f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 37900f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 38000f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 38100f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 38200f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 400000 38300f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 38400f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 38500f792e0SHeiko Schocher #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 38696b8a054SScott Wood 38796b8a054SScott Wood /* 38896b8a054SScott Wood * General PCI 38996b8a054SScott Wood * Addresses are mapped 1-1. 39096b8a054SScott Wood */ 3916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 3936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 3946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 3956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 3966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 3986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 3996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 40096b8a054SScott Wood 40196b8a054SScott Wood #define CONFIG_PCI_PNP /* do pci plug-and-play */ 4026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 40396b8a054SScott Wood 40496b8a054SScott Wood /* 40589c7784eSTimur Tabi * TSEC 40696b8a054SScott Wood */ 40796b8a054SScott Wood #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 40896b8a054SScott Wood 40989c7784eSTimur Tabi #define CONFIG_GMII /* MII PHY management */ 41089c7784eSTimur Tabi 41189c7784eSTimur Tabi #ifdef CONFIG_TSEC1 41289c7784eSTimur Tabi #define CONFIG_HAS_ETH0 41389c7784eSTimur Tabi #define CONFIG_TSEC1_NAME "TSEC0" 4146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 41589c7784eSTimur Tabi #define TSEC1_PHY_ADDR 0x1c 41689c7784eSTimur Tabi #define TSEC1_FLAGS TSEC_GIGABIT 41789c7784eSTimur Tabi #define TSEC1_PHYIDX 0 41896b8a054SScott Wood #endif 41996b8a054SScott Wood 42089c7784eSTimur Tabi #ifdef CONFIG_TSEC2 42189c7784eSTimur Tabi #define CONFIG_HAS_ETH1 422255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 4236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 42496b8a054SScott Wood #define TSEC2_PHY_ADDR 4 4253a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 42696b8a054SScott Wood #define TSEC2_PHYIDX 0 42789c7784eSTimur Tabi #endif 42889c7784eSTimur Tabi 42996b8a054SScott Wood /* Options are: TSEC[0-1] */ 43096b8a054SScott Wood #define CONFIG_ETHPRIME "TSEC1" 43196b8a054SScott Wood 43296b8a054SScott Wood /* 43396b8a054SScott Wood * Configure on-board RTC 43496b8a054SScott Wood */ 43596b8a054SScott Wood #define CONFIG_RTC_DS1337 4366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 43796b8a054SScott Wood 43896b8a054SScott Wood /* 43996b8a054SScott Wood * Environment 44096b8a054SScott Wood */ 44122f4442dSScott Wood #if defined(CONFIG_NAND) 44251bfee19SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_NAND 1 4430e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET (512 * 1024) 4446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 4450e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 4460e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 4470e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 448261c07bcSJoe Hershberger #define CONFIG_ENV_OFFSET_REDUND \ 449261c07bcSJoe Hershberger (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 4506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif !defined(CONFIG_SYS_RAMBOOT) 4515a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 452261c07bcSJoe Hershberger #define CONFIG_ENV_ADDR \ 453261c07bcSJoe Hershberger (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4540e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 4550e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 45696b8a054SScott Wood 45796b8a054SScott Wood /* Address and size of Redundant Environment Sector */ 45896b8a054SScott Wood #else 45993f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 4606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4610e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 46296b8a054SScott Wood #endif 46396b8a054SScott Wood 46496b8a054SScott Wood #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 4656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 46696b8a054SScott Wood 4678ea5499aSJon Loeliger /* 468079a136cSJon Loeliger * BOOTP options 469079a136cSJon Loeliger */ 470079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 471079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTPATH 472079a136cSJon Loeliger #define CONFIG_BOOTP_GATEWAY 473079a136cSJon Loeliger #define CONFIG_BOOTP_HOSTNAME 474079a136cSJon Loeliger 475079a136cSJon Loeliger /* 4768ea5499aSJon Loeliger * Command line configuration. 4778ea5499aSJon Loeliger */ 4788ea5499aSJon Loeliger #define CONFIG_CMD_DATE 4798ea5499aSJon Loeliger #define CONFIG_CMD_PCI 4808ea5499aSJon Loeliger 48196b8a054SScott Wood #define CONFIG_CMDLINE_EDITING 1 482a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 48396b8a054SScott Wood 48496b8a054SScott Wood /* 48596b8a054SScott Wood * Miscellaneous configurable options 48696b8a054SScott Wood */ 4876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 4886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 4896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 49096b8a054SScott Wood 491261c07bcSJoe Hershberger /* Print Buffer Size */ 492261c07bcSJoe Hershberger #define CONFIG_SYS_PBSIZE \ 493261c07bcSJoe Hershberger (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 4946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 495261c07bcSJoe Hershberger /* Boot Argument Buffer Size */ 496261c07bcSJoe Hershberger #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 49796b8a054SScott Wood 49896b8a054SScott Wood /* 49996b8a054SScott Wood * For booting Linux, the board info and command line data 5009f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 50196b8a054SScott Wood * the maximum mapped by the Linux kernel during initialization. 50296b8a054SScott Wood */ 503261c07bcSJoe Hershberger /* Initial Memory map for Linux*/ 504261c07bcSJoe Hershberger #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 505*63865278SKevin Hao #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 50696b8a054SScott Wood 5076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 50896b8a054SScott Wood 5096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 51096b8a054SScott Wood 51196b8a054SScott Wood /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 51296b8a054SScott Wood /* 0x62040000 */ 5136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 51496b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 51596b8a054SScott Wood HRCWL_DDRCM |\ 51696b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 51796b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 51896b8a054SScott Wood HRCWL_CSB_TO_CLKIN_2X1 |\ 51996b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 52096b8a054SScott Wood 5216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 522e4c09508SScott Wood 5236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 52496b8a054SScott Wood 52596b8a054SScott Wood /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 52696b8a054SScott Wood /* 0x65040000 */ 5276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 52896b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 52996b8a054SScott Wood HRCWL_DDRCM |\ 53096b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 53196b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 53296b8a054SScott Wood HRCWL_CSB_TO_CLKIN_5X1 |\ 53396b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 53496b8a054SScott Wood 5356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 536e4c09508SScott Wood 53796b8a054SScott Wood #endif 53896b8a054SScott Wood 5396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH_BASE (\ 54096b8a054SScott Wood HRCWH_PCI_HOST |\ 54196b8a054SScott Wood HRCWH_PCI1_ARBITER_ENABLE |\ 54296b8a054SScott Wood HRCWH_CORE_ENABLE |\ 54396b8a054SScott Wood HRCWH_BOOTSEQ_DISABLE |\ 54496b8a054SScott Wood HRCWH_SW_WATCHDOG_DISABLE |\ 54596b8a054SScott Wood HRCWH_TSEC1M_IN_RGMII |\ 54696b8a054SScott Wood HRCWH_TSEC2M_IN_RGMII |\ 547e4c09508SScott Wood HRCWH_BIG_ENDIAN) 548e4c09508SScott Wood 54922f4442dSScott Wood #ifdef CONFIG_NAND 5506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 551e4c09508SScott Wood HRCWH_FROM_0XFFF00100 |\ 552e4c09508SScott Wood HRCWH_ROM_LOC_NAND_SP_8BIT |\ 553e4c09508SScott Wood HRCWH_RL_EXT_NAND) 554e4c09508SScott Wood #else 5556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 556e4c09508SScott Wood HRCWH_FROM_0X00000100 |\ 557e4c09508SScott Wood HRCWH_ROM_LOC_LOCAL_16BIT |\ 558e4c09508SScott Wood HRCWH_RL_EXT_LEGACY) 559e4c09508SScott Wood #endif 56096b8a054SScott Wood 56196b8a054SScott Wood /* System IO Config */ 5626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 5630eaf8f9eSJoe Hershberger /* Enable Internal USB Phy and GPIO on LCD Connector */ 5640eaf8f9eSJoe Hershberger #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 56596b8a054SScott Wood 5666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_INIT 0x000000000 5676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 5681a2e203bSKim Phillips HID0_ENABLE_INSTRUCTION_CACHE | \ 56996b8a054SScott Wood HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 57096b8a054SScott Wood 5716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 57296b8a054SScott Wood 57331d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 57431d82672SBecky Bruce 57596b8a054SScott Wood /* DDR @ 0x00000000 */ 57672cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 577261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 578261c07bcSJoe Hershberger | BATU_BL_256M \ 579261c07bcSJoe Hershberger | BATU_VS \ 580261c07bcSJoe Hershberger | BATU_VP) 58196b8a054SScott Wood 58296b8a054SScott Wood /* PCI @ 0x80000000 */ 58372cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 584261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 585261c07bcSJoe Hershberger | BATU_BL_256M \ 586261c07bcSJoe Hershberger | BATU_VS \ 587261c07bcSJoe Hershberger | BATU_VP) 588261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 58972cd4087SJoe Hershberger | BATL_PP_RW \ 590261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 591261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 592261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 593261c07bcSJoe Hershberger | BATU_BL_256M \ 594261c07bcSJoe Hershberger | BATU_VS \ 595261c07bcSJoe Hershberger | BATU_VP) 59696b8a054SScott Wood 59796b8a054SScott Wood /* PCI2 not supported on 8313 */ 5986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L (0) 5996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U (0) 6006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L (0) 6016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U (0) 60296b8a054SScott Wood 60396b8a054SScott Wood /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 604261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 60572cd4087SJoe Hershberger | BATL_PP_RW \ 606261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 607261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 608261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 609261c07bcSJoe Hershberger | BATU_BL_256M \ 610261c07bcSJoe Hershberger | BATU_VS \ 611261c07bcSJoe Hershberger | BATU_VP) 61296b8a054SScott Wood 61396b8a054SScott Wood /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 61472cd4087SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 6156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 61696b8a054SScott Wood 6176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L (0) 6186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U (0) 61996b8a054SScott Wood 6206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 6216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 6226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 6236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 6246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 6256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 6266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 6276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 6286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 6296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 6306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 6316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 6326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 6336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 6346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 6356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 63696b8a054SScott Wood 63796b8a054SScott Wood /* 63896b8a054SScott Wood * Environment Configuration 63996b8a054SScott Wood */ 64096b8a054SScott Wood #define CONFIG_ENV_OVERWRITE 64196b8a054SScott Wood 642261c07bcSJoe Hershberger #define CONFIG_NETDEV "eth1" 64396b8a054SScott Wood 64496b8a054SScott Wood #define CONFIG_HOSTNAME mpc8313erdb 6458b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfs/root/path" 646b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 647261c07bcSJoe Hershberger /* U-Boot image on TFTP server */ 648261c07bcSJoe Hershberger #define CONFIG_UBOOTPATH "u-boot.bin" 649261c07bcSJoe Hershberger #define CONFIG_FDTFILE "mpc8313erdb.dtb" 65096b8a054SScott Wood 651261c07bcSJoe Hershberger /* default location for tftp and bootm */ 652261c07bcSJoe Hershberger #define CONFIG_LOADADDR 800000 65396b8a054SScott Wood #define CONFIG_BAUDRATE 115200 65496b8a054SScott Wood 65596b8a054SScott Wood #define CONFIG_EXTRA_ENV_SETTINGS \ 656261c07bcSJoe Hershberger "netdev=" CONFIG_NETDEV "\0" \ 65796b8a054SScott Wood "ethprime=TSEC1\0" \ 658261c07bcSJoe Hershberger "uboot=" CONFIG_UBOOTPATH "\0" \ 65996b8a054SScott Wood "tftpflash=tftpboot $loadaddr $uboot; " \ 6605368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 6615368c55dSMarek Vasut " +$filesize; " \ 6625368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 6635368c55dSMarek Vasut " +$filesize; " \ 6645368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 6655368c55dSMarek Vasut " $filesize; " \ 6665368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 6675368c55dSMarek Vasut " +$filesize; " \ 6685368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 6695368c55dSMarek Vasut " $filesize\0" \ 67079f516bcSKim Phillips "fdtaddr=780000\0" \ 671261c07bcSJoe Hershberger "fdtfile=" CONFIG_FDTFILE "\0" \ 67296b8a054SScott Wood "console=ttyS0\0" \ 67396b8a054SScott Wood "setbootargs=setenv bootargs " \ 67496b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 67596b8a054SScott Wood "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 676261c07bcSJoe Hershberger "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 677261c07bcSJoe Hershberger "$netdev:off " \ 67896b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 67996b8a054SScott Wood 68096b8a054SScott Wood #define CONFIG_NFSBOOTCOMMAND \ 68196b8a054SScott Wood "setenv rootdev /dev/nfs;" \ 68296b8a054SScott Wood "run setbootargs;" \ 68396b8a054SScott Wood "run setipargs;" \ 68496b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 68596b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 68696b8a054SScott Wood "bootm $loadaddr - $fdtaddr" 68796b8a054SScott Wood 68896b8a054SScott Wood #define CONFIG_RAMBOOTCOMMAND \ 68996b8a054SScott Wood "setenv rootdev /dev/ram;" \ 69096b8a054SScott Wood "run setbootargs;" \ 69196b8a054SScott Wood "tftp $ramdiskaddr $ramdiskfile;" \ 69296b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 69396b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 69496b8a054SScott Wood "bootm $loadaddr $ramdiskaddr $fdtaddr" 69596b8a054SScott Wood 69696b8a054SScott Wood #endif /* __CONFIG_H */ 697