196b8a054SScott Wood /* 2e8d3ca8bSScott Wood * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 396b8a054SScott Wood * 496b8a054SScott Wood * See file CREDITS for list of people who contributed to this 596b8a054SScott Wood * project. 696b8a054SScott Wood * 796b8a054SScott Wood * This program is free software; you can redistribute it and/or 896b8a054SScott Wood * modify it under the terms of the GNU General Public License as 996b8a054SScott Wood * published by the Free Software Foundation; either version 2 of 1096b8a054SScott Wood * the License, or (at your option) any later version. 1196b8a054SScott Wood * 1296b8a054SScott Wood * This program is distributed in the hope that it will be useful, 1396b8a054SScott Wood * but WITHOUT ANY WARRANTY; without even the implied warranty of 1496b8a054SScott Wood * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1596b8a054SScott Wood * GNU General Public License for more details. 1696b8a054SScott Wood * 1796b8a054SScott Wood * You should have received a copy of the GNU General Public License 1896b8a054SScott Wood * along with this program; if not, write to the Free Software 1996b8a054SScott Wood * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 2096b8a054SScott Wood * MA 02111-1307 USA 2196b8a054SScott Wood */ 2296b8a054SScott Wood /* 2396b8a054SScott Wood * mpc8313epb board configuration file 2496b8a054SScott Wood */ 2596b8a054SScott Wood 2696b8a054SScott Wood #ifndef __CONFIG_H 2796b8a054SScott Wood #define __CONFIG_H 2896b8a054SScott Wood 2996b8a054SScott Wood /* 3096b8a054SScott Wood * High Level Configuration Options 3196b8a054SScott Wood */ 3296b8a054SScott Wood #define CONFIG_E300 1 330f898604SPeter Tyser #define CONFIG_MPC83xx 1 342c7920afSPeter Tyser #define CONFIG_MPC831x 1 3596b8a054SScott Wood #define CONFIG_MPC8313 1 3696b8a054SScott Wood #define CONFIG_MPC8313ERDB 1 3796b8a054SScott Wood 3822f4442dSScott Wood #ifdef CONFIG_NAND 3922f4442dSScott Wood #define CONFIG_SPL 4022f4442dSScott Wood #define CONFIG_SPL_INIT_MINIMAL 4122f4442dSScott Wood #define CONFIG_SPL_SERIAL_SUPPORT 4222f4442dSScott Wood #define CONFIG_SPL_NAND_SUPPORT 4322f4442dSScott Wood #define CONFIG_SPL_NAND_MINIMAL 4422f4442dSScott Wood #define CONFIG_SPL_FLUSH_IMAGE 4522f4442dSScott Wood #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 4622f4442dSScott Wood #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 4722f4442dSScott Wood 4822f4442dSScott Wood #ifdef CONFIG_SPL_BUILD 4922f4442dSScott Wood #define CONFIG_NS16550_MIN_FUNCTIONS 5022f4442dSScott Wood #endif 5122f4442dSScott Wood 5222f4442dSScott Wood #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 5322f4442dSScott Wood #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 5422f4442dSScott Wood #define CONFIG_SPL_MAX_SIZE (4 * 1024) 55*6113d3f2SBenoît Thébaudeau #define CONFIG_SPL_PAD_TO 0x4000 5622f4442dSScott Wood 57f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 58f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 59f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 60f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 61f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 62f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 63f1c574d4SScott Wood 6422f4442dSScott Wood #ifdef CONFIG_SPL_BUILD 65f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 6622f4442dSScott Wood #endif 6722f4442dSScott Wood 6822f4442dSScott Wood #endif /* CONFIG_NAND */ 69f1c574d4SScott Wood 702ae18241SWolfgang Denk #ifndef CONFIG_SYS_TEXT_BASE 712ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFE000000 722ae18241SWolfgang Denk #endif 732ae18241SWolfgang Denk 74f1c574d4SScott Wood #ifndef CONFIG_SYS_MONITOR_BASE 75f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 76f1c574d4SScott Wood #endif 77f1c574d4SScott Wood 7896b8a054SScott Wood #define CONFIG_PCI 790914f483SBecky Bruce #define CONFIG_FSL_ELBC 1 8096b8a054SScott Wood 8189c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 8289c7784eSTimur Tabi 8389c7784eSTimur Tabi /* 8489c7784eSTimur Tabi * On-board devices 854ce1e23bSYork Sun * 864ce1e23bSYork Sun * TSEC1 is VSC switch 874ce1e23bSYork Sun * TSEC2 is SoC TSEC 8889c7784eSTimur Tabi */ 8989c7784eSTimur Tabi #define CONFIG_VSC7385_ENET 904ce1e23bSYork Sun #define CONFIG_TSEC2 9189c7784eSTimur Tabi 926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 935c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 955c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 9696b8a054SScott Wood #else 9796b8a054SScott Wood #error Unknown oscillator frequency. 9896b8a054SScott Wood #endif 9996b8a054SScott Wood 10096b8a054SScott Wood #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 10196b8a054SScott Wood 1020eaf8f9eSJoe Hershberger #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ 1030eaf8f9eSJoe Hershberger #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */ 10496b8a054SScott Wood 1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 10696b8a054SScott Wood 10722f4442dSScott Wood #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) 1086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 109e4c09508SScott Wood #endif 110e4c09508SScott Wood 1116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00001000 1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x07f00000 11396b8a054SScott Wood 11496b8a054SScott Wood /* Early revs of this board will lock up hard when attempting 11596b8a054SScott Wood * to access the PMC registers, unless a JTAG debugger is 11696b8a054SScott Wood * connected, or some resistor modifications are made. 11796b8a054SScott Wood */ 1186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 11996b8a054SScott Wood 1206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 1216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 12296b8a054SScott Wood 12396b8a054SScott Wood /* 12489c7784eSTimur Tabi * Device configurations 12589c7784eSTimur Tabi */ 12689c7784eSTimur Tabi 12789c7784eSTimur Tabi /* Vitesse 7385 */ 12889c7784eSTimur Tabi 12989c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 13089c7784eSTimur Tabi 1314ce1e23bSYork Sun #define CONFIG_TSEC1 13289c7784eSTimur Tabi 13389c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 13489c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFE7FE000 13589c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 13689c7784eSTimur Tabi 13789c7784eSTimur Tabi #endif 13889c7784eSTimur Tabi 13989c7784eSTimur Tabi /* 14096b8a054SScott Wood * DDR Setup 14196b8a054SScott Wood */ 1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 14596b8a054SScott Wood 14696b8a054SScott Wood /* 14796b8a054SScott Wood * Manually set up DDR parameters, as this board does not 14896b8a054SScott Wood * seem to have the SPD connected to I2C. 14996b8a054SScott Wood */ 1506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 1512e651b24SJoe Hershberger #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 1522fef4020SJoe Hershberger | CSCONFIG_ODT_RD_NEVER \ 1532fef4020SJoe Hershberger | CSCONFIG_ODT_WR_ONLY_CURRENT \ 154261c07bcSJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 155261c07bcSJoe Hershberger | CSCONFIG_COL_BIT_10) 156e1d8ed2cSPoonam Aggrwal /* 0x80010102 */ 15796b8a054SScott Wood 1586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_3 0x00000000 1596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 16096b8a054SScott Wood | (0 << TIMING_CFG0_WRT_SHIFT) \ 16196b8a054SScott Wood | (0 << TIMING_CFG0_RRT_SHIFT) \ 16296b8a054SScott Wood | (0 << TIMING_CFG0_WWT_SHIFT) \ 16396b8a054SScott Wood | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 16496b8a054SScott Wood | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 16596b8a054SScott Wood | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 16696b8a054SScott Wood | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 16796b8a054SScott Wood /* 0x00220802 */ 1686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 169e1d8ed2cSPoonam Aggrwal | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 17096b8a054SScott Wood | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 17196b8a054SScott Wood | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 172e1d8ed2cSPoonam Aggrwal | (10 << TIMING_CFG1_REFREC_SHIFT) \ 17396b8a054SScott Wood | (3 << TIMING_CFG1_WRREC_SHIFT) \ 17496b8a054SScott Wood | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 17596b8a054SScott Wood | (2 << TIMING_CFG1_WRTORD_SHIFT)) 176e1d8ed2cSPoonam Aggrwal /* 0x3835a322 */ 1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 178e1d8ed2cSPoonam Aggrwal | (5 << TIMING_CFG2_CPO_SHIFT) \ 17996b8a054SScott Wood | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 18096b8a054SScott Wood | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 18196b8a054SScott Wood | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 18296b8a054SScott Wood | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 183e1d8ed2cSPoonam Aggrwal | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 184e1d8ed2cSPoonam Aggrwal /* 0x129048c6 */ /* P9-45,may need tuning */ 1856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 186e1d8ed2cSPoonam Aggrwal | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 187e1d8ed2cSPoonam Aggrwal /* 0x05100500 */ 18896b8a054SScott Wood #if defined(CONFIG_DDR_2T_TIMING) 1896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 190bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1912fef4020SJoe Hershberger | SDRAM_CFG_DBW_32 \ 1922fef4020SJoe Hershberger | SDRAM_CFG_2T_EN) 1932fef4020SJoe Hershberger /* 0x43088000 */ 19496b8a054SScott Wood #else 1956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 196bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1972fef4020SJoe Hershberger | SDRAM_CFG_DBW_32) 19896b8a054SScott Wood /* 0x43080000 */ 19996b8a054SScott Wood #endif 2006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG2 0x00401000 20196b8a054SScott Wood /* set burst length to 8 for 32-bit data path */ 2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 203e1d8ed2cSPoonam Aggrwal | (0x0632 << SDRAM_MODE_SD_SHIFT)) 204e1d8ed2cSPoonam Aggrwal /* 0x44480632 */ 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x8000C000 20696b8a054SScott Wood 2076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 20896b8a054SScott Wood /*0x02000000*/ 2096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 21096b8a054SScott Wood | DDRCDR_PZ_NOMZ \ 21196b8a054SScott Wood | DDRCDR_NZ_NOMZ \ 21296b8a054SScott Wood | DDRCDR_M_ODR) 21396b8a054SScott Wood 21496b8a054SScott Wood /* 21596b8a054SScott Wood * FLASH on the Local Bus 21696b8a054SScott Wood */ 2176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 21800b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 2196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 2206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 2236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 22496b8a054SScott Wood 225261c07bcSJoe Hershberger #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 2267d6a0982SJoe Hershberger | BR_PS_16 /* 16 bit port */ \ 2277d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 228261c07bcSJoe Hershberger | BR_V) /* valid */ 2297d6a0982SJoe Hershberger #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 23096b8a054SScott Wood | OR_GPCM_XACS \ 23196b8a054SScott Wood | OR_GPCM_SCY_9 \ 23296b8a054SScott Wood | OR_GPCM_EHTR \ 23396b8a054SScott Wood | OR_GPCM_EAD) 23496b8a054SScott Wood /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 235261c07bcSJoe Hershberger /* window base at flash base */ 236261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2377d6a0982SJoe Hershberger /* 16 MB window size */ 2387d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 23996b8a054SScott Wood 2406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 2416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 24296b8a054SScott Wood 2436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 24596b8a054SScott Wood 246261c07bcSJoe Hershberger #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 24722f4442dSScott Wood !defined(CONFIG_SPL_BUILD) 2486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 24996b8a054SScott Wood #endif 25096b8a054SScott Wood 2516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 252261c07bcSJoe Hershberger #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 253553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 25496b8a054SScott Wood 255261c07bcSJoe Hershberger #define CONFIG_SYS_GBL_DATA_OFFSET \ 256261c07bcSJoe Hershberger (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 25896b8a054SScott Wood 2596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 2604a9932a4SKim Phillips #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 2616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 26296b8a054SScott Wood 26396b8a054SScott Wood /* 26496b8a054SScott Wood * Local Bus LCRR and LBCR regs 26596b8a054SScott Wood */ 266c7190f02SKim Phillips #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 267c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 2686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 26996b8a054SScott Wood | (0xFF << LBCR_BMT_SHIFT) \ 27096b8a054SScott Wood | 0xF) /* 0x0004ff0f */ 27196b8a054SScott Wood 272261c07bcSJoe Hershberger /* LB refresh timer prescal, 266MHz/32 */ 273261c07bcSJoe Hershberger #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 27496b8a054SScott Wood 2757817cb20SMarcel Ziswiler /* drivers/mtd/nand/nand.c */ 27622f4442dSScott Wood #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) 2776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xFFF00000 278e4c09508SScott Wood #else 2796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xE2800000 280e4c09508SScott Wood #endif 281e4c09508SScott Wood 282e8d3ca8bSScott Wood #define CONFIG_MTD_DEVICE 283e8d3ca8bSScott Wood #define CONFIG_MTD_PARTITION 284e8d3ca8bSScott Wood #define CONFIG_CMD_MTDPARTS 285e8d3ca8bSScott Wood #define MTDIDS_DEFAULT "nand0=e2800000.flash" 286e8d3ca8bSScott Wood #define MTDPARTS_DEFAULT \ 287c947c12eSScott Wood "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" 288e8d3ca8bSScott Wood 2896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_NAND_DEVICE 1 29096b8a054SScott Wood #define CONFIG_MTD_NAND_VERIFY_WRITE 291acdab5c3SScott Wood #define CONFIG_CMD_NAND 1 292acdab5c3SScott Wood #define CONFIG_NAND_FSL_ELBC 1 2936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 2947d6a0982SJoe Hershberger #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 29596b8a054SScott Wood 296e4c09508SScott Wood 2976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 2987d6a0982SJoe Hershberger | BR_DECC_CHK_GEN /* Use HW ECC */ \ 299261c07bcSJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 30096b8a054SScott Wood | BR_MS_FCM /* MSEL = FCM */ \ 30196b8a054SScott Wood | BR_V) /* valid */ 3027d6a0982SJoe Hershberger #define CONFIG_SYS_NAND_OR_PRELIM \ 3037d6a0982SJoe Hershberger (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 30496b8a054SScott Wood | OR_FCM_CSCT \ 30596b8a054SScott Wood | OR_FCM_CST \ 30696b8a054SScott Wood | OR_FCM_CHT \ 30796b8a054SScott Wood | OR_FCM_SCY_1 \ 30896b8a054SScott Wood | OR_FCM_TRLX \ 30996b8a054SScott Wood | OR_FCM_EHTR) 31096b8a054SScott Wood /* 0xFFFF8396 */ 311e4c09508SScott Wood 31222f4442dSScott Wood #ifdef CONFIG_NAND 3136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 3146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 3156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 3166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 317e4c09508SScott Wood #else 3186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 3196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 3206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 3216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 322e4c09508SScott Wood #endif 323e4c09508SScott Wood 3246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 3257d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 32696b8a054SScott Wood 3276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 3286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 329e4c09508SScott Wood 3307d6a0982SJoe Hershberger /* local bus write LED / read status buffer (BCSR) mapping */ 3317d6a0982SJoe Hershberger #define CONFIG_SYS_BCSR_ADDR 0xFA000000 3327d6a0982SJoe Hershberger #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 3337d6a0982SJoe Hershberger /* map at 0xFA000000 on LCS3 */ 3347d6a0982SJoe Hershberger #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 3357d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 3367d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 3377d6a0982SJoe Hershberger | BR_V) /* valid */ 3387d6a0982SJoe Hershberger /* 0xFA000801 */ 3397d6a0982SJoe Hershberger #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 3407d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 3417d6a0982SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 3427d6a0982SJoe Hershberger | OR_GPCM_XACS \ 3437d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 3447d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 3457d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 3467d6a0982SJoe Hershberger | OR_GPCM_EAD) 3477d6a0982SJoe Hershberger /* 0xFFFF8FF7 */ 3487d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 3497d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 35096b8a054SScott Wood 35189c7784eSTimur Tabi /* Vitesse 7385 */ 35289c7784eSTimur Tabi 35389c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 35489c7784eSTimur Tabi 3557d6a0982SJoe Hershberger /* VSC7385 Base address on LCS2 */ 3567d6a0982SJoe Hershberger #define CONFIG_SYS_VSC7385_BASE 0xF0000000 3577d6a0982SJoe Hershberger #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 3587d6a0982SJoe Hershberger 3597d6a0982SJoe Hershberger #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 3607d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 3617d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 3627d6a0982SJoe Hershberger | BR_V) /* valid */ 3637d6a0982SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 3647d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 3657d6a0982SJoe Hershberger | OR_GPCM_XACS \ 3667d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 3677d6a0982SJoe Hershberger | OR_GPCM_SETA \ 3687d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 3697d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 3707d6a0982SJoe Hershberger | OR_GPCM_EAD) 3717d6a0982SJoe Hershberger /* 0xFFFE09FF */ 3727d6a0982SJoe Hershberger 373261c07bcSJoe Hershberger /* Access window base at VSC7385 base */ 374261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 3757d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 37689c7784eSTimur Tabi 37789c7784eSTimur Tabi #endif 37889c7784eSTimur Tabi 37996b8a054SScott Wood /* pass open firmware flat tree */ 38035cc4e48SKim Phillips #define CONFIG_OF_LIBFDT 1 38196b8a054SScott Wood #define CONFIG_OF_BOARD_SETUP 1 3825b8bc606SKim Phillips #define CONFIG_OF_STDOUT_VIA_ALIAS 1 38396b8a054SScott Wood 3840eaf8f9eSJoe Hershberger #define CONFIG_MPC83XX_GPIO 1 3850eaf8f9eSJoe Hershberger #define CONFIG_CMD_GPIO 1 3860eaf8f9eSJoe Hershberger 38796b8a054SScott Wood /* 38896b8a054SScott Wood * Serial Port 38996b8a054SScott Wood */ 39096b8a054SScott Wood #define CONFIG_CONS_INDEX 1 3916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 39496b8a054SScott Wood 3956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 39696b8a054SScott Wood {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 39796b8a054SScott Wood 3986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 3996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 40096b8a054SScott Wood 40196b8a054SScott Wood /* Use the HUSH parser */ 4026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 40396b8a054SScott Wood 40496b8a054SScott Wood /* I2C */ 40596b8a054SScott Wood #define CONFIG_HARD_I2C /* I2C with hardware support*/ 40696b8a054SScott Wood #define CONFIG_FSL_I2C 40796b8a054SScott Wood #define CONFIG_I2C_MULTI_BUS 4086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 4096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 4106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ 4116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 4126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 41396b8a054SScott Wood 41496b8a054SScott Wood /* 41596b8a054SScott Wood * General PCI 41696b8a054SScott Wood * Addresses are mapped 1-1. 41796b8a054SScott Wood */ 4186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 4196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 4206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 4216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 4226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 4236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 4246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 4256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 4266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 42796b8a054SScott Wood 42896b8a054SScott Wood #define CONFIG_PCI_PNP /* do pci plug-and-play */ 4296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 43096b8a054SScott Wood 43196b8a054SScott Wood /* 43289c7784eSTimur Tabi * TSEC 43396b8a054SScott Wood */ 43496b8a054SScott Wood #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 43596b8a054SScott Wood 43689c7784eSTimur Tabi #define CONFIG_GMII /* MII PHY management */ 43789c7784eSTimur Tabi 43889c7784eSTimur Tabi #ifdef CONFIG_TSEC1 43989c7784eSTimur Tabi #define CONFIG_HAS_ETH0 44089c7784eSTimur Tabi #define CONFIG_TSEC1_NAME "TSEC0" 4416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 44289c7784eSTimur Tabi #define TSEC1_PHY_ADDR 0x1c 44389c7784eSTimur Tabi #define TSEC1_FLAGS TSEC_GIGABIT 44489c7784eSTimur Tabi #define TSEC1_PHYIDX 0 44596b8a054SScott Wood #endif 44696b8a054SScott Wood 44789c7784eSTimur Tabi #ifdef CONFIG_TSEC2 44889c7784eSTimur Tabi #define CONFIG_HAS_ETH1 449255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 4506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 45196b8a054SScott Wood #define TSEC2_PHY_ADDR 4 4523a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 45396b8a054SScott Wood #define TSEC2_PHYIDX 0 45489c7784eSTimur Tabi #endif 45589c7784eSTimur Tabi 45696b8a054SScott Wood 45796b8a054SScott Wood /* Options are: TSEC[0-1] */ 45896b8a054SScott Wood #define CONFIG_ETHPRIME "TSEC1" 45996b8a054SScott Wood 46096b8a054SScott Wood /* 46196b8a054SScott Wood * Configure on-board RTC 46296b8a054SScott Wood */ 46396b8a054SScott Wood #define CONFIG_RTC_DS1337 4646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 46596b8a054SScott Wood 46696b8a054SScott Wood /* 46796b8a054SScott Wood * Environment 46896b8a054SScott Wood */ 46922f4442dSScott Wood #if defined(CONFIG_NAND) 47051bfee19SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_NAND 1 4710e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET (512 * 1024) 4726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 4730e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 4740e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 4750e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 476261c07bcSJoe Hershberger #define CONFIG_ENV_OFFSET_REDUND \ 477261c07bcSJoe Hershberger (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 4786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif !defined(CONFIG_SYS_RAMBOOT) 4795a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 480261c07bcSJoe Hershberger #define CONFIG_ENV_ADDR \ 481261c07bcSJoe Hershberger (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4820e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 4830e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 48496b8a054SScott Wood 48596b8a054SScott Wood /* Address and size of Redundant Environment Sector */ 48696b8a054SScott Wood #else 48793f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 4886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4890e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 49096b8a054SScott Wood #endif 49196b8a054SScott Wood 49296b8a054SScott Wood #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 4936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 49496b8a054SScott Wood 4958ea5499aSJon Loeliger /* 496079a136cSJon Loeliger * BOOTP options 497079a136cSJon Loeliger */ 498079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 499079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTPATH 500079a136cSJon Loeliger #define CONFIG_BOOTP_GATEWAY 501079a136cSJon Loeliger #define CONFIG_BOOTP_HOSTNAME 502079a136cSJon Loeliger 503079a136cSJon Loeliger 504079a136cSJon Loeliger /* 5058ea5499aSJon Loeliger * Command line configuration. 5068ea5499aSJon Loeliger */ 5078ea5499aSJon Loeliger #include <config_cmd_default.h> 5088ea5499aSJon Loeliger 5098ea5499aSJon Loeliger #define CONFIG_CMD_PING 5108ea5499aSJon Loeliger #define CONFIG_CMD_DHCP 5118ea5499aSJon Loeliger #define CONFIG_CMD_I2C 5128ea5499aSJon Loeliger #define CONFIG_CMD_MII 5138ea5499aSJon Loeliger #define CONFIG_CMD_DATE 5148ea5499aSJon Loeliger #define CONFIG_CMD_PCI 5158ea5499aSJon Loeliger 51622f4442dSScott Wood #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND) 517bdab39d3SMike Frysinger #undef CONFIG_CMD_SAVEENV 5188ea5499aSJon Loeliger #undef CONFIG_CMD_LOADS 5198ea5499aSJon Loeliger #endif 52096b8a054SScott Wood 52196b8a054SScott Wood #define CONFIG_CMDLINE_EDITING 1 522a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 52396b8a054SScott Wood 52496b8a054SScott Wood /* 52596b8a054SScott Wood * Miscellaneous configurable options 52696b8a054SScott Wood */ 5276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 5286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 5296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 5306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 53196b8a054SScott Wood 532261c07bcSJoe Hershberger /* Print Buffer Size */ 533261c07bcSJoe Hershberger #define CONFIG_SYS_PBSIZE \ 534261c07bcSJoe Hershberger (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 5356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 536261c07bcSJoe Hershberger /* Boot Argument Buffer Size */ 537261c07bcSJoe Hershberger #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 5386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 53996b8a054SScott Wood 54096b8a054SScott Wood /* 54196b8a054SScott Wood * For booting Linux, the board info and command line data 5429f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 54396b8a054SScott Wood * the maximum mapped by the Linux kernel during initialization. 54496b8a054SScott Wood */ 545261c07bcSJoe Hershberger /* Initial Memory map for Linux*/ 546261c07bcSJoe Hershberger #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 54796b8a054SScott Wood 5486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 54996b8a054SScott Wood 5506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 55196b8a054SScott Wood 55296b8a054SScott Wood /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 55396b8a054SScott Wood /* 0x62040000 */ 5546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 55596b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 55696b8a054SScott Wood HRCWL_DDRCM |\ 55796b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 55896b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 55996b8a054SScott Wood HRCWL_CSB_TO_CLKIN_2X1 |\ 56096b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 56196b8a054SScott Wood 5626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 563e4c09508SScott Wood 5646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 56596b8a054SScott Wood 56696b8a054SScott Wood /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 56796b8a054SScott Wood /* 0x65040000 */ 5686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 56996b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 57096b8a054SScott Wood HRCWL_DDRCM |\ 57196b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 57296b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 57396b8a054SScott Wood HRCWL_CSB_TO_CLKIN_5X1 |\ 57496b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 57596b8a054SScott Wood 5766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 577e4c09508SScott Wood 57896b8a054SScott Wood #endif 57996b8a054SScott Wood 5806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH_BASE (\ 58196b8a054SScott Wood HRCWH_PCI_HOST |\ 58296b8a054SScott Wood HRCWH_PCI1_ARBITER_ENABLE |\ 58396b8a054SScott Wood HRCWH_CORE_ENABLE |\ 58496b8a054SScott Wood HRCWH_BOOTSEQ_DISABLE |\ 58596b8a054SScott Wood HRCWH_SW_WATCHDOG_DISABLE |\ 58696b8a054SScott Wood HRCWH_TSEC1M_IN_RGMII |\ 58796b8a054SScott Wood HRCWH_TSEC2M_IN_RGMII |\ 588e4c09508SScott Wood HRCWH_BIG_ENDIAN) 589e4c09508SScott Wood 59022f4442dSScott Wood #ifdef CONFIG_NAND 5916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 592e4c09508SScott Wood HRCWH_FROM_0XFFF00100 |\ 593e4c09508SScott Wood HRCWH_ROM_LOC_NAND_SP_8BIT |\ 594e4c09508SScott Wood HRCWH_RL_EXT_NAND) 595e4c09508SScott Wood #else 5966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 597e4c09508SScott Wood HRCWH_FROM_0X00000100 |\ 598e4c09508SScott Wood HRCWH_ROM_LOC_LOCAL_16BIT |\ 599e4c09508SScott Wood HRCWH_RL_EXT_LEGACY) 600e4c09508SScott Wood #endif 60196b8a054SScott Wood 60296b8a054SScott Wood /* System IO Config */ 6036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 6040eaf8f9eSJoe Hershberger /* Enable Internal USB Phy and GPIO on LCD Connector */ 6050eaf8f9eSJoe Hershberger #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 60696b8a054SScott Wood 6076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_INIT 0x000000000 6086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 6091a2e203bSKim Phillips HID0_ENABLE_INSTRUCTION_CACHE | \ 61096b8a054SScott Wood HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 61196b8a054SScott Wood 6126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 61396b8a054SScott Wood 61431d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 61531d82672SBecky Bruce 61696b8a054SScott Wood /* DDR @ 0x00000000 */ 61772cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 618261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 619261c07bcSJoe Hershberger | BATU_BL_256M \ 620261c07bcSJoe Hershberger | BATU_VS \ 621261c07bcSJoe Hershberger | BATU_VP) 62296b8a054SScott Wood 62396b8a054SScott Wood /* PCI @ 0x80000000 */ 62472cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 625261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 626261c07bcSJoe Hershberger | BATU_BL_256M \ 627261c07bcSJoe Hershberger | BATU_VS \ 628261c07bcSJoe Hershberger | BATU_VP) 629261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 63072cd4087SJoe Hershberger | BATL_PP_RW \ 631261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 632261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 633261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 634261c07bcSJoe Hershberger | BATU_BL_256M \ 635261c07bcSJoe Hershberger | BATU_VS \ 636261c07bcSJoe Hershberger | BATU_VP) 63796b8a054SScott Wood 63896b8a054SScott Wood /* PCI2 not supported on 8313 */ 6396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L (0) 6406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U (0) 6416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L (0) 6426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U (0) 64396b8a054SScott Wood 64496b8a054SScott Wood /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 645261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 64672cd4087SJoe Hershberger | BATL_PP_RW \ 647261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 648261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 649261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 650261c07bcSJoe Hershberger | BATU_BL_256M \ 651261c07bcSJoe Hershberger | BATU_VS \ 652261c07bcSJoe Hershberger | BATU_VP) 65396b8a054SScott Wood 65496b8a054SScott Wood /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 65572cd4087SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 6566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 65796b8a054SScott Wood 6586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L (0) 6596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U (0) 66096b8a054SScott Wood 6616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 6626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 6636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 6646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 6656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 6666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 6676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 6686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 6696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 6706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 6716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 6726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 6736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 6746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 6756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 6766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 67796b8a054SScott Wood 67896b8a054SScott Wood /* 67996b8a054SScott Wood * Environment Configuration 68096b8a054SScott Wood */ 68196b8a054SScott Wood #define CONFIG_ENV_OVERWRITE 68296b8a054SScott Wood 683261c07bcSJoe Hershberger #define CONFIG_NETDEV "eth1" 68496b8a054SScott Wood 68596b8a054SScott Wood #define CONFIG_HOSTNAME mpc8313erdb 6868b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfs/root/path" 687b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 688261c07bcSJoe Hershberger /* U-Boot image on TFTP server */ 689261c07bcSJoe Hershberger #define CONFIG_UBOOTPATH "u-boot.bin" 690261c07bcSJoe Hershberger #define CONFIG_FDTFILE "mpc8313erdb.dtb" 69196b8a054SScott Wood 692261c07bcSJoe Hershberger /* default location for tftp and bootm */ 693261c07bcSJoe Hershberger #define CONFIG_LOADADDR 800000 6947fd0bea2SKim Phillips #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 69596b8a054SScott Wood #define CONFIG_BAUDRATE 115200 69696b8a054SScott Wood 69796b8a054SScott Wood #define CONFIG_EXTRA_ENV_SETTINGS \ 698261c07bcSJoe Hershberger "netdev=" CONFIG_NETDEV "\0" \ 69996b8a054SScott Wood "ethprime=TSEC1\0" \ 700261c07bcSJoe Hershberger "uboot=" CONFIG_UBOOTPATH "\0" \ 70196b8a054SScott Wood "tftpflash=tftpboot $loadaddr $uboot; " \ 7025368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 7035368c55dSMarek Vasut " +$filesize; " \ 7045368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 7055368c55dSMarek Vasut " +$filesize; " \ 7065368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 7075368c55dSMarek Vasut " $filesize; " \ 7085368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 7095368c55dSMarek Vasut " +$filesize; " \ 7105368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 7115368c55dSMarek Vasut " $filesize\0" \ 71279f516bcSKim Phillips "fdtaddr=780000\0" \ 713261c07bcSJoe Hershberger "fdtfile=" CONFIG_FDTFILE "\0" \ 71496b8a054SScott Wood "console=ttyS0\0" \ 71596b8a054SScott Wood "setbootargs=setenv bootargs " \ 71696b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 71796b8a054SScott Wood "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 718261c07bcSJoe Hershberger "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 719261c07bcSJoe Hershberger "$netdev:off " \ 72096b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 72196b8a054SScott Wood 72296b8a054SScott Wood #define CONFIG_NFSBOOTCOMMAND \ 72396b8a054SScott Wood "setenv rootdev /dev/nfs;" \ 72496b8a054SScott Wood "run setbootargs;" \ 72596b8a054SScott Wood "run setipargs;" \ 72696b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 72796b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 72896b8a054SScott Wood "bootm $loadaddr - $fdtaddr" 72996b8a054SScott Wood 73096b8a054SScott Wood #define CONFIG_RAMBOOTCOMMAND \ 73196b8a054SScott Wood "setenv rootdev /dev/ram;" \ 73296b8a054SScott Wood "run setbootargs;" \ 73396b8a054SScott Wood "tftp $ramdiskaddr $ramdiskfile;" \ 73496b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 73596b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 73696b8a054SScott Wood "bootm $loadaddr $ramdiskaddr $fdtaddr" 73796b8a054SScott Wood 73896b8a054SScott Wood #endif /* __CONFIG_H */ 739