196b8a054SScott Wood /* 296b8a054SScott Wood * Copyright (C) Freescale Semiconductor, Inc. 2006. 396b8a054SScott Wood * 496b8a054SScott Wood * See file CREDITS for list of people who contributed to this 596b8a054SScott Wood * project. 696b8a054SScott Wood * 796b8a054SScott Wood * This program is free software; you can redistribute it and/or 896b8a054SScott Wood * modify it under the terms of the GNU General Public License as 996b8a054SScott Wood * published by the Free Software Foundation; either version 2 of 1096b8a054SScott Wood * the License, or (at your option) any later version. 1196b8a054SScott Wood * 1296b8a054SScott Wood * This program is distributed in the hope that it will be useful, 1396b8a054SScott Wood * but WITHOUT ANY WARRANTY; without even the implied warranty of 1496b8a054SScott Wood * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1596b8a054SScott Wood * GNU General Public License for more details. 1696b8a054SScott Wood * 1796b8a054SScott Wood * You should have received a copy of the GNU General Public License 1896b8a054SScott Wood * along with this program; if not, write to the Free Software 1996b8a054SScott Wood * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 2096b8a054SScott Wood * MA 02111-1307 USA 2196b8a054SScott Wood */ 2296b8a054SScott Wood /* 2396b8a054SScott Wood * mpc8313epb board configuration file 2496b8a054SScott Wood */ 2596b8a054SScott Wood 2696b8a054SScott Wood #ifndef __CONFIG_H 2796b8a054SScott Wood #define __CONFIG_H 2896b8a054SScott Wood 2996b8a054SScott Wood /* 3096b8a054SScott Wood * High Level Configuration Options 3196b8a054SScott Wood */ 3296b8a054SScott Wood #define CONFIG_E300 1 330f898604SPeter Tyser #define CONFIG_MPC83xx 1 342c7920afSPeter Tyser #define CONFIG_MPC831x 1 3596b8a054SScott Wood #define CONFIG_MPC8313 1 3696b8a054SScott Wood #define CONFIG_MPC8313ERDB 1 3796b8a054SScott Wood 3896b8a054SScott Wood #define CONFIG_PCI 3996b8a054SScott Wood #define CONFIG_83XX_GENERIC_PCI 4096b8a054SScott Wood 4189c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 4289c7784eSTimur Tabi 4389c7784eSTimur Tabi /* 4489c7784eSTimur Tabi * On-board devices 454ce1e23bSYork Sun * 464ce1e23bSYork Sun * TSEC1 is VSC switch 474ce1e23bSYork Sun * TSEC2 is SoC TSEC 4889c7784eSTimur Tabi */ 4989c7784eSTimur Tabi #define CONFIG_VSC7385_ENET 504ce1e23bSYork Sun #define CONFIG_TSEC2 5189c7784eSTimur Tabi 526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 535c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 555c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 5696b8a054SScott Wood #else 5796b8a054SScott Wood #error Unknown oscillator frequency. 5896b8a054SScott Wood #endif 5996b8a054SScott Wood 6096b8a054SScott Wood #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 6196b8a054SScott Wood 6296b8a054SScott Wood #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 6396b8a054SScott Wood 646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 6596b8a054SScott Wood 66e4c09508SScott Wood #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 68e4c09508SScott Wood #endif 69e4c09508SScott Wood 706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00001000 716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x07f00000 7296b8a054SScott Wood 7396b8a054SScott Wood /* Early revs of this board will lock up hard when attempting 7496b8a054SScott Wood * to access the PMC registers, unless a JTAG debugger is 7596b8a054SScott Wood * connected, or some resistor modifications are made. 7696b8a054SScott Wood */ 776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 7896b8a054SScott Wood 796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 8196b8a054SScott Wood 8296b8a054SScott Wood /* 8389c7784eSTimur Tabi * Device configurations 8489c7784eSTimur Tabi */ 8589c7784eSTimur Tabi 8689c7784eSTimur Tabi /* Vitesse 7385 */ 8789c7784eSTimur Tabi 8889c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 8989c7784eSTimur Tabi 904ce1e23bSYork Sun #define CONFIG_TSEC1 9189c7784eSTimur Tabi 9289c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 9389c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFE7FE000 9489c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 9589c7784eSTimur Tabi 9689c7784eSTimur Tabi #endif 9789c7784eSTimur Tabi 9889c7784eSTimur Tabi /* 9996b8a054SScott Wood * DDR Setup 10096b8a054SScott Wood */ 1016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 10496b8a054SScott Wood 10596b8a054SScott Wood /* 10696b8a054SScott Wood * Manually set up DDR parameters, as this board does not 10796b8a054SScott Wood * seem to have the SPD connected to I2C. 10896b8a054SScott Wood */ 1096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 1106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \ 111e1d8ed2cSPoonam Aggrwal | 0x00010000 /* TODO */ \ 11296b8a054SScott Wood | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) 113e1d8ed2cSPoonam Aggrwal /* 0x80010102 */ 11496b8a054SScott Wood 1156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_3 0x00000000 1166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 11796b8a054SScott Wood | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 11896b8a054SScott Wood | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 11996b8a054SScott Wood | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 12096b8a054SScott Wood | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 12196b8a054SScott Wood | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 12296b8a054SScott Wood | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 12396b8a054SScott Wood | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 12496b8a054SScott Wood /* 0x00220802 */ 1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ 126e1d8ed2cSPoonam Aggrwal | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 12796b8a054SScott Wood | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ 12896b8a054SScott Wood | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 129e1d8ed2cSPoonam Aggrwal | (10 << TIMING_CFG1_REFREC_SHIFT ) \ 13096b8a054SScott Wood | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ 13196b8a054SScott Wood | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 13296b8a054SScott Wood | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 133e1d8ed2cSPoonam Aggrwal /* 0x3835a322 */ 1346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 135e1d8ed2cSPoonam Aggrwal | ( 5 << TIMING_CFG2_CPO_SHIFT ) \ 13696b8a054SScott Wood | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 13796b8a054SScott Wood | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 13896b8a054SScott Wood | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 13996b8a054SScott Wood | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 140e1d8ed2cSPoonam Aggrwal | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 141e1d8ed2cSPoonam Aggrwal /* 0x129048c6 */ /* P9-45,may need tuning */ 1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 143e1d8ed2cSPoonam Aggrwal | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 144e1d8ed2cSPoonam Aggrwal /* 0x05100500 */ 14596b8a054SScott Wood #if defined(CONFIG_DDR_2T_TIMING) 1466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ 147bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 14896b8a054SScott Wood | SDRAM_CFG_2T_EN \ 14996b8a054SScott Wood | SDRAM_CFG_DBW_32 ) 15096b8a054SScott Wood #else 1516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ 152bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 15396b8a054SScott Wood | SDRAM_CFG_32_BE ) 15496b8a054SScott Wood /* 0x43080000 */ 15596b8a054SScott Wood #endif 1566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG2 0x00401000 15796b8a054SScott Wood /* set burst length to 8 for 32-bit data path */ 1586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ 159e1d8ed2cSPoonam Aggrwal | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) ) 160e1d8ed2cSPoonam Aggrwal /* 0x44480632 */ 1616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x8000C000 16296b8a054SScott Wood 1636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 16496b8a054SScott Wood /*0x02000000*/ 1656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \ 16696b8a054SScott Wood | DDRCDR_PZ_NOMZ \ 16796b8a054SScott Wood | DDRCDR_NZ_NOMZ \ 16896b8a054SScott Wood | DDRCDR_M_ODR ) 16996b8a054SScott Wood 17096b8a054SScott Wood /* 17196b8a054SScott Wood * FLASH on the Local Bus 17296b8a054SScott Wood */ 1736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 17400b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 1756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 1766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 1786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 1796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 18096b8a054SScott Wood 1816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ 18296b8a054SScott Wood (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 18396b8a054SScott Wood BR_V) /* valid */ 1846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NOR_OR_PRELIM ( 0xFF800000 /* 8 MByte */ \ 18596b8a054SScott Wood | OR_GPCM_XACS \ 18696b8a054SScott Wood | OR_GPCM_SCY_9 \ 18796b8a054SScott Wood | OR_GPCM_EHTR \ 18896b8a054SScott Wood | OR_GPCM_EAD ) 18996b8a054SScott Wood /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 1906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ 1916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ 19296b8a054SScott Wood 1936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 1946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 19596b8a054SScott Wood 1966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 1976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 19896b8a054SScott Wood 1996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 20096b8a054SScott Wood 2016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_SPL) 2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 20396b8a054SScott Wood #endif 20496b8a054SScott Wood 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 2066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 2076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 20896b8a054SScott Wood 2096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 2106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 2116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 21296b8a054SScott Wood 2136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 214*4a9932a4SKim Phillips #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 2156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 21696b8a054SScott Wood 21796b8a054SScott Wood /* 21896b8a054SScott Wood * Local Bus LCRR and LBCR regs 21996b8a054SScott Wood */ 2206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4 2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \ 22296b8a054SScott Wood | (0xFF << LBCR_BMT_SHIFT) \ 22396b8a054SScott Wood | 0xF ) /* 0x0004ff0f */ 22496b8a054SScott Wood 2256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ 22696b8a054SScott Wood 2277817cb20SMarcel Ziswiler /* drivers/mtd/nand/nand.c */ 228e4c09508SScott Wood #ifdef CONFIG_NAND_SPL 2296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xFFF00000 230e4c09508SScott Wood #else 2316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xE2800000 232e4c09508SScott Wood #endif 233e4c09508SScott Wood 2346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_NAND_DEVICE 1 23596b8a054SScott Wood #define CONFIG_MTD_NAND_VERIFY_WRITE 236acdab5c3SScott Wood #define CONFIG_CMD_NAND 1 237acdab5c3SScott Wood #define CONFIG_NAND_FSL_ELBC 1 2386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 239d9ac3d5aSKim Phillips #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ 24096b8a054SScott Wood 2416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 2426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 2436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 2446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 2456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 246e4c09508SScott Wood 2476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ 24896b8a054SScott Wood | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 24996b8a054SScott Wood | BR_PS_8 /* Port Size = 8 bit */ \ 25096b8a054SScott Wood | BR_MS_FCM /* MSEL = FCM */ \ 25196b8a054SScott Wood | BR_V ) /* valid */ 2526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \ 25396b8a054SScott Wood | OR_FCM_CSCT \ 25496b8a054SScott Wood | OR_FCM_CST \ 25596b8a054SScott Wood | OR_FCM_CHT \ 25696b8a054SScott Wood | OR_FCM_SCY_1 \ 25796b8a054SScott Wood | OR_FCM_TRLX \ 25896b8a054SScott Wood | OR_FCM_EHTR ) 25996b8a054SScott Wood /* 0xFFFF8396 */ 260e4c09508SScott Wood 261e4c09508SScott Wood #ifdef CONFIG_NAND_U_BOOT 2626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 2646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 266e4c09508SScott Wood #else 2676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 2696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 271e4c09508SScott Wood #endif 272e4c09508SScott Wood 2736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 2746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 27596b8a054SScott Wood 2766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 2776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 278e4c09508SScott Wood 27996b8a054SScott Wood /* local bus read write buffer mapping */ 2806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ 2816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ 2826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xFA000000 2836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 28496b8a054SScott Wood 28589c7784eSTimur Tabi /* Vitesse 7385 */ 28689c7784eSTimur Tabi 2876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_VSC7385_BASE 0xF0000000 28889c7784eSTimur Tabi 28989c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 29089c7784eSTimur Tabi 2916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ 2926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ 2936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE/* Access window base at VSC7385 base */ 2946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ 29589c7784eSTimur Tabi 29689c7784eSTimur Tabi #endif 29789c7784eSTimur Tabi 29896b8a054SScott Wood /* pass open firmware flat tree */ 29935cc4e48SKim Phillips #define CONFIG_OF_LIBFDT 1 30096b8a054SScott Wood #define CONFIG_OF_BOARD_SETUP 1 3015b8bc606SKim Phillips #define CONFIG_OF_STDOUT_VIA_ALIAS 1 30296b8a054SScott Wood 30396b8a054SScott Wood /* 30496b8a054SScott Wood * Serial Port 30596b8a054SScott Wood */ 30696b8a054SScott Wood #define CONFIG_CONS_INDEX 1 3076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 31096b8a054SScott Wood 3116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 31296b8a054SScott Wood {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 31396b8a054SScott Wood 3146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 3156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 31696b8a054SScott Wood 31796b8a054SScott Wood /* Use the HUSH parser */ 3186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 3196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 32096b8a054SScott Wood 32196b8a054SScott Wood /* I2C */ 32296b8a054SScott Wood #define CONFIG_HARD_I2C /* I2C with hardware support*/ 32396b8a054SScott Wood #define CONFIG_FSL_I2C 32496b8a054SScott Wood #define CONFIG_I2C_MULTI_BUS 3256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 3266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 3276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 3286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 3296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 33096b8a054SScott Wood 33196b8a054SScott Wood /* 33296b8a054SScott Wood * General PCI 33396b8a054SScott Wood * Addresses are mapped 1-1. 33496b8a054SScott Wood */ 3356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 3376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 3386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 3396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 3406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 3426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 3436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 34496b8a054SScott Wood 34596b8a054SScott Wood #define CONFIG_PCI_PNP /* do pci plug-and-play */ 3466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 34796b8a054SScott Wood 34896b8a054SScott Wood /* 34989c7784eSTimur Tabi * TSEC 35096b8a054SScott Wood */ 35196b8a054SScott Wood #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 35296b8a054SScott Wood 35389c7784eSTimur Tabi #define CONFIG_NET_MULTI 35489c7784eSTimur Tabi #define CONFIG_GMII /* MII PHY management */ 35589c7784eSTimur Tabi 35689c7784eSTimur Tabi #ifdef CONFIG_TSEC1 35789c7784eSTimur Tabi #define CONFIG_HAS_ETH0 35889c7784eSTimur Tabi #define CONFIG_TSEC1_NAME "TSEC0" 3596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 36089c7784eSTimur Tabi #define TSEC1_PHY_ADDR 0x1c 36189c7784eSTimur Tabi #define TSEC1_FLAGS TSEC_GIGABIT 36289c7784eSTimur Tabi #define TSEC1_PHYIDX 0 36396b8a054SScott Wood #endif 36496b8a054SScott Wood 36589c7784eSTimur Tabi #ifdef CONFIG_TSEC2 36689c7784eSTimur Tabi #define CONFIG_HAS_ETH1 367255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 3686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 36996b8a054SScott Wood #define TSEC2_PHY_ADDR 4 3703a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 37196b8a054SScott Wood #define TSEC2_PHYIDX 0 37289c7784eSTimur Tabi #endif 37389c7784eSTimur Tabi 37496b8a054SScott Wood 37596b8a054SScott Wood /* Options are: TSEC[0-1] */ 37696b8a054SScott Wood #define CONFIG_ETHPRIME "TSEC1" 37796b8a054SScott Wood 37896b8a054SScott Wood /* 37996b8a054SScott Wood * Configure on-board RTC 38096b8a054SScott Wood */ 38196b8a054SScott Wood #define CONFIG_RTC_DS1337 3826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 38396b8a054SScott Wood 38496b8a054SScott Wood /* 38596b8a054SScott Wood * Environment 38696b8a054SScott Wood */ 387e4c09508SScott Wood #if defined(CONFIG_NAND_U_BOOT) 38851bfee19SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_NAND 1 3890e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET (512 * 1024) 3906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 3910e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 3920e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 3930e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 3940e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 3956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif !defined(CONFIG_SYS_RAMBOOT) 3965a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 3976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 3980e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 3990e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 40096b8a054SScott Wood 40196b8a054SScott Wood /* Address and size of Redundant Environment Sector */ 40296b8a054SScott Wood #else 40393f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 4046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4050e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 40696b8a054SScott Wood #endif 40796b8a054SScott Wood 40896b8a054SScott Wood #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 4096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 41096b8a054SScott Wood 4118ea5499aSJon Loeliger /* 412079a136cSJon Loeliger * BOOTP options 413079a136cSJon Loeliger */ 414079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 415079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTPATH 416079a136cSJon Loeliger #define CONFIG_BOOTP_GATEWAY 417079a136cSJon Loeliger #define CONFIG_BOOTP_HOSTNAME 418079a136cSJon Loeliger 419079a136cSJon Loeliger 420079a136cSJon Loeliger /* 4218ea5499aSJon Loeliger * Command line configuration. 4228ea5499aSJon Loeliger */ 4238ea5499aSJon Loeliger #include <config_cmd_default.h> 4248ea5499aSJon Loeliger 4258ea5499aSJon Loeliger #define CONFIG_CMD_PING 4268ea5499aSJon Loeliger #define CONFIG_CMD_DHCP 4278ea5499aSJon Loeliger #define CONFIG_CMD_I2C 4288ea5499aSJon Loeliger #define CONFIG_CMD_MII 4298ea5499aSJon Loeliger #define CONFIG_CMD_DATE 4308ea5499aSJon Loeliger #define CONFIG_CMD_PCI 4318ea5499aSJon Loeliger 4326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) 433bdab39d3SMike Frysinger #undef CONFIG_CMD_SAVEENV 4348ea5499aSJon Loeliger #undef CONFIG_CMD_LOADS 4358ea5499aSJon Loeliger #endif 43696b8a054SScott Wood 43796b8a054SScott Wood #define CONFIG_CMDLINE_EDITING 1 43896b8a054SScott Wood 43996b8a054SScott Wood 44096b8a054SScott Wood /* 44196b8a054SScott Wood * Miscellaneous configurable options 44296b8a054SScott Wood */ 4436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 4446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 4456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 4466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 44796b8a054SScott Wood 4486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 4496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 4506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 4516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 45296b8a054SScott Wood 45396b8a054SScott Wood /* 45496b8a054SScott Wood * For booting Linux, the board info and command line data 45596b8a054SScott Wood * have to be in the first 8 MB of memory, since this is 45696b8a054SScott Wood * the maximum mapped by the Linux kernel during initialization. 45796b8a054SScott Wood */ 4586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 45996b8a054SScott Wood 4606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 46196b8a054SScott Wood 4626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 46396b8a054SScott Wood 46496b8a054SScott Wood /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 46596b8a054SScott Wood /* 0x62040000 */ 4666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 46796b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 46896b8a054SScott Wood HRCWL_DDRCM |\ 46996b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 47096b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 47196b8a054SScott Wood HRCWL_CSB_TO_CLKIN_2X1 |\ 47296b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 47396b8a054SScott Wood 4746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 475e4c09508SScott Wood 4766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 47796b8a054SScott Wood 47896b8a054SScott Wood /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 47996b8a054SScott Wood /* 0x65040000 */ 4806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 48196b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 48296b8a054SScott Wood HRCWL_DDRCM |\ 48396b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 48496b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 48596b8a054SScott Wood HRCWL_CSB_TO_CLKIN_5X1 |\ 48696b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 48796b8a054SScott Wood 4886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 489e4c09508SScott Wood 49096b8a054SScott Wood #endif 49196b8a054SScott Wood 4926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH_BASE (\ 49396b8a054SScott Wood HRCWH_PCI_HOST |\ 49496b8a054SScott Wood HRCWH_PCI1_ARBITER_ENABLE |\ 49596b8a054SScott Wood HRCWH_CORE_ENABLE |\ 49696b8a054SScott Wood HRCWH_BOOTSEQ_DISABLE |\ 49796b8a054SScott Wood HRCWH_SW_WATCHDOG_DISABLE |\ 49896b8a054SScott Wood HRCWH_TSEC1M_IN_RGMII |\ 49996b8a054SScott Wood HRCWH_TSEC2M_IN_RGMII |\ 500e4c09508SScott Wood HRCWH_BIG_ENDIAN) 501e4c09508SScott Wood 502e4c09508SScott Wood #ifdef CONFIG_NAND_SPL 5036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 504e4c09508SScott Wood HRCWH_FROM_0XFFF00100 |\ 505e4c09508SScott Wood HRCWH_ROM_LOC_NAND_SP_8BIT |\ 506e4c09508SScott Wood HRCWH_RL_EXT_NAND) 507e4c09508SScott Wood #else 5086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 509e4c09508SScott Wood HRCWH_FROM_0X00000100 |\ 510e4c09508SScott Wood HRCWH_ROM_LOC_LOCAL_16BIT |\ 511e4c09508SScott Wood HRCWH_RL_EXT_LEGACY) 512e4c09508SScott Wood #endif 51396b8a054SScott Wood 51496b8a054SScott Wood /* System IO Config */ 5156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 5166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRL SICRL_USBDR /* Enable Internal USB Phy */ 51796b8a054SScott Wood 5186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_INIT 0x000000000 5196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 52096b8a054SScott Wood HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 52196b8a054SScott Wood 5226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 52396b8a054SScott Wood 52431d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 52531d82672SBecky Bruce 52696b8a054SScott Wood /* DDR @ 0x00000000 */ 5276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) 5286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 52996b8a054SScott Wood 53096b8a054SScott Wood /* PCI @ 0x80000000 */ 5316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) 5326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 5336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 5346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 53596b8a054SScott Wood 53696b8a054SScott Wood /* PCI2 not supported on 8313 */ 5376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L (0) 5386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U (0) 5396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L (0) 5406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U (0) 54196b8a054SScott Wood 54296b8a054SScott Wood /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 5436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 5446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 54596b8a054SScott Wood 54696b8a054SScott Wood /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 547c1230980SScott Wood #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) 5486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 54996b8a054SScott Wood 5506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L (0) 5516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U (0) 55296b8a054SScott Wood 5536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 5546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 5556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 5566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 5576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 5586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 5596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 5606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 5616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 5626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 5636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 5646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 5656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 5666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 5676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 5686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 56996b8a054SScott Wood 57096b8a054SScott Wood /* 57196b8a054SScott Wood * Internal Definitions 57296b8a054SScott Wood * 57396b8a054SScott Wood * Boot Flags 57496b8a054SScott Wood */ 57596b8a054SScott Wood #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 57696b8a054SScott Wood #define BOOTFLAG_WARM 0x02 /* Software reboot */ 57796b8a054SScott Wood 57896b8a054SScott Wood /* 57996b8a054SScott Wood * Environment Configuration 58096b8a054SScott Wood */ 58196b8a054SScott Wood #define CONFIG_ENV_OVERWRITE 58296b8a054SScott Wood 58396b8a054SScott Wood #define CONFIG_ETHADDR 00:E0:0C:00:95:01 58496b8a054SScott Wood #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 58596b8a054SScott Wood 58696b8a054SScott Wood #define CONFIG_IPADDR 10.0.0.2 58796b8a054SScott Wood #define CONFIG_SERVERIP 10.0.0.1 58896b8a054SScott Wood #define CONFIG_GATEWAYIP 10.0.0.1 58996b8a054SScott Wood #define CONFIG_NETMASK 255.0.0.0 59096b8a054SScott Wood #define CONFIG_NETDEV eth1 59196b8a054SScott Wood 59296b8a054SScott Wood #define CONFIG_HOSTNAME mpc8313erdb 59396b8a054SScott Wood #define CONFIG_ROOTPATH /nfs/root/path 59496b8a054SScott Wood #define CONFIG_BOOTFILE uImage 59596b8a054SScott Wood #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 59696b8a054SScott Wood #define CONFIG_FDTFILE mpc8313erdb.dtb 59796b8a054SScott Wood 598b2115757SKim Phillips #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ 5997fd0bea2SKim Phillips #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 60096b8a054SScott Wood #define CONFIG_BAUDRATE 115200 60196b8a054SScott Wood 60296b8a054SScott Wood #define XMK_STR(x) #x 60396b8a054SScott Wood #define MK_STR(x) XMK_STR(x) 60496b8a054SScott Wood 60596b8a054SScott Wood #define CONFIG_EXTRA_ENV_SETTINGS \ 60696b8a054SScott Wood "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 60796b8a054SScott Wood "ethprime=TSEC1\0" \ 60896b8a054SScott Wood "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 60996b8a054SScott Wood "tftpflash=tftpboot $loadaddr $uboot; " \ 61096b8a054SScott Wood "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 61196b8a054SScott Wood "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 61296b8a054SScott Wood "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 61396b8a054SScott Wood "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 61496b8a054SScott Wood "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 61596b8a054SScott Wood "fdtaddr=400000\0" \ 61696b8a054SScott Wood "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 61796b8a054SScott Wood "console=ttyS0\0" \ 61896b8a054SScott Wood "setbootargs=setenv bootargs " \ 61996b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 62096b8a054SScott Wood "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 62196b8a054SScott Wood "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 62296b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 62396b8a054SScott Wood 62496b8a054SScott Wood #define CONFIG_NFSBOOTCOMMAND \ 62596b8a054SScott Wood "setenv rootdev /dev/nfs;" \ 62696b8a054SScott Wood "run setbootargs;" \ 62796b8a054SScott Wood "run setipargs;" \ 62896b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 62996b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 63096b8a054SScott Wood "bootm $loadaddr - $fdtaddr" 63196b8a054SScott Wood 63296b8a054SScott Wood #define CONFIG_RAMBOOTCOMMAND \ 63396b8a054SScott Wood "setenv rootdev /dev/ram;" \ 63496b8a054SScott Wood "run setbootargs;" \ 63596b8a054SScott Wood "tftp $ramdiskaddr $ramdiskfile;" \ 63696b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 63796b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 63896b8a054SScott Wood "bootm $loadaddr $ramdiskaddr $fdtaddr" 63996b8a054SScott Wood 64096b8a054SScott Wood #undef MK_STR 64196b8a054SScott Wood #undef XMK_STR 64296b8a054SScott Wood 64396b8a054SScott Wood #endif /* __CONFIG_H */ 644