196b8a054SScott Wood /* 2e8d3ca8bSScott Wood * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 396b8a054SScott Wood * 496b8a054SScott Wood * See file CREDITS for list of people who contributed to this 596b8a054SScott Wood * project. 696b8a054SScott Wood * 796b8a054SScott Wood * This program is free software; you can redistribute it and/or 896b8a054SScott Wood * modify it under the terms of the GNU General Public License as 996b8a054SScott Wood * published by the Free Software Foundation; either version 2 of 1096b8a054SScott Wood * the License, or (at your option) any later version. 1196b8a054SScott Wood * 1296b8a054SScott Wood * This program is distributed in the hope that it will be useful, 1396b8a054SScott Wood * but WITHOUT ANY WARRANTY; without even the implied warranty of 1496b8a054SScott Wood * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1596b8a054SScott Wood * GNU General Public License for more details. 1696b8a054SScott Wood * 1796b8a054SScott Wood * You should have received a copy of the GNU General Public License 1896b8a054SScott Wood * along with this program; if not, write to the Free Software 1996b8a054SScott Wood * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 2096b8a054SScott Wood * MA 02111-1307 USA 2196b8a054SScott Wood */ 2296b8a054SScott Wood /* 2396b8a054SScott Wood * mpc8313epb board configuration file 2496b8a054SScott Wood */ 2596b8a054SScott Wood 2696b8a054SScott Wood #ifndef __CONFIG_H 2796b8a054SScott Wood #define __CONFIG_H 2896b8a054SScott Wood 2996b8a054SScott Wood /* 3096b8a054SScott Wood * High Level Configuration Options 3196b8a054SScott Wood */ 3296b8a054SScott Wood #define CONFIG_E300 1 330f898604SPeter Tyser #define CONFIG_MPC83xx 1 342c7920afSPeter Tyser #define CONFIG_MPC831x 1 3596b8a054SScott Wood #define CONFIG_MPC8313 1 3696b8a054SScott Wood #define CONFIG_MPC8313ERDB 1 3796b8a054SScott Wood 38f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 39f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 40f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 41f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 42f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 43f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 44f1c574d4SScott Wood 45f1c574d4SScott Wood #ifdef CONFIG_NAND_U_BOOT 46f1c574d4SScott Wood #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 47f1c574d4SScott Wood #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 48f1c574d4SScott Wood #ifdef CONFIG_NAND_SPL 49f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 50f1c574d4SScott Wood #endif /* CONFIG_NAND_SPL */ 51f1c574d4SScott Wood #endif /* CONFIG_NAND_U_BOOT */ 52f1c574d4SScott Wood 532ae18241SWolfgang Denk #ifndef CONFIG_SYS_TEXT_BASE 542ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFE000000 552ae18241SWolfgang Denk #endif 562ae18241SWolfgang Denk 57f1c574d4SScott Wood #ifndef CONFIG_SYS_MONITOR_BASE 58f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 59f1c574d4SScott Wood #endif 60f1c574d4SScott Wood 6196b8a054SScott Wood #define CONFIG_PCI 620914f483SBecky Bruce #define CONFIG_FSL_ELBC 1 6396b8a054SScott Wood 6489c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 6589c7784eSTimur Tabi 6689c7784eSTimur Tabi /* 6789c7784eSTimur Tabi * On-board devices 684ce1e23bSYork Sun * 694ce1e23bSYork Sun * TSEC1 is VSC switch 704ce1e23bSYork Sun * TSEC2 is SoC TSEC 7189c7784eSTimur Tabi */ 7289c7784eSTimur Tabi #define CONFIG_VSC7385_ENET 734ce1e23bSYork Sun #define CONFIG_TSEC2 7489c7784eSTimur Tabi 756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 765c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 785c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 7996b8a054SScott Wood #else 8096b8a054SScott Wood #error Unknown oscillator frequency. 8196b8a054SScott Wood #endif 8296b8a054SScott Wood 8396b8a054SScott Wood #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 8496b8a054SScott Wood 8596b8a054SScott Wood #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 8696b8a054SScott Wood 876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 8896b8a054SScott Wood 89e4c09508SScott Wood #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 91e4c09508SScott Wood #endif 92e4c09508SScott Wood 936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00001000 946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x07f00000 9596b8a054SScott Wood 9696b8a054SScott Wood /* Early revs of this board will lock up hard when attempting 9796b8a054SScott Wood * to access the PMC registers, unless a JTAG debugger is 9896b8a054SScott Wood * connected, or some resistor modifications are made. 9996b8a054SScott Wood */ 1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 10196b8a054SScott Wood 1026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 1036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 10496b8a054SScott Wood 10596b8a054SScott Wood /* 10689c7784eSTimur Tabi * Device configurations 10789c7784eSTimur Tabi */ 10889c7784eSTimur Tabi 10989c7784eSTimur Tabi /* Vitesse 7385 */ 11089c7784eSTimur Tabi 11189c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 11289c7784eSTimur Tabi 1134ce1e23bSYork Sun #define CONFIG_TSEC1 11489c7784eSTimur Tabi 11589c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 11689c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFE7FE000 11789c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 11889c7784eSTimur Tabi 11989c7784eSTimur Tabi #endif 12089c7784eSTimur Tabi 12189c7784eSTimur Tabi /* 12296b8a054SScott Wood * DDR Setup 12396b8a054SScott Wood */ 1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 12796b8a054SScott Wood 12896b8a054SScott Wood /* 12996b8a054SScott Wood * Manually set up DDR parameters, as this board does not 13096b8a054SScott Wood * seem to have the SPD connected to I2C. 13196b8a054SScott Wood */ 1326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 1336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \ 134*2fef4020SJoe Hershberger | CSCONFIG_ODT_RD_NEVER \ 135*2fef4020SJoe Hershberger | CSCONFIG_ODT_WR_ONLY_CURRENT \ 136261c07bcSJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 137261c07bcSJoe Hershberger | CSCONFIG_COL_BIT_10) 138e1d8ed2cSPoonam Aggrwal /* 0x80010102 */ 13996b8a054SScott Wood 1406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_3 0x00000000 1416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 14296b8a054SScott Wood | (0 << TIMING_CFG0_WRT_SHIFT) \ 14396b8a054SScott Wood | (0 << TIMING_CFG0_RRT_SHIFT) \ 14496b8a054SScott Wood | (0 << TIMING_CFG0_WWT_SHIFT) \ 14596b8a054SScott Wood | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 14696b8a054SScott Wood | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 14796b8a054SScott Wood | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 14896b8a054SScott Wood | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 14996b8a054SScott Wood /* 0x00220802 */ 1506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 151e1d8ed2cSPoonam Aggrwal | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 15296b8a054SScott Wood | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 15396b8a054SScott Wood | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 154e1d8ed2cSPoonam Aggrwal | (10 << TIMING_CFG1_REFREC_SHIFT) \ 15596b8a054SScott Wood | (3 << TIMING_CFG1_WRREC_SHIFT) \ 15696b8a054SScott Wood | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 15796b8a054SScott Wood | (2 << TIMING_CFG1_WRTORD_SHIFT)) 158e1d8ed2cSPoonam Aggrwal /* 0x3835a322 */ 1596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 160e1d8ed2cSPoonam Aggrwal | (5 << TIMING_CFG2_CPO_SHIFT) \ 16196b8a054SScott Wood | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 16296b8a054SScott Wood | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 16396b8a054SScott Wood | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 16496b8a054SScott Wood | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 165e1d8ed2cSPoonam Aggrwal | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 166e1d8ed2cSPoonam Aggrwal /* 0x129048c6 */ /* P9-45,may need tuning */ 1676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 168e1d8ed2cSPoonam Aggrwal | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 169e1d8ed2cSPoonam Aggrwal /* 0x05100500 */ 17096b8a054SScott Wood #if defined(CONFIG_DDR_2T_TIMING) 1716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 172bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 173*2fef4020SJoe Hershberger | SDRAM_CFG_DBW_32 \ 174*2fef4020SJoe Hershberger | SDRAM_CFG_2T_EN) 175*2fef4020SJoe Hershberger /* 0x43088000 */ 17696b8a054SScott Wood #else 1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 178bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 179*2fef4020SJoe Hershberger | SDRAM_CFG_DBW_32) 18096b8a054SScott Wood /* 0x43080000 */ 18196b8a054SScott Wood #endif 1826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG2 0x00401000 18396b8a054SScott Wood /* set burst length to 8 for 32-bit data path */ 1846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 185e1d8ed2cSPoonam Aggrwal | (0x0632 << SDRAM_MODE_SD_SHIFT)) 186e1d8ed2cSPoonam Aggrwal /* 0x44480632 */ 1876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x8000C000 18896b8a054SScott Wood 1896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 19096b8a054SScott Wood /*0x02000000*/ 1916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 19296b8a054SScott Wood | DDRCDR_PZ_NOMZ \ 19396b8a054SScott Wood | DDRCDR_NZ_NOMZ \ 19496b8a054SScott Wood | DDRCDR_M_ODR) 19596b8a054SScott Wood 19696b8a054SScott Wood /* 19796b8a054SScott Wood * FLASH on the Local Bus 19896b8a054SScott Wood */ 1996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 20000b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 2016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 2036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 20696b8a054SScott Wood 207261c07bcSJoe Hershberger #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 208261c07bcSJoe Hershberger | (2 << BR_PS_SHIFT) /* 16 bit port */ \ 209261c07bcSJoe Hershberger | BR_V) /* valid */ 2106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NOR_OR_PRELIM (0xFF800000 /* 8 MByte */ \ 21196b8a054SScott Wood | OR_GPCM_XACS \ 21296b8a054SScott Wood | OR_GPCM_SCY_9 \ 21396b8a054SScott Wood | OR_GPCM_EHTR \ 21496b8a054SScott Wood | OR_GPCM_EAD) 21596b8a054SScott Wood /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 216261c07bcSJoe Hershberger /* window base at flash base */ 217261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ 21996b8a054SScott Wood 2206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 22296b8a054SScott Wood 2236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 22596b8a054SScott Wood 226261c07bcSJoe Hershberger #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 227261c07bcSJoe Hershberger !defined(CONFIG_NAND_SPL) 2286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 22996b8a054SScott Wood #endif 23096b8a054SScott Wood 2316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 232261c07bcSJoe Hershberger #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 233553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 23496b8a054SScott Wood 235261c07bcSJoe Hershberger #define CONFIG_SYS_GBL_DATA_OFFSET \ 236261c07bcSJoe Hershberger (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 23896b8a054SScott Wood 2396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 2404a9932a4SKim Phillips #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 2416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 24296b8a054SScott Wood 24396b8a054SScott Wood /* 24496b8a054SScott Wood * Local Bus LCRR and LBCR regs 24596b8a054SScott Wood */ 246c7190f02SKim Phillips #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 247c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 2486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 24996b8a054SScott Wood | (0xFF << LBCR_BMT_SHIFT) \ 25096b8a054SScott Wood | 0xF) /* 0x0004ff0f */ 25196b8a054SScott Wood 252261c07bcSJoe Hershberger /* LB refresh timer prescal, 266MHz/32 */ 253261c07bcSJoe Hershberger #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 25496b8a054SScott Wood 2557817cb20SMarcel Ziswiler /* drivers/mtd/nand/nand.c */ 256e4c09508SScott Wood #ifdef CONFIG_NAND_SPL 2576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xFFF00000 258e4c09508SScott Wood #else 2596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xE2800000 260e4c09508SScott Wood #endif 261e4c09508SScott Wood 262e8d3ca8bSScott Wood #define CONFIG_MTD_DEVICE 263e8d3ca8bSScott Wood #define CONFIG_MTD_PARTITION 264e8d3ca8bSScott Wood #define CONFIG_CMD_MTDPARTS 265e8d3ca8bSScott Wood #define MTDIDS_DEFAULT "nand0=e2800000.flash" 266e8d3ca8bSScott Wood #define MTDPARTS_DEFAULT \ 267e8d3ca8bSScott Wood "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" 268e8d3ca8bSScott Wood 2696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_NAND_DEVICE 1 27096b8a054SScott Wood #define CONFIG_MTD_NAND_VERIFY_WRITE 271acdab5c3SScott Wood #define CONFIG_CMD_NAND 1 272acdab5c3SScott Wood #define CONFIG_NAND_FSL_ELBC 1 2736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 27496b8a054SScott Wood 275e4c09508SScott Wood 2766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 27796b8a054SScott Wood | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 278261c07bcSJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 27996b8a054SScott Wood | BR_MS_FCM /* MSEL = FCM */ \ 28096b8a054SScott Wood | BR_V) /* valid */ 2816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \ 28296b8a054SScott Wood | OR_FCM_CSCT \ 28396b8a054SScott Wood | OR_FCM_CST \ 28496b8a054SScott Wood | OR_FCM_CHT \ 28596b8a054SScott Wood | OR_FCM_SCY_1 \ 28696b8a054SScott Wood | OR_FCM_TRLX \ 28796b8a054SScott Wood | OR_FCM_EHTR) 28896b8a054SScott Wood /* 0xFFFF8396 */ 289e4c09508SScott Wood 290e4c09508SScott Wood #ifdef CONFIG_NAND_U_BOOT 2916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 2936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 295e4c09508SScott Wood #else 2966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 2986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 300e4c09508SScott Wood #endif 301e4c09508SScott Wood 3026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 3036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 30496b8a054SScott Wood 3056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 3066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 307e4c09508SScott Wood 30896b8a054SScott Wood /* local bus read write buffer mapping */ 3096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ 3106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ 3116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xFA000000 3126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 31396b8a054SScott Wood 31489c7784eSTimur Tabi /* Vitesse 7385 */ 31589c7784eSTimur Tabi 3166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_VSC7385_BASE 0xF0000000 31789c7784eSTimur Tabi 31889c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 31989c7784eSTimur Tabi 320261c07bcSJoe Hershberger /* VSC7385 Base address */ 321261c07bcSJoe Hershberger #define CONFIG_SYS_BR2_PRELIM 0xf0000801 322261c07bcSJoe Hershberger /* VSC7385, 128K bytes*/ 323261c07bcSJoe Hershberger #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff 324261c07bcSJoe Hershberger /* Access window base at VSC7385 base */ 325261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 326261c07bcSJoe Hershberger /* Access window size 128K */ 327261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 32889c7784eSTimur Tabi 32989c7784eSTimur Tabi #endif 33089c7784eSTimur Tabi 33196b8a054SScott Wood /* pass open firmware flat tree */ 33235cc4e48SKim Phillips #define CONFIG_OF_LIBFDT 1 33396b8a054SScott Wood #define CONFIG_OF_BOARD_SETUP 1 3345b8bc606SKim Phillips #define CONFIG_OF_STDOUT_VIA_ALIAS 1 33596b8a054SScott Wood 33696b8a054SScott Wood /* 33796b8a054SScott Wood * Serial Port 33896b8a054SScott Wood */ 33996b8a054SScott Wood #define CONFIG_CONS_INDEX 1 3406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 34396b8a054SScott Wood 3446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 34596b8a054SScott Wood {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 34696b8a054SScott Wood 3476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 3486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 34996b8a054SScott Wood 35096b8a054SScott Wood /* Use the HUSH parser */ 3516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 3526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 35396b8a054SScott Wood 35496b8a054SScott Wood /* I2C */ 35596b8a054SScott Wood #define CONFIG_HARD_I2C /* I2C with hardware support*/ 35696b8a054SScott Wood #define CONFIG_FSL_I2C 35796b8a054SScott Wood #define CONFIG_I2C_MULTI_BUS 3586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 3596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 3606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ 3616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 3626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 36396b8a054SScott Wood 36496b8a054SScott Wood /* 36596b8a054SScott Wood * General PCI 36696b8a054SScott Wood * Addresses are mapped 1-1. 36796b8a054SScott Wood */ 3686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 3706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 3716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 3726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 3736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 3756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 3766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 37796b8a054SScott Wood 37896b8a054SScott Wood #define CONFIG_PCI_PNP /* do pci plug-and-play */ 3796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 38096b8a054SScott Wood 38196b8a054SScott Wood /* 38289c7784eSTimur Tabi * TSEC 38396b8a054SScott Wood */ 38496b8a054SScott Wood #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 38596b8a054SScott Wood 38689c7784eSTimur Tabi #define CONFIG_GMII /* MII PHY management */ 38789c7784eSTimur Tabi 38889c7784eSTimur Tabi #ifdef CONFIG_TSEC1 38989c7784eSTimur Tabi #define CONFIG_HAS_ETH0 39089c7784eSTimur Tabi #define CONFIG_TSEC1_NAME "TSEC0" 3916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 39289c7784eSTimur Tabi #define TSEC1_PHY_ADDR 0x1c 39389c7784eSTimur Tabi #define TSEC1_FLAGS TSEC_GIGABIT 39489c7784eSTimur Tabi #define TSEC1_PHYIDX 0 39596b8a054SScott Wood #endif 39696b8a054SScott Wood 39789c7784eSTimur Tabi #ifdef CONFIG_TSEC2 39889c7784eSTimur Tabi #define CONFIG_HAS_ETH1 399255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 4006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 40196b8a054SScott Wood #define TSEC2_PHY_ADDR 4 4023a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 40396b8a054SScott Wood #define TSEC2_PHYIDX 0 40489c7784eSTimur Tabi #endif 40589c7784eSTimur Tabi 40696b8a054SScott Wood 40796b8a054SScott Wood /* Options are: TSEC[0-1] */ 40896b8a054SScott Wood #define CONFIG_ETHPRIME "TSEC1" 40996b8a054SScott Wood 41096b8a054SScott Wood /* 41196b8a054SScott Wood * Configure on-board RTC 41296b8a054SScott Wood */ 41396b8a054SScott Wood #define CONFIG_RTC_DS1337 4146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 41596b8a054SScott Wood 41696b8a054SScott Wood /* 41796b8a054SScott Wood * Environment 41896b8a054SScott Wood */ 419e4c09508SScott Wood #if defined(CONFIG_NAND_U_BOOT) 42051bfee19SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_NAND 1 4210e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET (512 * 1024) 4226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 4230e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 4240e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 4250e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 426261c07bcSJoe Hershberger #define CONFIG_ENV_OFFSET_REDUND \ 427261c07bcSJoe Hershberger (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 4286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif !defined(CONFIG_SYS_RAMBOOT) 4295a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 430261c07bcSJoe Hershberger #define CONFIG_ENV_ADDR \ 431261c07bcSJoe Hershberger (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4320e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 4330e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 43496b8a054SScott Wood 43596b8a054SScott Wood /* Address and size of Redundant Environment Sector */ 43696b8a054SScott Wood #else 43793f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 4386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4390e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 44096b8a054SScott Wood #endif 44196b8a054SScott Wood 44296b8a054SScott Wood #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 4436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 44496b8a054SScott Wood 4458ea5499aSJon Loeliger /* 446079a136cSJon Loeliger * BOOTP options 447079a136cSJon Loeliger */ 448079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 449079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTPATH 450079a136cSJon Loeliger #define CONFIG_BOOTP_GATEWAY 451079a136cSJon Loeliger #define CONFIG_BOOTP_HOSTNAME 452079a136cSJon Loeliger 453079a136cSJon Loeliger 454079a136cSJon Loeliger /* 4558ea5499aSJon Loeliger * Command line configuration. 4568ea5499aSJon Loeliger */ 4578ea5499aSJon Loeliger #include <config_cmd_default.h> 4588ea5499aSJon Loeliger 4598ea5499aSJon Loeliger #define CONFIG_CMD_PING 4608ea5499aSJon Loeliger #define CONFIG_CMD_DHCP 4618ea5499aSJon Loeliger #define CONFIG_CMD_I2C 4628ea5499aSJon Loeliger #define CONFIG_CMD_MII 4638ea5499aSJon Loeliger #define CONFIG_CMD_DATE 4648ea5499aSJon Loeliger #define CONFIG_CMD_PCI 4658ea5499aSJon Loeliger 4666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) 467bdab39d3SMike Frysinger #undef CONFIG_CMD_SAVEENV 4688ea5499aSJon Loeliger #undef CONFIG_CMD_LOADS 4698ea5499aSJon Loeliger #endif 47096b8a054SScott Wood 47196b8a054SScott Wood #define CONFIG_CMDLINE_EDITING 1 472a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 47396b8a054SScott Wood 47496b8a054SScott Wood /* 47596b8a054SScott Wood * Miscellaneous configurable options 47696b8a054SScott Wood */ 4776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 4786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 4796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 4806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 48196b8a054SScott Wood 482261c07bcSJoe Hershberger /* Print Buffer Size */ 483261c07bcSJoe Hershberger #define CONFIG_SYS_PBSIZE \ 484261c07bcSJoe Hershberger (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 4856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 486261c07bcSJoe Hershberger /* Boot Argument Buffer Size */ 487261c07bcSJoe Hershberger #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 4886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 48996b8a054SScott Wood 49096b8a054SScott Wood /* 49196b8a054SScott Wood * For booting Linux, the board info and command line data 4929f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 49396b8a054SScott Wood * the maximum mapped by the Linux kernel during initialization. 49496b8a054SScott Wood */ 495261c07bcSJoe Hershberger /* Initial Memory map for Linux*/ 496261c07bcSJoe Hershberger #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 49796b8a054SScott Wood 4986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 49996b8a054SScott Wood 5006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 50196b8a054SScott Wood 50296b8a054SScott Wood /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 50396b8a054SScott Wood /* 0x62040000 */ 5046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 50596b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 50696b8a054SScott Wood HRCWL_DDRCM |\ 50796b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 50896b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 50996b8a054SScott Wood HRCWL_CSB_TO_CLKIN_2X1 |\ 51096b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 51196b8a054SScott Wood 5126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 513e4c09508SScott Wood 5146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 51596b8a054SScott Wood 51696b8a054SScott Wood /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 51796b8a054SScott Wood /* 0x65040000 */ 5186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 51996b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 52096b8a054SScott Wood HRCWL_DDRCM |\ 52196b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 52296b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 52396b8a054SScott Wood HRCWL_CSB_TO_CLKIN_5X1 |\ 52496b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 52596b8a054SScott Wood 5266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 527e4c09508SScott Wood 52896b8a054SScott Wood #endif 52996b8a054SScott Wood 5306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH_BASE (\ 53196b8a054SScott Wood HRCWH_PCI_HOST |\ 53296b8a054SScott Wood HRCWH_PCI1_ARBITER_ENABLE |\ 53396b8a054SScott Wood HRCWH_CORE_ENABLE |\ 53496b8a054SScott Wood HRCWH_BOOTSEQ_DISABLE |\ 53596b8a054SScott Wood HRCWH_SW_WATCHDOG_DISABLE |\ 53696b8a054SScott Wood HRCWH_TSEC1M_IN_RGMII |\ 53796b8a054SScott Wood HRCWH_TSEC2M_IN_RGMII |\ 538e4c09508SScott Wood HRCWH_BIG_ENDIAN) 539e4c09508SScott Wood 540e4c09508SScott Wood #ifdef CONFIG_NAND_SPL 5416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 542e4c09508SScott Wood HRCWH_FROM_0XFFF00100 |\ 543e4c09508SScott Wood HRCWH_ROM_LOC_NAND_SP_8BIT |\ 544e4c09508SScott Wood HRCWH_RL_EXT_NAND) 545e4c09508SScott Wood #else 5466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 547e4c09508SScott Wood HRCWH_FROM_0X00000100 |\ 548e4c09508SScott Wood HRCWH_ROM_LOC_LOCAL_16BIT |\ 549e4c09508SScott Wood HRCWH_RL_EXT_LEGACY) 550e4c09508SScott Wood #endif 55196b8a054SScott Wood 55296b8a054SScott Wood /* System IO Config */ 5536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 554f986325dSRon Madrid #define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */ 55596b8a054SScott Wood 5566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_INIT 0x000000000 5576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 5581a2e203bSKim Phillips HID0_ENABLE_INSTRUCTION_CACHE | \ 55996b8a054SScott Wood HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 56096b8a054SScott Wood 5616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 56296b8a054SScott Wood 56331d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 56431d82672SBecky Bruce 56596b8a054SScott Wood /* DDR @ 0x00000000 */ 56672cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 567261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 568261c07bcSJoe Hershberger | BATU_BL_256M \ 569261c07bcSJoe Hershberger | BATU_VS \ 570261c07bcSJoe Hershberger | BATU_VP) 57196b8a054SScott Wood 57296b8a054SScott Wood /* PCI @ 0x80000000 */ 57372cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 574261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 575261c07bcSJoe Hershberger | BATU_BL_256M \ 576261c07bcSJoe Hershberger | BATU_VS \ 577261c07bcSJoe Hershberger | BATU_VP) 578261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 57972cd4087SJoe Hershberger | BATL_PP_RW \ 580261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 581261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 582261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 583261c07bcSJoe Hershberger | BATU_BL_256M \ 584261c07bcSJoe Hershberger | BATU_VS \ 585261c07bcSJoe Hershberger | BATU_VP) 58696b8a054SScott Wood 58796b8a054SScott Wood /* PCI2 not supported on 8313 */ 5886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L (0) 5896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U (0) 5906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L (0) 5916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U (0) 59296b8a054SScott Wood 59396b8a054SScott Wood /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 594261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 59572cd4087SJoe Hershberger | BATL_PP_RW \ 596261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 597261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 598261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 599261c07bcSJoe Hershberger | BATU_BL_256M \ 600261c07bcSJoe Hershberger | BATU_VS \ 601261c07bcSJoe Hershberger | BATU_VP) 60296b8a054SScott Wood 60396b8a054SScott Wood /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 60472cd4087SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 6056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 60696b8a054SScott Wood 6076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L (0) 6086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U (0) 60996b8a054SScott Wood 6106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 6116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 6126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 6136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 6146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 6156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 6166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 6176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 6186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 6196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 6206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 6216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 6226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 6236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 6246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 6256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 62696b8a054SScott Wood 62796b8a054SScott Wood /* 62896b8a054SScott Wood * Environment Configuration 62996b8a054SScott Wood */ 63096b8a054SScott Wood #define CONFIG_ENV_OVERWRITE 63196b8a054SScott Wood 632261c07bcSJoe Hershberger #define CONFIG_NETDEV "eth1" 63396b8a054SScott Wood 63496b8a054SScott Wood #define CONFIG_HOSTNAME mpc8313erdb 6358b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfs/root/path" 636b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 637261c07bcSJoe Hershberger /* U-Boot image on TFTP server */ 638261c07bcSJoe Hershberger #define CONFIG_UBOOTPATH "u-boot.bin" 639261c07bcSJoe Hershberger #define CONFIG_FDTFILE "mpc8313erdb.dtb" 64096b8a054SScott Wood 641261c07bcSJoe Hershberger /* default location for tftp and bootm */ 642261c07bcSJoe Hershberger #define CONFIG_LOADADDR 800000 6437fd0bea2SKim Phillips #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 64496b8a054SScott Wood #define CONFIG_BAUDRATE 115200 64596b8a054SScott Wood 64696b8a054SScott Wood #define XMK_STR(x) #x 64796b8a054SScott Wood #define MK_STR(x) XMK_STR(x) 64896b8a054SScott Wood 64996b8a054SScott Wood #define CONFIG_EXTRA_ENV_SETTINGS \ 650261c07bcSJoe Hershberger "netdev=" CONFIG_NETDEV "\0" \ 65196b8a054SScott Wood "ethprime=TSEC1\0" \ 652261c07bcSJoe Hershberger "uboot=" CONFIG_UBOOTPATH "\0" \ 65396b8a054SScott Wood "tftpflash=tftpboot $loadaddr $uboot; " \ 65414d0a02aSWolfgang Denk "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 65514d0a02aSWolfgang Denk "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 65614d0a02aSWolfgang Denk "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\ 65714d0a02aSWolfgang Denk "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 65814d0a02aSWolfgang Denk "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\ 65979f516bcSKim Phillips "fdtaddr=780000\0" \ 660261c07bcSJoe Hershberger "fdtfile=" CONFIG_FDTFILE "\0" \ 66196b8a054SScott Wood "console=ttyS0\0" \ 66296b8a054SScott Wood "setbootargs=setenv bootargs " \ 66396b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 66496b8a054SScott Wood "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 665261c07bcSJoe Hershberger "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 666261c07bcSJoe Hershberger "$netdev:off " \ 66796b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 66896b8a054SScott Wood 66996b8a054SScott Wood #define CONFIG_NFSBOOTCOMMAND \ 67096b8a054SScott Wood "setenv rootdev /dev/nfs;" \ 67196b8a054SScott Wood "run setbootargs;" \ 67296b8a054SScott Wood "run setipargs;" \ 67396b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 67496b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 67596b8a054SScott Wood "bootm $loadaddr - $fdtaddr" 67696b8a054SScott Wood 67796b8a054SScott Wood #define CONFIG_RAMBOOTCOMMAND \ 67896b8a054SScott Wood "setenv rootdev /dev/ram;" \ 67996b8a054SScott Wood "run setbootargs;" \ 68096b8a054SScott Wood "tftp $ramdiskaddr $ramdiskfile;" \ 68196b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 68296b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 68396b8a054SScott Wood "bootm $loadaddr $ramdiskaddr $fdtaddr" 68496b8a054SScott Wood 68596b8a054SScott Wood #undef MK_STR 68696b8a054SScott Wood #undef XMK_STR 68796b8a054SScott Wood 68896b8a054SScott Wood #endif /* __CONFIG_H */ 689