196b8a054SScott Wood /* 2e8d3ca8bSScott Wood * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 396b8a054SScott Wood * 496b8a054SScott Wood * See file CREDITS for list of people who contributed to this 596b8a054SScott Wood * project. 696b8a054SScott Wood * 796b8a054SScott Wood * This program is free software; you can redistribute it and/or 896b8a054SScott Wood * modify it under the terms of the GNU General Public License as 996b8a054SScott Wood * published by the Free Software Foundation; either version 2 of 1096b8a054SScott Wood * the License, or (at your option) any later version. 1196b8a054SScott Wood * 1296b8a054SScott Wood * This program is distributed in the hope that it will be useful, 1396b8a054SScott Wood * but WITHOUT ANY WARRANTY; without even the implied warranty of 1496b8a054SScott Wood * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1596b8a054SScott Wood * GNU General Public License for more details. 1696b8a054SScott Wood * 1796b8a054SScott Wood * You should have received a copy of the GNU General Public License 1896b8a054SScott Wood * along with this program; if not, write to the Free Software 1996b8a054SScott Wood * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 2096b8a054SScott Wood * MA 02111-1307 USA 2196b8a054SScott Wood */ 2296b8a054SScott Wood /* 2396b8a054SScott Wood * mpc8313epb board configuration file 2496b8a054SScott Wood */ 2596b8a054SScott Wood 2696b8a054SScott Wood #ifndef __CONFIG_H 2796b8a054SScott Wood #define __CONFIG_H 2896b8a054SScott Wood 2996b8a054SScott Wood /* 3096b8a054SScott Wood * High Level Configuration Options 3196b8a054SScott Wood */ 3296b8a054SScott Wood #define CONFIG_E300 1 330f898604SPeter Tyser #define CONFIG_MPC83xx 1 342c7920afSPeter Tyser #define CONFIG_MPC831x 1 3596b8a054SScott Wood #define CONFIG_MPC8313 1 3696b8a054SScott Wood #define CONFIG_MPC8313ERDB 1 3796b8a054SScott Wood 38f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 39f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 40f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 41f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 42f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 43f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 44f1c574d4SScott Wood 45f1c574d4SScott Wood #ifdef CONFIG_NAND_U_BOOT 46f1c574d4SScott Wood #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 47f1c574d4SScott Wood #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 48f1c574d4SScott Wood #ifdef CONFIG_NAND_SPL 49f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 50f1c574d4SScott Wood #endif /* CONFIG_NAND_SPL */ 51f1c574d4SScott Wood #endif /* CONFIG_NAND_U_BOOT */ 52f1c574d4SScott Wood 532ae18241SWolfgang Denk #ifndef CONFIG_SYS_TEXT_BASE 542ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFE000000 552ae18241SWolfgang Denk #endif 562ae18241SWolfgang Denk 57f1c574d4SScott Wood #ifndef CONFIG_SYS_MONITOR_BASE 58f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 59f1c574d4SScott Wood #endif 60f1c574d4SScott Wood 6196b8a054SScott Wood #define CONFIG_PCI 620914f483SBecky Bruce #define CONFIG_FSL_ELBC 1 6396b8a054SScott Wood 6489c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 6589c7784eSTimur Tabi 6689c7784eSTimur Tabi /* 6789c7784eSTimur Tabi * On-board devices 684ce1e23bSYork Sun * 694ce1e23bSYork Sun * TSEC1 is VSC switch 704ce1e23bSYork Sun * TSEC2 is SoC TSEC 7189c7784eSTimur Tabi */ 7289c7784eSTimur Tabi #define CONFIG_VSC7385_ENET 734ce1e23bSYork Sun #define CONFIG_TSEC2 7489c7784eSTimur Tabi 756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 765c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 785c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 7996b8a054SScott Wood #else 8096b8a054SScott Wood #error Unknown oscillator frequency. 8196b8a054SScott Wood #endif 8296b8a054SScott Wood 8396b8a054SScott Wood #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 8496b8a054SScott Wood 8596b8a054SScott Wood #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 8696b8a054SScott Wood 876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 8896b8a054SScott Wood 89e4c09508SScott Wood #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 91e4c09508SScott Wood #endif 92e4c09508SScott Wood 936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00001000 946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x07f00000 9596b8a054SScott Wood 9696b8a054SScott Wood /* Early revs of this board will lock up hard when attempting 9796b8a054SScott Wood * to access the PMC registers, unless a JTAG debugger is 9896b8a054SScott Wood * connected, or some resistor modifications are made. 9996b8a054SScott Wood */ 1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 10196b8a054SScott Wood 1026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 1036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 10496b8a054SScott Wood 10596b8a054SScott Wood /* 10689c7784eSTimur Tabi * Device configurations 10789c7784eSTimur Tabi */ 10889c7784eSTimur Tabi 10989c7784eSTimur Tabi /* Vitesse 7385 */ 11089c7784eSTimur Tabi 11189c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 11289c7784eSTimur Tabi 1134ce1e23bSYork Sun #define CONFIG_TSEC1 11489c7784eSTimur Tabi 11589c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 11689c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFE7FE000 11789c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 11889c7784eSTimur Tabi 11989c7784eSTimur Tabi #endif 12089c7784eSTimur Tabi 12189c7784eSTimur Tabi /* 12296b8a054SScott Wood * DDR Setup 12396b8a054SScott Wood */ 1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 12796b8a054SScott Wood 12896b8a054SScott Wood /* 12996b8a054SScott Wood * Manually set up DDR parameters, as this board does not 13096b8a054SScott Wood * seem to have the SPD connected to I2C. 13196b8a054SScott Wood */ 1326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 133*2e651b24SJoe Hershberger #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 1342fef4020SJoe Hershberger | CSCONFIG_ODT_RD_NEVER \ 1352fef4020SJoe Hershberger | CSCONFIG_ODT_WR_ONLY_CURRENT \ 136261c07bcSJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 137261c07bcSJoe Hershberger | CSCONFIG_COL_BIT_10) 138e1d8ed2cSPoonam Aggrwal /* 0x80010102 */ 13996b8a054SScott Wood 1406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_3 0x00000000 1416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 14296b8a054SScott Wood | (0 << TIMING_CFG0_WRT_SHIFT) \ 14396b8a054SScott Wood | (0 << TIMING_CFG0_RRT_SHIFT) \ 14496b8a054SScott Wood | (0 << TIMING_CFG0_WWT_SHIFT) \ 14596b8a054SScott Wood | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 14696b8a054SScott Wood | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 14796b8a054SScott Wood | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 14896b8a054SScott Wood | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 14996b8a054SScott Wood /* 0x00220802 */ 1506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 151e1d8ed2cSPoonam Aggrwal | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 15296b8a054SScott Wood | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 15396b8a054SScott Wood | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 154e1d8ed2cSPoonam Aggrwal | (10 << TIMING_CFG1_REFREC_SHIFT) \ 15596b8a054SScott Wood | (3 << TIMING_CFG1_WRREC_SHIFT) \ 15696b8a054SScott Wood | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 15796b8a054SScott Wood | (2 << TIMING_CFG1_WRTORD_SHIFT)) 158e1d8ed2cSPoonam Aggrwal /* 0x3835a322 */ 1596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 160e1d8ed2cSPoonam Aggrwal | (5 << TIMING_CFG2_CPO_SHIFT) \ 16196b8a054SScott Wood | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 16296b8a054SScott Wood | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 16396b8a054SScott Wood | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 16496b8a054SScott Wood | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 165e1d8ed2cSPoonam Aggrwal | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 166e1d8ed2cSPoonam Aggrwal /* 0x129048c6 */ /* P9-45,may need tuning */ 1676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 168e1d8ed2cSPoonam Aggrwal | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 169e1d8ed2cSPoonam Aggrwal /* 0x05100500 */ 17096b8a054SScott Wood #if defined(CONFIG_DDR_2T_TIMING) 1716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 172bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1732fef4020SJoe Hershberger | SDRAM_CFG_DBW_32 \ 1742fef4020SJoe Hershberger | SDRAM_CFG_2T_EN) 1752fef4020SJoe Hershberger /* 0x43088000 */ 17696b8a054SScott Wood #else 1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 178bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1792fef4020SJoe Hershberger | SDRAM_CFG_DBW_32) 18096b8a054SScott Wood /* 0x43080000 */ 18196b8a054SScott Wood #endif 1826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG2 0x00401000 18396b8a054SScott Wood /* set burst length to 8 for 32-bit data path */ 1846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 185e1d8ed2cSPoonam Aggrwal | (0x0632 << SDRAM_MODE_SD_SHIFT)) 186e1d8ed2cSPoonam Aggrwal /* 0x44480632 */ 1876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x8000C000 18896b8a054SScott Wood 1896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 19096b8a054SScott Wood /*0x02000000*/ 1916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 19296b8a054SScott Wood | DDRCDR_PZ_NOMZ \ 19396b8a054SScott Wood | DDRCDR_NZ_NOMZ \ 19496b8a054SScott Wood | DDRCDR_M_ODR) 19596b8a054SScott Wood 19696b8a054SScott Wood /* 19796b8a054SScott Wood * FLASH on the Local Bus 19896b8a054SScott Wood */ 1996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 20000b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 2016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 2036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 20696b8a054SScott Wood 207261c07bcSJoe Hershberger #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 2087d6a0982SJoe Hershberger | BR_PS_16 /* 16 bit port */ \ 2097d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 210261c07bcSJoe Hershberger | BR_V) /* valid */ 2117d6a0982SJoe Hershberger #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 21296b8a054SScott Wood | OR_GPCM_XACS \ 21396b8a054SScott Wood | OR_GPCM_SCY_9 \ 21496b8a054SScott Wood | OR_GPCM_EHTR \ 21596b8a054SScott Wood | OR_GPCM_EAD) 21696b8a054SScott Wood /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 217261c07bcSJoe Hershberger /* window base at flash base */ 218261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2197d6a0982SJoe Hershberger /* 16 MB window size */ 2207d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 22196b8a054SScott Wood 2226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 2236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 22496b8a054SScott Wood 2256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 22796b8a054SScott Wood 228261c07bcSJoe Hershberger #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 229261c07bcSJoe Hershberger !defined(CONFIG_NAND_SPL) 2306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 23196b8a054SScott Wood #endif 23296b8a054SScott Wood 2336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 234261c07bcSJoe Hershberger #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 235553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 23696b8a054SScott Wood 237261c07bcSJoe Hershberger #define CONFIG_SYS_GBL_DATA_OFFSET \ 238261c07bcSJoe Hershberger (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 24096b8a054SScott Wood 2416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 2424a9932a4SKim Phillips #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 2436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 24496b8a054SScott Wood 24596b8a054SScott Wood /* 24696b8a054SScott Wood * Local Bus LCRR and LBCR regs 24796b8a054SScott Wood */ 248c7190f02SKim Phillips #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 249c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 2506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 25196b8a054SScott Wood | (0xFF << LBCR_BMT_SHIFT) \ 25296b8a054SScott Wood | 0xF) /* 0x0004ff0f */ 25396b8a054SScott Wood 254261c07bcSJoe Hershberger /* LB refresh timer prescal, 266MHz/32 */ 255261c07bcSJoe Hershberger #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 25696b8a054SScott Wood 2577817cb20SMarcel Ziswiler /* drivers/mtd/nand/nand.c */ 258e4c09508SScott Wood #ifdef CONFIG_NAND_SPL 2596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xFFF00000 260e4c09508SScott Wood #else 2616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xE2800000 262e4c09508SScott Wood #endif 263e4c09508SScott Wood 264e8d3ca8bSScott Wood #define CONFIG_MTD_DEVICE 265e8d3ca8bSScott Wood #define CONFIG_MTD_PARTITION 266e8d3ca8bSScott Wood #define CONFIG_CMD_MTDPARTS 267e8d3ca8bSScott Wood #define MTDIDS_DEFAULT "nand0=e2800000.flash" 268e8d3ca8bSScott Wood #define MTDPARTS_DEFAULT \ 269e8d3ca8bSScott Wood "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" 270e8d3ca8bSScott Wood 2716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_NAND_DEVICE 1 27296b8a054SScott Wood #define CONFIG_MTD_NAND_VERIFY_WRITE 273acdab5c3SScott Wood #define CONFIG_CMD_NAND 1 274acdab5c3SScott Wood #define CONFIG_NAND_FSL_ELBC 1 2756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 2767d6a0982SJoe Hershberger #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 27796b8a054SScott Wood 278e4c09508SScott Wood 2796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 2807d6a0982SJoe Hershberger | BR_DECC_CHK_GEN /* Use HW ECC */ \ 281261c07bcSJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 28296b8a054SScott Wood | BR_MS_FCM /* MSEL = FCM */ \ 28396b8a054SScott Wood | BR_V) /* valid */ 2847d6a0982SJoe Hershberger #define CONFIG_SYS_NAND_OR_PRELIM \ 2857d6a0982SJoe Hershberger (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 28696b8a054SScott Wood | OR_FCM_CSCT \ 28796b8a054SScott Wood | OR_FCM_CST \ 28896b8a054SScott Wood | OR_FCM_CHT \ 28996b8a054SScott Wood | OR_FCM_SCY_1 \ 29096b8a054SScott Wood | OR_FCM_TRLX \ 29196b8a054SScott Wood | OR_FCM_EHTR) 29296b8a054SScott Wood /* 0xFFFF8396 */ 293e4c09508SScott Wood 294e4c09508SScott Wood #ifdef CONFIG_NAND_U_BOOT 2956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 2976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 299e4c09508SScott Wood #else 3006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 3016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 3026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 3036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 304e4c09508SScott Wood #endif 305e4c09508SScott Wood 3066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 3077d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 30896b8a054SScott Wood 3096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 3106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 311e4c09508SScott Wood 3127d6a0982SJoe Hershberger /* local bus write LED / read status buffer (BCSR) mapping */ 3137d6a0982SJoe Hershberger #define CONFIG_SYS_BCSR_ADDR 0xFA000000 3147d6a0982SJoe Hershberger #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 3157d6a0982SJoe Hershberger /* map at 0xFA000000 on LCS3 */ 3167d6a0982SJoe Hershberger #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 3177d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 3187d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 3197d6a0982SJoe Hershberger | BR_V) /* valid */ 3207d6a0982SJoe Hershberger /* 0xFA000801 */ 3217d6a0982SJoe Hershberger #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 3227d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 3237d6a0982SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 3247d6a0982SJoe Hershberger | OR_GPCM_XACS \ 3257d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 3267d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 3277d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 3287d6a0982SJoe Hershberger | OR_GPCM_EAD) 3297d6a0982SJoe Hershberger /* 0xFFFF8FF7 */ 3307d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 3317d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 33296b8a054SScott Wood 33389c7784eSTimur Tabi /* Vitesse 7385 */ 33489c7784eSTimur Tabi 33589c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 33689c7784eSTimur Tabi 3377d6a0982SJoe Hershberger /* VSC7385 Base address on LCS2 */ 3387d6a0982SJoe Hershberger #define CONFIG_SYS_VSC7385_BASE 0xF0000000 3397d6a0982SJoe Hershberger #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 3407d6a0982SJoe Hershberger 3417d6a0982SJoe Hershberger #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 3427d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 3437d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 3447d6a0982SJoe Hershberger | BR_V) /* valid */ 3457d6a0982SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 3467d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 3477d6a0982SJoe Hershberger | OR_GPCM_XACS \ 3487d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 3497d6a0982SJoe Hershberger | OR_GPCM_SETA \ 3507d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 3517d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 3527d6a0982SJoe Hershberger | OR_GPCM_EAD) 3537d6a0982SJoe Hershberger /* 0xFFFE09FF */ 3547d6a0982SJoe Hershberger 355261c07bcSJoe Hershberger /* Access window base at VSC7385 base */ 356261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 3577d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 35889c7784eSTimur Tabi 35989c7784eSTimur Tabi #endif 36089c7784eSTimur Tabi 36196b8a054SScott Wood /* pass open firmware flat tree */ 36235cc4e48SKim Phillips #define CONFIG_OF_LIBFDT 1 36396b8a054SScott Wood #define CONFIG_OF_BOARD_SETUP 1 3645b8bc606SKim Phillips #define CONFIG_OF_STDOUT_VIA_ALIAS 1 36596b8a054SScott Wood 36696b8a054SScott Wood /* 36796b8a054SScott Wood * Serial Port 36896b8a054SScott Wood */ 36996b8a054SScott Wood #define CONFIG_CONS_INDEX 1 3706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 37396b8a054SScott Wood 3746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 37596b8a054SScott Wood {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 37696b8a054SScott Wood 3776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 3786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 37996b8a054SScott Wood 38096b8a054SScott Wood /* Use the HUSH parser */ 3816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 3826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 38396b8a054SScott Wood 38496b8a054SScott Wood /* I2C */ 38596b8a054SScott Wood #define CONFIG_HARD_I2C /* I2C with hardware support*/ 38696b8a054SScott Wood #define CONFIG_FSL_I2C 38796b8a054SScott Wood #define CONFIG_I2C_MULTI_BUS 3886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 3896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 3906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ 3916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 3926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 39396b8a054SScott Wood 39496b8a054SScott Wood /* 39596b8a054SScott Wood * General PCI 39696b8a054SScott Wood * Addresses are mapped 1-1. 39796b8a054SScott Wood */ 3986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 4006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 4016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 4026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 4036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 4046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 4056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 4066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 40796b8a054SScott Wood 40896b8a054SScott Wood #define CONFIG_PCI_PNP /* do pci plug-and-play */ 4096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 41096b8a054SScott Wood 41196b8a054SScott Wood /* 41289c7784eSTimur Tabi * TSEC 41396b8a054SScott Wood */ 41496b8a054SScott Wood #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 41596b8a054SScott Wood 41689c7784eSTimur Tabi #define CONFIG_GMII /* MII PHY management */ 41789c7784eSTimur Tabi 41889c7784eSTimur Tabi #ifdef CONFIG_TSEC1 41989c7784eSTimur Tabi #define CONFIG_HAS_ETH0 42089c7784eSTimur Tabi #define CONFIG_TSEC1_NAME "TSEC0" 4216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 42289c7784eSTimur Tabi #define TSEC1_PHY_ADDR 0x1c 42389c7784eSTimur Tabi #define TSEC1_FLAGS TSEC_GIGABIT 42489c7784eSTimur Tabi #define TSEC1_PHYIDX 0 42596b8a054SScott Wood #endif 42696b8a054SScott Wood 42789c7784eSTimur Tabi #ifdef CONFIG_TSEC2 42889c7784eSTimur Tabi #define CONFIG_HAS_ETH1 429255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 4306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 43196b8a054SScott Wood #define TSEC2_PHY_ADDR 4 4323a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 43396b8a054SScott Wood #define TSEC2_PHYIDX 0 43489c7784eSTimur Tabi #endif 43589c7784eSTimur Tabi 43696b8a054SScott Wood 43796b8a054SScott Wood /* Options are: TSEC[0-1] */ 43896b8a054SScott Wood #define CONFIG_ETHPRIME "TSEC1" 43996b8a054SScott Wood 44096b8a054SScott Wood /* 44196b8a054SScott Wood * Configure on-board RTC 44296b8a054SScott Wood */ 44396b8a054SScott Wood #define CONFIG_RTC_DS1337 4446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 44596b8a054SScott Wood 44696b8a054SScott Wood /* 44796b8a054SScott Wood * Environment 44896b8a054SScott Wood */ 449e4c09508SScott Wood #if defined(CONFIG_NAND_U_BOOT) 45051bfee19SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_NAND 1 4510e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET (512 * 1024) 4526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 4530e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 4540e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 4550e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 456261c07bcSJoe Hershberger #define CONFIG_ENV_OFFSET_REDUND \ 457261c07bcSJoe Hershberger (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 4586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif !defined(CONFIG_SYS_RAMBOOT) 4595a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 460261c07bcSJoe Hershberger #define CONFIG_ENV_ADDR \ 461261c07bcSJoe Hershberger (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4620e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 4630e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 46496b8a054SScott Wood 46596b8a054SScott Wood /* Address and size of Redundant Environment Sector */ 46696b8a054SScott Wood #else 46793f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 4686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4690e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 47096b8a054SScott Wood #endif 47196b8a054SScott Wood 47296b8a054SScott Wood #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 4736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 47496b8a054SScott Wood 4758ea5499aSJon Loeliger /* 476079a136cSJon Loeliger * BOOTP options 477079a136cSJon Loeliger */ 478079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 479079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTPATH 480079a136cSJon Loeliger #define CONFIG_BOOTP_GATEWAY 481079a136cSJon Loeliger #define CONFIG_BOOTP_HOSTNAME 482079a136cSJon Loeliger 483079a136cSJon Loeliger 484079a136cSJon Loeliger /* 4858ea5499aSJon Loeliger * Command line configuration. 4868ea5499aSJon Loeliger */ 4878ea5499aSJon Loeliger #include <config_cmd_default.h> 4888ea5499aSJon Loeliger 4898ea5499aSJon Loeliger #define CONFIG_CMD_PING 4908ea5499aSJon Loeliger #define CONFIG_CMD_DHCP 4918ea5499aSJon Loeliger #define CONFIG_CMD_I2C 4928ea5499aSJon Loeliger #define CONFIG_CMD_MII 4938ea5499aSJon Loeliger #define CONFIG_CMD_DATE 4948ea5499aSJon Loeliger #define CONFIG_CMD_PCI 4958ea5499aSJon Loeliger 4966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) 497bdab39d3SMike Frysinger #undef CONFIG_CMD_SAVEENV 4988ea5499aSJon Loeliger #undef CONFIG_CMD_LOADS 4998ea5499aSJon Loeliger #endif 50096b8a054SScott Wood 50196b8a054SScott Wood #define CONFIG_CMDLINE_EDITING 1 502a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 50396b8a054SScott Wood 50496b8a054SScott Wood /* 50596b8a054SScott Wood * Miscellaneous configurable options 50696b8a054SScott Wood */ 5076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 5086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 5096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 5106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 51196b8a054SScott Wood 512261c07bcSJoe Hershberger /* Print Buffer Size */ 513261c07bcSJoe Hershberger #define CONFIG_SYS_PBSIZE \ 514261c07bcSJoe Hershberger (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 5156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 516261c07bcSJoe Hershberger /* Boot Argument Buffer Size */ 517261c07bcSJoe Hershberger #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 5186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 51996b8a054SScott Wood 52096b8a054SScott Wood /* 52196b8a054SScott Wood * For booting Linux, the board info and command line data 5229f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 52396b8a054SScott Wood * the maximum mapped by the Linux kernel during initialization. 52496b8a054SScott Wood */ 525261c07bcSJoe Hershberger /* Initial Memory map for Linux*/ 526261c07bcSJoe Hershberger #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 52796b8a054SScott Wood 5286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 52996b8a054SScott Wood 5306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 53196b8a054SScott Wood 53296b8a054SScott Wood /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 53396b8a054SScott Wood /* 0x62040000 */ 5346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 53596b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 53696b8a054SScott Wood HRCWL_DDRCM |\ 53796b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 53896b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 53996b8a054SScott Wood HRCWL_CSB_TO_CLKIN_2X1 |\ 54096b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 54196b8a054SScott Wood 5426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 543e4c09508SScott Wood 5446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 54596b8a054SScott Wood 54696b8a054SScott Wood /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 54796b8a054SScott Wood /* 0x65040000 */ 5486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 54996b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 55096b8a054SScott Wood HRCWL_DDRCM |\ 55196b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 55296b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 55396b8a054SScott Wood HRCWL_CSB_TO_CLKIN_5X1 |\ 55496b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 55596b8a054SScott Wood 5566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 557e4c09508SScott Wood 55896b8a054SScott Wood #endif 55996b8a054SScott Wood 5606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH_BASE (\ 56196b8a054SScott Wood HRCWH_PCI_HOST |\ 56296b8a054SScott Wood HRCWH_PCI1_ARBITER_ENABLE |\ 56396b8a054SScott Wood HRCWH_CORE_ENABLE |\ 56496b8a054SScott Wood HRCWH_BOOTSEQ_DISABLE |\ 56596b8a054SScott Wood HRCWH_SW_WATCHDOG_DISABLE |\ 56696b8a054SScott Wood HRCWH_TSEC1M_IN_RGMII |\ 56796b8a054SScott Wood HRCWH_TSEC2M_IN_RGMII |\ 568e4c09508SScott Wood HRCWH_BIG_ENDIAN) 569e4c09508SScott Wood 570e4c09508SScott Wood #ifdef CONFIG_NAND_SPL 5716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 572e4c09508SScott Wood HRCWH_FROM_0XFFF00100 |\ 573e4c09508SScott Wood HRCWH_ROM_LOC_NAND_SP_8BIT |\ 574e4c09508SScott Wood HRCWH_RL_EXT_NAND) 575e4c09508SScott Wood #else 5766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 577e4c09508SScott Wood HRCWH_FROM_0X00000100 |\ 578e4c09508SScott Wood HRCWH_ROM_LOC_LOCAL_16BIT |\ 579e4c09508SScott Wood HRCWH_RL_EXT_LEGACY) 580e4c09508SScott Wood #endif 58196b8a054SScott Wood 58296b8a054SScott Wood /* System IO Config */ 5836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 584f986325dSRon Madrid #define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */ 58596b8a054SScott Wood 5866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_INIT 0x000000000 5876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 5881a2e203bSKim Phillips HID0_ENABLE_INSTRUCTION_CACHE | \ 58996b8a054SScott Wood HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 59096b8a054SScott Wood 5916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 59296b8a054SScott Wood 59331d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 59431d82672SBecky Bruce 59596b8a054SScott Wood /* DDR @ 0x00000000 */ 59672cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 597261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 598261c07bcSJoe Hershberger | BATU_BL_256M \ 599261c07bcSJoe Hershberger | BATU_VS \ 600261c07bcSJoe Hershberger | BATU_VP) 60196b8a054SScott Wood 60296b8a054SScott Wood /* PCI @ 0x80000000 */ 60372cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 604261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 605261c07bcSJoe Hershberger | BATU_BL_256M \ 606261c07bcSJoe Hershberger | BATU_VS \ 607261c07bcSJoe Hershberger | BATU_VP) 608261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 60972cd4087SJoe Hershberger | BATL_PP_RW \ 610261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 611261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 612261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 613261c07bcSJoe Hershberger | BATU_BL_256M \ 614261c07bcSJoe Hershberger | BATU_VS \ 615261c07bcSJoe Hershberger | BATU_VP) 61696b8a054SScott Wood 61796b8a054SScott Wood /* PCI2 not supported on 8313 */ 6186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L (0) 6196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U (0) 6206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L (0) 6216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U (0) 62296b8a054SScott Wood 62396b8a054SScott Wood /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 624261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 62572cd4087SJoe Hershberger | BATL_PP_RW \ 626261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 627261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 628261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 629261c07bcSJoe Hershberger | BATU_BL_256M \ 630261c07bcSJoe Hershberger | BATU_VS \ 631261c07bcSJoe Hershberger | BATU_VP) 63296b8a054SScott Wood 63396b8a054SScott Wood /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 63472cd4087SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 6356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 63696b8a054SScott Wood 6376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L (0) 6386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U (0) 63996b8a054SScott Wood 6406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 6416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 6426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 6436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 6446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 6456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 6466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 6476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 6486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 6496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 6506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 6516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 6526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 6536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 6546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 6556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 65696b8a054SScott Wood 65796b8a054SScott Wood /* 65896b8a054SScott Wood * Environment Configuration 65996b8a054SScott Wood */ 66096b8a054SScott Wood #define CONFIG_ENV_OVERWRITE 66196b8a054SScott Wood 662261c07bcSJoe Hershberger #define CONFIG_NETDEV "eth1" 66396b8a054SScott Wood 66496b8a054SScott Wood #define CONFIG_HOSTNAME mpc8313erdb 6658b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfs/root/path" 666b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 667261c07bcSJoe Hershberger /* U-Boot image on TFTP server */ 668261c07bcSJoe Hershberger #define CONFIG_UBOOTPATH "u-boot.bin" 669261c07bcSJoe Hershberger #define CONFIG_FDTFILE "mpc8313erdb.dtb" 67096b8a054SScott Wood 671261c07bcSJoe Hershberger /* default location for tftp and bootm */ 672261c07bcSJoe Hershberger #define CONFIG_LOADADDR 800000 6737fd0bea2SKim Phillips #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 67496b8a054SScott Wood #define CONFIG_BAUDRATE 115200 67596b8a054SScott Wood 67696b8a054SScott Wood #define XMK_STR(x) #x 67796b8a054SScott Wood #define MK_STR(x) XMK_STR(x) 67896b8a054SScott Wood 67996b8a054SScott Wood #define CONFIG_EXTRA_ENV_SETTINGS \ 680261c07bcSJoe Hershberger "netdev=" CONFIG_NETDEV "\0" \ 68196b8a054SScott Wood "ethprime=TSEC1\0" \ 682261c07bcSJoe Hershberger "uboot=" CONFIG_UBOOTPATH "\0" \ 68396b8a054SScott Wood "tftpflash=tftpboot $loadaddr $uboot; " \ 68414d0a02aSWolfgang Denk "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 68514d0a02aSWolfgang Denk "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 68614d0a02aSWolfgang Denk "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\ 68714d0a02aSWolfgang Denk "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 68814d0a02aSWolfgang Denk "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\ 68979f516bcSKim Phillips "fdtaddr=780000\0" \ 690261c07bcSJoe Hershberger "fdtfile=" CONFIG_FDTFILE "\0" \ 69196b8a054SScott Wood "console=ttyS0\0" \ 69296b8a054SScott Wood "setbootargs=setenv bootargs " \ 69396b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 69496b8a054SScott Wood "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 695261c07bcSJoe Hershberger "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 696261c07bcSJoe Hershberger "$netdev:off " \ 69796b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 69896b8a054SScott Wood 69996b8a054SScott Wood #define CONFIG_NFSBOOTCOMMAND \ 70096b8a054SScott Wood "setenv rootdev /dev/nfs;" \ 70196b8a054SScott Wood "run setbootargs;" \ 70296b8a054SScott Wood "run setipargs;" \ 70396b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 70496b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 70596b8a054SScott Wood "bootm $loadaddr - $fdtaddr" 70696b8a054SScott Wood 70796b8a054SScott Wood #define CONFIG_RAMBOOTCOMMAND \ 70896b8a054SScott Wood "setenv rootdev /dev/ram;" \ 70996b8a054SScott Wood "run setbootargs;" \ 71096b8a054SScott Wood "tftp $ramdiskaddr $ramdiskfile;" \ 71196b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 71296b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 71396b8a054SScott Wood "bootm $loadaddr $ramdiskaddr $fdtaddr" 71496b8a054SScott Wood 71596b8a054SScott Wood #undef MK_STR 71696b8a054SScott Wood #undef XMK_STR 71796b8a054SScott Wood 71896b8a054SScott Wood #endif /* __CONFIG_H */ 719