196b8a054SScott Wood /* 2e8d3ca8bSScott Wood * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 396b8a054SScott Wood * 496b8a054SScott Wood * See file CREDITS for list of people who contributed to this 596b8a054SScott Wood * project. 696b8a054SScott Wood * 796b8a054SScott Wood * This program is free software; you can redistribute it and/or 896b8a054SScott Wood * modify it under the terms of the GNU General Public License as 996b8a054SScott Wood * published by the Free Software Foundation; either version 2 of 1096b8a054SScott Wood * the License, or (at your option) any later version. 1196b8a054SScott Wood * 1296b8a054SScott Wood * This program is distributed in the hope that it will be useful, 1396b8a054SScott Wood * but WITHOUT ANY WARRANTY; without even the implied warranty of 1496b8a054SScott Wood * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1596b8a054SScott Wood * GNU General Public License for more details. 1696b8a054SScott Wood * 1796b8a054SScott Wood * You should have received a copy of the GNU General Public License 1896b8a054SScott Wood * along with this program; if not, write to the Free Software 1996b8a054SScott Wood * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 2096b8a054SScott Wood * MA 02111-1307 USA 2196b8a054SScott Wood */ 2296b8a054SScott Wood /* 2396b8a054SScott Wood * mpc8313epb board configuration file 2496b8a054SScott Wood */ 2596b8a054SScott Wood 2696b8a054SScott Wood #ifndef __CONFIG_H 2796b8a054SScott Wood #define __CONFIG_H 2896b8a054SScott Wood 2996b8a054SScott Wood /* 3096b8a054SScott Wood * High Level Configuration Options 3196b8a054SScott Wood */ 3296b8a054SScott Wood #define CONFIG_E300 1 330f898604SPeter Tyser #define CONFIG_MPC83xx 1 342c7920afSPeter Tyser #define CONFIG_MPC831x 1 3596b8a054SScott Wood #define CONFIG_MPC8313 1 3696b8a054SScott Wood #define CONFIG_MPC8313ERDB 1 3796b8a054SScott Wood 38f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 39f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 40f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 41f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 42f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 43f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 44f1c574d4SScott Wood 45f1c574d4SScott Wood #ifdef CONFIG_NAND_U_BOOT 46f1c574d4SScott Wood #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 47f1c574d4SScott Wood #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 48f1c574d4SScott Wood #ifdef CONFIG_NAND_SPL 49f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 50f1c574d4SScott Wood #endif /* CONFIG_NAND_SPL */ 51f1c574d4SScott Wood #endif /* CONFIG_NAND_U_BOOT */ 52f1c574d4SScott Wood 532ae18241SWolfgang Denk #ifndef CONFIG_SYS_TEXT_BASE 542ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFE000000 552ae18241SWolfgang Denk #endif 562ae18241SWolfgang Denk 57f1c574d4SScott Wood #ifndef CONFIG_SYS_MONITOR_BASE 58f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 59f1c574d4SScott Wood #endif 60f1c574d4SScott Wood 6196b8a054SScott Wood #define CONFIG_PCI 620914f483SBecky Bruce #define CONFIG_FSL_ELBC 1 6396b8a054SScott Wood 6489c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 6589c7784eSTimur Tabi 6689c7784eSTimur Tabi /* 6789c7784eSTimur Tabi * On-board devices 684ce1e23bSYork Sun * 694ce1e23bSYork Sun * TSEC1 is VSC switch 704ce1e23bSYork Sun * TSEC2 is SoC TSEC 7189c7784eSTimur Tabi */ 7289c7784eSTimur Tabi #define CONFIG_VSC7385_ENET 734ce1e23bSYork Sun #define CONFIG_TSEC2 7489c7784eSTimur Tabi 756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 765c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 785c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 7996b8a054SScott Wood #else 8096b8a054SScott Wood #error Unknown oscillator frequency. 8196b8a054SScott Wood #endif 8296b8a054SScott Wood 8396b8a054SScott Wood #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 8496b8a054SScott Wood 8596b8a054SScott Wood #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 8696b8a054SScott Wood 876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 8896b8a054SScott Wood 89e4c09508SScott Wood #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 91e4c09508SScott Wood #endif 92e4c09508SScott Wood 936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00001000 946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x07f00000 9596b8a054SScott Wood 9696b8a054SScott Wood /* Early revs of this board will lock up hard when attempting 9796b8a054SScott Wood * to access the PMC registers, unless a JTAG debugger is 9896b8a054SScott Wood * connected, or some resistor modifications are made. 9996b8a054SScott Wood */ 1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 10196b8a054SScott Wood 1026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 1036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 10496b8a054SScott Wood 10596b8a054SScott Wood /* 10689c7784eSTimur Tabi * Device configurations 10789c7784eSTimur Tabi */ 10889c7784eSTimur Tabi 10989c7784eSTimur Tabi /* Vitesse 7385 */ 11089c7784eSTimur Tabi 11189c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 11289c7784eSTimur Tabi 1134ce1e23bSYork Sun #define CONFIG_TSEC1 11489c7784eSTimur Tabi 11589c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 11689c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFE7FE000 11789c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 11889c7784eSTimur Tabi 11989c7784eSTimur Tabi #endif 12089c7784eSTimur Tabi 12189c7784eSTimur Tabi /* 12296b8a054SScott Wood * DDR Setup 12396b8a054SScott Wood */ 1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 12796b8a054SScott Wood 12896b8a054SScott Wood /* 12996b8a054SScott Wood * Manually set up DDR parameters, as this board does not 13096b8a054SScott Wood * seem to have the SPD connected to I2C. 13196b8a054SScott Wood */ 1326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 1336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \ 134e1d8ed2cSPoonam Aggrwal | 0x00010000 /* TODO */ \ 135*261c07bcSJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 136*261c07bcSJoe Hershberger | CSCONFIG_COL_BIT_10) 137e1d8ed2cSPoonam Aggrwal /* 0x80010102 */ 13896b8a054SScott Wood 1396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_3 0x00000000 1406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 14196b8a054SScott Wood | (0 << TIMING_CFG0_WRT_SHIFT) \ 14296b8a054SScott Wood | (0 << TIMING_CFG0_RRT_SHIFT) \ 14396b8a054SScott Wood | (0 << TIMING_CFG0_WWT_SHIFT) \ 14496b8a054SScott Wood | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 14596b8a054SScott Wood | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 14696b8a054SScott Wood | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 14796b8a054SScott Wood | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 14896b8a054SScott Wood /* 0x00220802 */ 1496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 150e1d8ed2cSPoonam Aggrwal | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 15196b8a054SScott Wood | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 15296b8a054SScott Wood | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 153e1d8ed2cSPoonam Aggrwal | (10 << TIMING_CFG1_REFREC_SHIFT) \ 15496b8a054SScott Wood | (3 << TIMING_CFG1_WRREC_SHIFT) \ 15596b8a054SScott Wood | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 15696b8a054SScott Wood | (2 << TIMING_CFG1_WRTORD_SHIFT)) 157e1d8ed2cSPoonam Aggrwal /* 0x3835a322 */ 1586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 159e1d8ed2cSPoonam Aggrwal | (5 << TIMING_CFG2_CPO_SHIFT) \ 16096b8a054SScott Wood | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 16196b8a054SScott Wood | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 16296b8a054SScott Wood | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 16396b8a054SScott Wood | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 164e1d8ed2cSPoonam Aggrwal | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 165e1d8ed2cSPoonam Aggrwal /* 0x129048c6 */ /* P9-45,may need tuning */ 1666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 167e1d8ed2cSPoonam Aggrwal | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 168e1d8ed2cSPoonam Aggrwal /* 0x05100500 */ 16996b8a054SScott Wood #if defined(CONFIG_DDR_2T_TIMING) 1706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 171bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 17296b8a054SScott Wood | SDRAM_CFG_2T_EN \ 17396b8a054SScott Wood | SDRAM_CFG_DBW_32) 17496b8a054SScott Wood #else 1756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 176bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 17796b8a054SScott Wood | SDRAM_CFG_32_BE) 17896b8a054SScott Wood /* 0x43080000 */ 17996b8a054SScott Wood #endif 1806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG2 0x00401000 18196b8a054SScott Wood /* set burst length to 8 for 32-bit data path */ 1826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 183e1d8ed2cSPoonam Aggrwal | (0x0632 << SDRAM_MODE_SD_SHIFT)) 184e1d8ed2cSPoonam Aggrwal /* 0x44480632 */ 1856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x8000C000 18696b8a054SScott Wood 1876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 18896b8a054SScott Wood /*0x02000000*/ 1896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 19096b8a054SScott Wood | DDRCDR_PZ_NOMZ \ 19196b8a054SScott Wood | DDRCDR_NZ_NOMZ \ 19296b8a054SScott Wood | DDRCDR_M_ODR) 19396b8a054SScott Wood 19496b8a054SScott Wood /* 19596b8a054SScott Wood * FLASH on the Local Bus 19696b8a054SScott Wood */ 1976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 19800b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 1996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 2006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 2016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 2036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 20496b8a054SScott Wood 205*261c07bcSJoe Hershberger #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 206*261c07bcSJoe Hershberger | (2 << BR_PS_SHIFT) /* 16 bit port */ \ 207*261c07bcSJoe Hershberger | BR_V) /* valid */ 2086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NOR_OR_PRELIM (0xFF800000 /* 8 MByte */ \ 20996b8a054SScott Wood | OR_GPCM_XACS \ 21096b8a054SScott Wood | OR_GPCM_SCY_9 \ 21196b8a054SScott Wood | OR_GPCM_EHTR \ 21296b8a054SScott Wood | OR_GPCM_EAD) 21396b8a054SScott Wood /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 214*261c07bcSJoe Hershberger /* window base at flash base */ 215*261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ 21796b8a054SScott Wood 2186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 2196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 22096b8a054SScott Wood 2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 22396b8a054SScott Wood 224*261c07bcSJoe Hershberger #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 225*261c07bcSJoe Hershberger !defined(CONFIG_NAND_SPL) 2266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 22796b8a054SScott Wood #endif 22896b8a054SScott Wood 2296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 230*261c07bcSJoe Hershberger #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 231553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 23296b8a054SScott Wood 233*261c07bcSJoe Hershberger #define CONFIG_SYS_GBL_DATA_OFFSET \ 234*261c07bcSJoe Hershberger (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 23696b8a054SScott Wood 2376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 2384a9932a4SKim Phillips #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 2396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 24096b8a054SScott Wood 24196b8a054SScott Wood /* 24296b8a054SScott Wood * Local Bus LCRR and LBCR regs 24396b8a054SScott Wood */ 244c7190f02SKim Phillips #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 245c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 2466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 24796b8a054SScott Wood | (0xFF << LBCR_BMT_SHIFT) \ 24896b8a054SScott Wood | 0xF) /* 0x0004ff0f */ 24996b8a054SScott Wood 250*261c07bcSJoe Hershberger /* LB refresh timer prescal, 266MHz/32 */ 251*261c07bcSJoe Hershberger #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 25296b8a054SScott Wood 2537817cb20SMarcel Ziswiler /* drivers/mtd/nand/nand.c */ 254e4c09508SScott Wood #ifdef CONFIG_NAND_SPL 2556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xFFF00000 256e4c09508SScott Wood #else 2576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xE2800000 258e4c09508SScott Wood #endif 259e4c09508SScott Wood 260e8d3ca8bSScott Wood #define CONFIG_MTD_DEVICE 261e8d3ca8bSScott Wood #define CONFIG_MTD_PARTITION 262e8d3ca8bSScott Wood #define CONFIG_CMD_MTDPARTS 263e8d3ca8bSScott Wood #define MTDIDS_DEFAULT "nand0=e2800000.flash" 264e8d3ca8bSScott Wood #define MTDPARTS_DEFAULT \ 265e8d3ca8bSScott Wood "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" 266e8d3ca8bSScott Wood 2676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_NAND_DEVICE 1 26896b8a054SScott Wood #define CONFIG_MTD_NAND_VERIFY_WRITE 269acdab5c3SScott Wood #define CONFIG_CMD_NAND 1 270acdab5c3SScott Wood #define CONFIG_NAND_FSL_ELBC 1 2716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 27296b8a054SScott Wood 273e4c09508SScott Wood 2746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 27596b8a054SScott Wood | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 276*261c07bcSJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 27796b8a054SScott Wood | BR_MS_FCM /* MSEL = FCM */ \ 27896b8a054SScott Wood | BR_V) /* valid */ 2796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \ 28096b8a054SScott Wood | OR_FCM_CSCT \ 28196b8a054SScott Wood | OR_FCM_CST \ 28296b8a054SScott Wood | OR_FCM_CHT \ 28396b8a054SScott Wood | OR_FCM_SCY_1 \ 28496b8a054SScott Wood | OR_FCM_TRLX \ 28596b8a054SScott Wood | OR_FCM_EHTR) 28696b8a054SScott Wood /* 0xFFFF8396 */ 287e4c09508SScott Wood 288e4c09508SScott Wood #ifdef CONFIG_NAND_U_BOOT 2896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 2916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 293e4c09508SScott Wood #else 2946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 2966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 298e4c09508SScott Wood #endif 299e4c09508SScott Wood 3006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 3016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 30296b8a054SScott Wood 3036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 3046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 305e4c09508SScott Wood 30696b8a054SScott Wood /* local bus read write buffer mapping */ 3076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ 3086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ 3096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xFA000000 3106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 31196b8a054SScott Wood 31289c7784eSTimur Tabi /* Vitesse 7385 */ 31389c7784eSTimur Tabi 3146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_VSC7385_BASE 0xF0000000 31589c7784eSTimur Tabi 31689c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 31789c7784eSTimur Tabi 318*261c07bcSJoe Hershberger /* VSC7385 Base address */ 319*261c07bcSJoe Hershberger #define CONFIG_SYS_BR2_PRELIM 0xf0000801 320*261c07bcSJoe Hershberger /* VSC7385, 128K bytes*/ 321*261c07bcSJoe Hershberger #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff 322*261c07bcSJoe Hershberger /* Access window base at VSC7385 base */ 323*261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 324*261c07bcSJoe Hershberger /* Access window size 128K */ 325*261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 32689c7784eSTimur Tabi 32789c7784eSTimur Tabi #endif 32889c7784eSTimur Tabi 32996b8a054SScott Wood /* pass open firmware flat tree */ 33035cc4e48SKim Phillips #define CONFIG_OF_LIBFDT 1 33196b8a054SScott Wood #define CONFIG_OF_BOARD_SETUP 1 3325b8bc606SKim Phillips #define CONFIG_OF_STDOUT_VIA_ALIAS 1 33396b8a054SScott Wood 33496b8a054SScott Wood /* 33596b8a054SScott Wood * Serial Port 33696b8a054SScott Wood */ 33796b8a054SScott Wood #define CONFIG_CONS_INDEX 1 3386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 34196b8a054SScott Wood 3426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 34396b8a054SScott Wood {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 34496b8a054SScott Wood 3456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 3466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 34796b8a054SScott Wood 34896b8a054SScott Wood /* Use the HUSH parser */ 3496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 3506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 35196b8a054SScott Wood 35296b8a054SScott Wood /* I2C */ 35396b8a054SScott Wood #define CONFIG_HARD_I2C /* I2C with hardware support*/ 35496b8a054SScott Wood #define CONFIG_FSL_I2C 35596b8a054SScott Wood #define CONFIG_I2C_MULTI_BUS 3566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 3576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 3586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ 3596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 3606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 36196b8a054SScott Wood 36296b8a054SScott Wood /* 36396b8a054SScott Wood * General PCI 36496b8a054SScott Wood * Addresses are mapped 1-1. 36596b8a054SScott Wood */ 3666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 3686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 3696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 3706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 3716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 3736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 3746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 37596b8a054SScott Wood 37696b8a054SScott Wood #define CONFIG_PCI_PNP /* do pci plug-and-play */ 3776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 37896b8a054SScott Wood 37996b8a054SScott Wood /* 38089c7784eSTimur Tabi * TSEC 38196b8a054SScott Wood */ 38296b8a054SScott Wood #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 38396b8a054SScott Wood 38489c7784eSTimur Tabi #define CONFIG_GMII /* MII PHY management */ 38589c7784eSTimur Tabi 38689c7784eSTimur Tabi #ifdef CONFIG_TSEC1 38789c7784eSTimur Tabi #define CONFIG_HAS_ETH0 38889c7784eSTimur Tabi #define CONFIG_TSEC1_NAME "TSEC0" 3896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 39089c7784eSTimur Tabi #define TSEC1_PHY_ADDR 0x1c 39189c7784eSTimur Tabi #define TSEC1_FLAGS TSEC_GIGABIT 39289c7784eSTimur Tabi #define TSEC1_PHYIDX 0 39396b8a054SScott Wood #endif 39496b8a054SScott Wood 39589c7784eSTimur Tabi #ifdef CONFIG_TSEC2 39689c7784eSTimur Tabi #define CONFIG_HAS_ETH1 397255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 3986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 39996b8a054SScott Wood #define TSEC2_PHY_ADDR 4 4003a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 40196b8a054SScott Wood #define TSEC2_PHYIDX 0 40289c7784eSTimur Tabi #endif 40389c7784eSTimur Tabi 40496b8a054SScott Wood 40596b8a054SScott Wood /* Options are: TSEC[0-1] */ 40696b8a054SScott Wood #define CONFIG_ETHPRIME "TSEC1" 40796b8a054SScott Wood 40896b8a054SScott Wood /* 40996b8a054SScott Wood * Configure on-board RTC 41096b8a054SScott Wood */ 41196b8a054SScott Wood #define CONFIG_RTC_DS1337 4126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 41396b8a054SScott Wood 41496b8a054SScott Wood /* 41596b8a054SScott Wood * Environment 41696b8a054SScott Wood */ 417e4c09508SScott Wood #if defined(CONFIG_NAND_U_BOOT) 41851bfee19SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_NAND 1 4190e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET (512 * 1024) 4206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 4210e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 4220e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 4230e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 424*261c07bcSJoe Hershberger #define CONFIG_ENV_OFFSET_REDUND \ 425*261c07bcSJoe Hershberger (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 4266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif !defined(CONFIG_SYS_RAMBOOT) 4275a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 428*261c07bcSJoe Hershberger #define CONFIG_ENV_ADDR \ 429*261c07bcSJoe Hershberger (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4300e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 4310e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 43296b8a054SScott Wood 43396b8a054SScott Wood /* Address and size of Redundant Environment Sector */ 43496b8a054SScott Wood #else 43593f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 4366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4370e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 43896b8a054SScott Wood #endif 43996b8a054SScott Wood 44096b8a054SScott Wood #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 4416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 44296b8a054SScott Wood 4438ea5499aSJon Loeliger /* 444079a136cSJon Loeliger * BOOTP options 445079a136cSJon Loeliger */ 446079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 447079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTPATH 448079a136cSJon Loeliger #define CONFIG_BOOTP_GATEWAY 449079a136cSJon Loeliger #define CONFIG_BOOTP_HOSTNAME 450079a136cSJon Loeliger 451079a136cSJon Loeliger 452079a136cSJon Loeliger /* 4538ea5499aSJon Loeliger * Command line configuration. 4548ea5499aSJon Loeliger */ 4558ea5499aSJon Loeliger #include <config_cmd_default.h> 4568ea5499aSJon Loeliger 4578ea5499aSJon Loeliger #define CONFIG_CMD_PING 4588ea5499aSJon Loeliger #define CONFIG_CMD_DHCP 4598ea5499aSJon Loeliger #define CONFIG_CMD_I2C 4608ea5499aSJon Loeliger #define CONFIG_CMD_MII 4618ea5499aSJon Loeliger #define CONFIG_CMD_DATE 4628ea5499aSJon Loeliger #define CONFIG_CMD_PCI 4638ea5499aSJon Loeliger 4646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) 465bdab39d3SMike Frysinger #undef CONFIG_CMD_SAVEENV 4668ea5499aSJon Loeliger #undef CONFIG_CMD_LOADS 4678ea5499aSJon Loeliger #endif 46896b8a054SScott Wood 46996b8a054SScott Wood #define CONFIG_CMDLINE_EDITING 1 470a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 47196b8a054SScott Wood 47296b8a054SScott Wood /* 47396b8a054SScott Wood * Miscellaneous configurable options 47496b8a054SScott Wood */ 4756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 4766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 4776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 4786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 47996b8a054SScott Wood 480*261c07bcSJoe Hershberger /* Print Buffer Size */ 481*261c07bcSJoe Hershberger #define CONFIG_SYS_PBSIZE \ 482*261c07bcSJoe Hershberger (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 4836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 484*261c07bcSJoe Hershberger /* Boot Argument Buffer Size */ 485*261c07bcSJoe Hershberger #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 4866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 48796b8a054SScott Wood 48896b8a054SScott Wood /* 48996b8a054SScott Wood * For booting Linux, the board info and command line data 4909f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 49196b8a054SScott Wood * the maximum mapped by the Linux kernel during initialization. 49296b8a054SScott Wood */ 493*261c07bcSJoe Hershberger /* Initial Memory map for Linux*/ 494*261c07bcSJoe Hershberger #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 49596b8a054SScott Wood 4966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 49796b8a054SScott Wood 4986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 49996b8a054SScott Wood 50096b8a054SScott Wood /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 50196b8a054SScott Wood /* 0x62040000 */ 5026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 50396b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 50496b8a054SScott Wood HRCWL_DDRCM |\ 50596b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 50696b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 50796b8a054SScott Wood HRCWL_CSB_TO_CLKIN_2X1 |\ 50896b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 50996b8a054SScott Wood 5106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 511e4c09508SScott Wood 5126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 51396b8a054SScott Wood 51496b8a054SScott Wood /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 51596b8a054SScott Wood /* 0x65040000 */ 5166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 51796b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 51896b8a054SScott Wood HRCWL_DDRCM |\ 51996b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 52096b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 52196b8a054SScott Wood HRCWL_CSB_TO_CLKIN_5X1 |\ 52296b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 52396b8a054SScott Wood 5246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 525e4c09508SScott Wood 52696b8a054SScott Wood #endif 52796b8a054SScott Wood 5286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH_BASE (\ 52996b8a054SScott Wood HRCWH_PCI_HOST |\ 53096b8a054SScott Wood HRCWH_PCI1_ARBITER_ENABLE |\ 53196b8a054SScott Wood HRCWH_CORE_ENABLE |\ 53296b8a054SScott Wood HRCWH_BOOTSEQ_DISABLE |\ 53396b8a054SScott Wood HRCWH_SW_WATCHDOG_DISABLE |\ 53496b8a054SScott Wood HRCWH_TSEC1M_IN_RGMII |\ 53596b8a054SScott Wood HRCWH_TSEC2M_IN_RGMII |\ 536e4c09508SScott Wood HRCWH_BIG_ENDIAN) 537e4c09508SScott Wood 538e4c09508SScott Wood #ifdef CONFIG_NAND_SPL 5396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 540e4c09508SScott Wood HRCWH_FROM_0XFFF00100 |\ 541e4c09508SScott Wood HRCWH_ROM_LOC_NAND_SP_8BIT |\ 542e4c09508SScott Wood HRCWH_RL_EXT_NAND) 543e4c09508SScott Wood #else 5446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 545e4c09508SScott Wood HRCWH_FROM_0X00000100 |\ 546e4c09508SScott Wood HRCWH_ROM_LOC_LOCAL_16BIT |\ 547e4c09508SScott Wood HRCWH_RL_EXT_LEGACY) 548e4c09508SScott Wood #endif 54996b8a054SScott Wood 55096b8a054SScott Wood /* System IO Config */ 5516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 552f986325dSRon Madrid #define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */ 55396b8a054SScott Wood 5546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_INIT 0x000000000 5556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 5561a2e203bSKim Phillips HID0_ENABLE_INSTRUCTION_CACHE | \ 55796b8a054SScott Wood HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 55896b8a054SScott Wood 5596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 56096b8a054SScott Wood 56131d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 56231d82672SBecky Bruce 56396b8a054SScott Wood /* DDR @ 0x00000000 */ 5646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) 565*261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 566*261c07bcSJoe Hershberger | BATU_BL_256M \ 567*261c07bcSJoe Hershberger | BATU_VS \ 568*261c07bcSJoe Hershberger | BATU_VP) 56996b8a054SScott Wood 57096b8a054SScott Wood /* PCI @ 0x80000000 */ 5716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) 572*261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 573*261c07bcSJoe Hershberger | BATU_BL_256M \ 574*261c07bcSJoe Hershberger | BATU_VS \ 575*261c07bcSJoe Hershberger | BATU_VP) 576*261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 577*261c07bcSJoe Hershberger | BATL_PP_10 \ 578*261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 579*261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 580*261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 581*261c07bcSJoe Hershberger | BATU_BL_256M \ 582*261c07bcSJoe Hershberger | BATU_VS \ 583*261c07bcSJoe Hershberger | BATU_VP) 58496b8a054SScott Wood 58596b8a054SScott Wood /* PCI2 not supported on 8313 */ 5866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L (0) 5876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U (0) 5886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L (0) 5896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U (0) 59096b8a054SScott Wood 59196b8a054SScott Wood /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 592*261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 593*261c07bcSJoe Hershberger | BATL_PP_10 \ 594*261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 595*261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 596*261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 597*261c07bcSJoe Hershberger | BATU_BL_256M \ 598*261c07bcSJoe Hershberger | BATU_VS \ 599*261c07bcSJoe Hershberger | BATU_VP) 60096b8a054SScott Wood 60196b8a054SScott Wood /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 602c1230980SScott Wood #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) 6036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 60496b8a054SScott Wood 6056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L (0) 6066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U (0) 60796b8a054SScott Wood 6086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 6096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 6106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 6116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 6126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 6136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 6146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 6156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 6166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 6176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 6186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 6196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 6206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 6216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 6226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 6236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 62496b8a054SScott Wood 62596b8a054SScott Wood /* 62696b8a054SScott Wood * Environment Configuration 62796b8a054SScott Wood */ 62896b8a054SScott Wood #define CONFIG_ENV_OVERWRITE 62996b8a054SScott Wood 630*261c07bcSJoe Hershberger #define CONFIG_NETDEV "eth1" 63196b8a054SScott Wood 63296b8a054SScott Wood #define CONFIG_HOSTNAME mpc8313erdb 6338b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfs/root/path" 634b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 635*261c07bcSJoe Hershberger /* U-Boot image on TFTP server */ 636*261c07bcSJoe Hershberger #define CONFIG_UBOOTPATH "u-boot.bin" 637*261c07bcSJoe Hershberger #define CONFIG_FDTFILE "mpc8313erdb.dtb" 63896b8a054SScott Wood 639*261c07bcSJoe Hershberger /* default location for tftp and bootm */ 640*261c07bcSJoe Hershberger #define CONFIG_LOADADDR 800000 6417fd0bea2SKim Phillips #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 64296b8a054SScott Wood #define CONFIG_BAUDRATE 115200 64396b8a054SScott Wood 64496b8a054SScott Wood #define XMK_STR(x) #x 64596b8a054SScott Wood #define MK_STR(x) XMK_STR(x) 64696b8a054SScott Wood 64796b8a054SScott Wood #define CONFIG_EXTRA_ENV_SETTINGS \ 648*261c07bcSJoe Hershberger "netdev=" CONFIG_NETDEV "\0" \ 64996b8a054SScott Wood "ethprime=TSEC1\0" \ 650*261c07bcSJoe Hershberger "uboot=" CONFIG_UBOOTPATH "\0" \ 65196b8a054SScott Wood "tftpflash=tftpboot $loadaddr $uboot; " \ 65214d0a02aSWolfgang Denk "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 65314d0a02aSWolfgang Denk "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 65414d0a02aSWolfgang Denk "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\ 65514d0a02aSWolfgang Denk "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\ 65614d0a02aSWolfgang Denk "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\ 65779f516bcSKim Phillips "fdtaddr=780000\0" \ 658*261c07bcSJoe Hershberger "fdtfile=" CONFIG_FDTFILE "\0" \ 65996b8a054SScott Wood "console=ttyS0\0" \ 66096b8a054SScott Wood "setbootargs=setenv bootargs " \ 66196b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 66296b8a054SScott Wood "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 663*261c07bcSJoe Hershberger "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 664*261c07bcSJoe Hershberger "$netdev:off " \ 66596b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 66696b8a054SScott Wood 66796b8a054SScott Wood #define CONFIG_NFSBOOTCOMMAND \ 66896b8a054SScott Wood "setenv rootdev /dev/nfs;" \ 66996b8a054SScott Wood "run setbootargs;" \ 67096b8a054SScott Wood "run setipargs;" \ 67196b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 67296b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 67396b8a054SScott Wood "bootm $loadaddr - $fdtaddr" 67496b8a054SScott Wood 67596b8a054SScott Wood #define CONFIG_RAMBOOTCOMMAND \ 67696b8a054SScott Wood "setenv rootdev /dev/ram;" \ 67796b8a054SScott Wood "run setbootargs;" \ 67896b8a054SScott Wood "tftp $ramdiskaddr $ramdiskfile;" \ 67996b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 68096b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 68196b8a054SScott Wood "bootm $loadaddr $ramdiskaddr $fdtaddr" 68296b8a054SScott Wood 68396b8a054SScott Wood #undef MK_STR 68496b8a054SScott Wood #undef XMK_STR 68596b8a054SScott Wood 68696b8a054SScott Wood #endif /* __CONFIG_H */ 687