196b8a054SScott Wood /* 2e8d3ca8bSScott Wood * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 396b8a054SScott Wood * 496b8a054SScott Wood * See file CREDITS for list of people who contributed to this 596b8a054SScott Wood * project. 696b8a054SScott Wood * 796b8a054SScott Wood * This program is free software; you can redistribute it and/or 896b8a054SScott Wood * modify it under the terms of the GNU General Public License as 996b8a054SScott Wood * published by the Free Software Foundation; either version 2 of 1096b8a054SScott Wood * the License, or (at your option) any later version. 1196b8a054SScott Wood * 1296b8a054SScott Wood * This program is distributed in the hope that it will be useful, 1396b8a054SScott Wood * but WITHOUT ANY WARRANTY; without even the implied warranty of 1496b8a054SScott Wood * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1596b8a054SScott Wood * GNU General Public License for more details. 1696b8a054SScott Wood * 1796b8a054SScott Wood * You should have received a copy of the GNU General Public License 1896b8a054SScott Wood * along with this program; if not, write to the Free Software 1996b8a054SScott Wood * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 2096b8a054SScott Wood * MA 02111-1307 USA 2196b8a054SScott Wood */ 2296b8a054SScott Wood /* 2396b8a054SScott Wood * mpc8313epb board configuration file 2496b8a054SScott Wood */ 2596b8a054SScott Wood 2696b8a054SScott Wood #ifndef __CONFIG_H 2796b8a054SScott Wood #define __CONFIG_H 2896b8a054SScott Wood 2996b8a054SScott Wood /* 3096b8a054SScott Wood * High Level Configuration Options 3196b8a054SScott Wood */ 3296b8a054SScott Wood #define CONFIG_E300 1 330f898604SPeter Tyser #define CONFIG_MPC83xx 1 342c7920afSPeter Tyser #define CONFIG_MPC831x 1 3596b8a054SScott Wood #define CONFIG_MPC8313 1 3696b8a054SScott Wood #define CONFIG_MPC8313ERDB 1 3796b8a054SScott Wood 382ae18241SWolfgang Denk #ifndef CONFIG_SYS_TEXT_BASE 392ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFE000000 402ae18241SWolfgang Denk #endif 412ae18241SWolfgang Denk 4296b8a054SScott Wood #define CONFIG_PCI 430914f483SBecky Bruce #define CONFIG_FSL_ELBC 1 4496b8a054SScott Wood 4589c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 4689c7784eSTimur Tabi 4789c7784eSTimur Tabi /* 4889c7784eSTimur Tabi * On-board devices 494ce1e23bSYork Sun * 504ce1e23bSYork Sun * TSEC1 is VSC switch 514ce1e23bSYork Sun * TSEC2 is SoC TSEC 5289c7784eSTimur Tabi */ 5389c7784eSTimur Tabi #define CONFIG_VSC7385_ENET 544ce1e23bSYork Sun #define CONFIG_TSEC2 5589c7784eSTimur Tabi 566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 575c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 595c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 6096b8a054SScott Wood #else 6196b8a054SScott Wood #error Unknown oscillator frequency. 6296b8a054SScott Wood #endif 6396b8a054SScott Wood 6496b8a054SScott Wood #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 6596b8a054SScott Wood 6696b8a054SScott Wood #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 6796b8a054SScott Wood 686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 6996b8a054SScott Wood 70e4c09508SScott Wood #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 72e4c09508SScott Wood #endif 73e4c09508SScott Wood 746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00001000 756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x07f00000 7696b8a054SScott Wood 7796b8a054SScott Wood /* Early revs of this board will lock up hard when attempting 7896b8a054SScott Wood * to access the PMC registers, unless a JTAG debugger is 7996b8a054SScott Wood * connected, or some resistor modifications are made. 8096b8a054SScott Wood */ 816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 8296b8a054SScott Wood 836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 8596b8a054SScott Wood 8696b8a054SScott Wood /* 8789c7784eSTimur Tabi * Device configurations 8889c7784eSTimur Tabi */ 8989c7784eSTimur Tabi 9089c7784eSTimur Tabi /* Vitesse 7385 */ 9189c7784eSTimur Tabi 9289c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 9389c7784eSTimur Tabi 944ce1e23bSYork Sun #define CONFIG_TSEC1 9589c7784eSTimur Tabi 9689c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 9789c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFE7FE000 9889c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 9989c7784eSTimur Tabi 10089c7784eSTimur Tabi #endif 10189c7784eSTimur Tabi 10289c7784eSTimur Tabi /* 10396b8a054SScott Wood * DDR Setup 10496b8a054SScott Wood */ 1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 10896b8a054SScott Wood 10996b8a054SScott Wood /* 11096b8a054SScott Wood * Manually set up DDR parameters, as this board does not 11196b8a054SScott Wood * seem to have the SPD connected to I2C. 11296b8a054SScott Wood */ 1136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 1146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \ 115e1d8ed2cSPoonam Aggrwal | 0x00010000 /* TODO */ \ 11696b8a054SScott Wood | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) 117e1d8ed2cSPoonam Aggrwal /* 0x80010102 */ 11896b8a054SScott Wood 1196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_3 0x00000000 1206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 12196b8a054SScott Wood | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 12296b8a054SScott Wood | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 12396b8a054SScott Wood | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 12496b8a054SScott Wood | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 12596b8a054SScott Wood | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 12696b8a054SScott Wood | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 12796b8a054SScott Wood | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 12896b8a054SScott Wood /* 0x00220802 */ 1296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ 130e1d8ed2cSPoonam Aggrwal | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 13196b8a054SScott Wood | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ 13296b8a054SScott Wood | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 133e1d8ed2cSPoonam Aggrwal | (10 << TIMING_CFG1_REFREC_SHIFT ) \ 13496b8a054SScott Wood | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ 13596b8a054SScott Wood | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 13696b8a054SScott Wood | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 137e1d8ed2cSPoonam Aggrwal /* 0x3835a322 */ 1386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 139e1d8ed2cSPoonam Aggrwal | ( 5 << TIMING_CFG2_CPO_SHIFT ) \ 14096b8a054SScott Wood | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 14196b8a054SScott Wood | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 14296b8a054SScott Wood | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 14396b8a054SScott Wood | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 144e1d8ed2cSPoonam Aggrwal | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 145e1d8ed2cSPoonam Aggrwal /* 0x129048c6 */ /* P9-45,may need tuning */ 1466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 147e1d8ed2cSPoonam Aggrwal | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 148e1d8ed2cSPoonam Aggrwal /* 0x05100500 */ 14996b8a054SScott Wood #if defined(CONFIG_DDR_2T_TIMING) 1506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ 151bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 15296b8a054SScott Wood | SDRAM_CFG_2T_EN \ 15396b8a054SScott Wood | SDRAM_CFG_DBW_32 ) 15496b8a054SScott Wood #else 1556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ 156bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 15796b8a054SScott Wood | SDRAM_CFG_32_BE ) 15896b8a054SScott Wood /* 0x43080000 */ 15996b8a054SScott Wood #endif 1606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG2 0x00401000 16196b8a054SScott Wood /* set burst length to 8 for 32-bit data path */ 1626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ 163e1d8ed2cSPoonam Aggrwal | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) ) 164e1d8ed2cSPoonam Aggrwal /* 0x44480632 */ 1656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x8000C000 16696b8a054SScott Wood 1676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 16896b8a054SScott Wood /*0x02000000*/ 1696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \ 17096b8a054SScott Wood | DDRCDR_PZ_NOMZ \ 17196b8a054SScott Wood | DDRCDR_NZ_NOMZ \ 17296b8a054SScott Wood | DDRCDR_M_ODR ) 17396b8a054SScott Wood 17496b8a054SScott Wood /* 17596b8a054SScott Wood * FLASH on the Local Bus 17696b8a054SScott Wood */ 1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 17800b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 1796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 1806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 1816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 1826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 1836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 18496b8a054SScott Wood 1856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ 18696b8a054SScott Wood (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 18796b8a054SScott Wood BR_V) /* valid */ 1886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NOR_OR_PRELIM ( 0xFF800000 /* 8 MByte */ \ 18996b8a054SScott Wood | OR_GPCM_XACS \ 19096b8a054SScott Wood | OR_GPCM_SCY_9 \ 19196b8a054SScott Wood | OR_GPCM_EHTR \ 19296b8a054SScott Wood | OR_GPCM_EAD ) 19396b8a054SScott Wood /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 1946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ 1956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ 19696b8a054SScott Wood 1976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 1986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 19996b8a054SScott Wood 2006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 20296b8a054SScott Wood 20314d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 20496b8a054SScott Wood 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_SPL) 2066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 20796b8a054SScott Wood #endif 20896b8a054SScott Wood 2096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 2106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 211553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 21296b8a054SScott Wood 213*25ddd1fbSWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 21596b8a054SScott Wood 2166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 2174a9932a4SKim Phillips #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 2186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 21996b8a054SScott Wood 22096b8a054SScott Wood /* 22196b8a054SScott Wood * Local Bus LCRR and LBCR regs 22296b8a054SScott Wood */ 223c7190f02SKim Phillips #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 224c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 2256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \ 22696b8a054SScott Wood | (0xFF << LBCR_BMT_SHIFT) \ 22796b8a054SScott Wood | 0xF ) /* 0x0004ff0f */ 22896b8a054SScott Wood 2296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ 23096b8a054SScott Wood 2317817cb20SMarcel Ziswiler /* drivers/mtd/nand/nand.c */ 232e4c09508SScott Wood #ifdef CONFIG_NAND_SPL 2336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xFFF00000 234e4c09508SScott Wood #else 2356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xE2800000 236e4c09508SScott Wood #endif 237e4c09508SScott Wood 238e8d3ca8bSScott Wood #define CONFIG_MTD_DEVICE 239e8d3ca8bSScott Wood #define CONFIG_MTD_PARTITION 240e8d3ca8bSScott Wood #define CONFIG_CMD_MTDPARTS 241e8d3ca8bSScott Wood #define MTDIDS_DEFAULT "nand0=e2800000.flash" 242e8d3ca8bSScott Wood #define MTDPARTS_DEFAULT \ 243e8d3ca8bSScott Wood "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" 244e8d3ca8bSScott Wood 2456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_NAND_DEVICE 1 24696b8a054SScott Wood #define CONFIG_MTD_NAND_VERIFY_WRITE 247acdab5c3SScott Wood #define CONFIG_CMD_NAND 1 248acdab5c3SScott Wood #define CONFIG_NAND_FSL_ELBC 1 2496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 25096b8a054SScott Wood 2516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 2526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 2536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 2546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 2556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 2566e1385d5SMingkai Hu #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 257e4c09508SScott Wood 2586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ 25996b8a054SScott Wood | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 26096b8a054SScott Wood | BR_PS_8 /* Port Size = 8 bit */ \ 26196b8a054SScott Wood | BR_MS_FCM /* MSEL = FCM */ \ 26296b8a054SScott Wood | BR_V ) /* valid */ 2636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \ 26496b8a054SScott Wood | OR_FCM_CSCT \ 26596b8a054SScott Wood | OR_FCM_CST \ 26696b8a054SScott Wood | OR_FCM_CHT \ 26796b8a054SScott Wood | OR_FCM_SCY_1 \ 26896b8a054SScott Wood | OR_FCM_TRLX \ 26996b8a054SScott Wood | OR_FCM_EHTR ) 27096b8a054SScott Wood /* 0xFFFF8396 */ 271e4c09508SScott Wood 272e4c09508SScott Wood #ifdef CONFIG_NAND_U_BOOT 2736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 2756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 277e4c09508SScott Wood #else 2786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 2806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 282e4c09508SScott Wood #endif 283e4c09508SScott Wood 2846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 2856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 28696b8a054SScott Wood 2876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 2886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 289e4c09508SScott Wood 29096b8a054SScott Wood /* local bus read write buffer mapping */ 2916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ 2926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ 2936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xFA000000 2946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 29596b8a054SScott Wood 29689c7784eSTimur Tabi /* Vitesse 7385 */ 29789c7784eSTimur Tabi 2986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_VSC7385_BASE 0xF0000000 29989c7784eSTimur Tabi 30089c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 30189c7784eSTimur Tabi 3026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ 3036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ 3046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE/* Access window base at VSC7385 base */ 3056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ 30689c7784eSTimur Tabi 30789c7784eSTimur Tabi #endif 30889c7784eSTimur Tabi 30996b8a054SScott Wood /* pass open firmware flat tree */ 31035cc4e48SKim Phillips #define CONFIG_OF_LIBFDT 1 31196b8a054SScott Wood #define CONFIG_OF_BOARD_SETUP 1 3125b8bc606SKim Phillips #define CONFIG_OF_STDOUT_VIA_ALIAS 1 31396b8a054SScott Wood 31496b8a054SScott Wood /* 31596b8a054SScott Wood * Serial Port 31696b8a054SScott Wood */ 31796b8a054SScott Wood #define CONFIG_CONS_INDEX 1 3186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 32196b8a054SScott Wood 3226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 32396b8a054SScott Wood {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 32496b8a054SScott Wood 3256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 3266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 32796b8a054SScott Wood 32896b8a054SScott Wood /* Use the HUSH parser */ 3296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 3306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 33196b8a054SScott Wood 33296b8a054SScott Wood /* I2C */ 33396b8a054SScott Wood #define CONFIG_HARD_I2C /* I2C with hardware support*/ 33496b8a054SScott Wood #define CONFIG_FSL_I2C 33596b8a054SScott Wood #define CONFIG_I2C_MULTI_BUS 3366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 3376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 3386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 3396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 3406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 34196b8a054SScott Wood 34296b8a054SScott Wood /* 34396b8a054SScott Wood * General PCI 34496b8a054SScott Wood * Addresses are mapped 1-1. 34596b8a054SScott Wood */ 3466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 3486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 3496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 3506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 3516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 3536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 3546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 35596b8a054SScott Wood 35696b8a054SScott Wood #define CONFIG_PCI_PNP /* do pci plug-and-play */ 3576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 35896b8a054SScott Wood 35996b8a054SScott Wood /* 36089c7784eSTimur Tabi * TSEC 36196b8a054SScott Wood */ 36296b8a054SScott Wood #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 36396b8a054SScott Wood 36489c7784eSTimur Tabi #define CONFIG_NET_MULTI 36589c7784eSTimur Tabi #define CONFIG_GMII /* MII PHY management */ 36689c7784eSTimur Tabi 36789c7784eSTimur Tabi #ifdef CONFIG_TSEC1 36889c7784eSTimur Tabi #define CONFIG_HAS_ETH0 36989c7784eSTimur Tabi #define CONFIG_TSEC1_NAME "TSEC0" 3706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 37189c7784eSTimur Tabi #define TSEC1_PHY_ADDR 0x1c 37289c7784eSTimur Tabi #define TSEC1_FLAGS TSEC_GIGABIT 37389c7784eSTimur Tabi #define TSEC1_PHYIDX 0 37496b8a054SScott Wood #endif 37596b8a054SScott Wood 37689c7784eSTimur Tabi #ifdef CONFIG_TSEC2 37789c7784eSTimur Tabi #define CONFIG_HAS_ETH1 378255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 3796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 38096b8a054SScott Wood #define TSEC2_PHY_ADDR 4 3813a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 38296b8a054SScott Wood #define TSEC2_PHYIDX 0 38389c7784eSTimur Tabi #endif 38489c7784eSTimur Tabi 38596b8a054SScott Wood 38696b8a054SScott Wood /* Options are: TSEC[0-1] */ 38796b8a054SScott Wood #define CONFIG_ETHPRIME "TSEC1" 38896b8a054SScott Wood 38996b8a054SScott Wood /* 39096b8a054SScott Wood * Configure on-board RTC 39196b8a054SScott Wood */ 39296b8a054SScott Wood #define CONFIG_RTC_DS1337 3936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 39496b8a054SScott Wood 39596b8a054SScott Wood /* 39696b8a054SScott Wood * Environment 39796b8a054SScott Wood */ 398e4c09508SScott Wood #if defined(CONFIG_NAND_U_BOOT) 39951bfee19SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_NAND 1 4000e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET (512 * 1024) 4016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 4020e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 4030e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 4040e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 4050e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 4066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif !defined(CONFIG_SYS_RAMBOOT) 4075a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 4086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4090e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 4100e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 41196b8a054SScott Wood 41296b8a054SScott Wood /* Address and size of Redundant Environment Sector */ 41396b8a054SScott Wood #else 41493f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 4156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4160e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 41796b8a054SScott Wood #endif 41896b8a054SScott Wood 41996b8a054SScott Wood #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 4206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 42196b8a054SScott Wood 4228ea5499aSJon Loeliger /* 423079a136cSJon Loeliger * BOOTP options 424079a136cSJon Loeliger */ 425079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 426079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTPATH 427079a136cSJon Loeliger #define CONFIG_BOOTP_GATEWAY 428079a136cSJon Loeliger #define CONFIG_BOOTP_HOSTNAME 429079a136cSJon Loeliger 430079a136cSJon Loeliger 431079a136cSJon Loeliger /* 4328ea5499aSJon Loeliger * Command line configuration. 4338ea5499aSJon Loeliger */ 4348ea5499aSJon Loeliger #include <config_cmd_default.h> 4358ea5499aSJon Loeliger 4368ea5499aSJon Loeliger #define CONFIG_CMD_PING 4378ea5499aSJon Loeliger #define CONFIG_CMD_DHCP 4388ea5499aSJon Loeliger #define CONFIG_CMD_I2C 4398ea5499aSJon Loeliger #define CONFIG_CMD_MII 4408ea5499aSJon Loeliger #define CONFIG_CMD_DATE 4418ea5499aSJon Loeliger #define CONFIG_CMD_PCI 4428ea5499aSJon Loeliger 4436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) 444bdab39d3SMike Frysinger #undef CONFIG_CMD_SAVEENV 4458ea5499aSJon Loeliger #undef CONFIG_CMD_LOADS 4468ea5499aSJon Loeliger #endif 44796b8a054SScott Wood 44896b8a054SScott Wood #define CONFIG_CMDLINE_EDITING 1 449a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 45096b8a054SScott Wood 45196b8a054SScott Wood /* 45296b8a054SScott Wood * Miscellaneous configurable options 45396b8a054SScott Wood */ 4546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 4556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 4566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 4576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 45896b8a054SScott Wood 4596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 4606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 4616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 4626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 46396b8a054SScott Wood 46496b8a054SScott Wood /* 46596b8a054SScott Wood * For booting Linux, the board info and command line data 4669f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 46796b8a054SScott Wood * the maximum mapped by the Linux kernel during initialization. 46896b8a054SScott Wood */ 4699f530d59SIra W. Snyder #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 47096b8a054SScott Wood 4716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 47296b8a054SScott Wood 4736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 47496b8a054SScott Wood 47596b8a054SScott Wood /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 47696b8a054SScott Wood /* 0x62040000 */ 4776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 47896b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 47996b8a054SScott Wood HRCWL_DDRCM |\ 48096b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 48196b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 48296b8a054SScott Wood HRCWL_CSB_TO_CLKIN_2X1 |\ 48396b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 48496b8a054SScott Wood 4856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 486e4c09508SScott Wood 4876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 48896b8a054SScott Wood 48996b8a054SScott Wood /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 49096b8a054SScott Wood /* 0x65040000 */ 4916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 49296b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 49396b8a054SScott Wood HRCWL_DDRCM |\ 49496b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 49596b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 49696b8a054SScott Wood HRCWL_CSB_TO_CLKIN_5X1 |\ 49796b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 49896b8a054SScott Wood 4996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 500e4c09508SScott Wood 50196b8a054SScott Wood #endif 50296b8a054SScott Wood 5036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH_BASE (\ 50496b8a054SScott Wood HRCWH_PCI_HOST |\ 50596b8a054SScott Wood HRCWH_PCI1_ARBITER_ENABLE |\ 50696b8a054SScott Wood HRCWH_CORE_ENABLE |\ 50796b8a054SScott Wood HRCWH_BOOTSEQ_DISABLE |\ 50896b8a054SScott Wood HRCWH_SW_WATCHDOG_DISABLE |\ 50996b8a054SScott Wood HRCWH_TSEC1M_IN_RGMII |\ 51096b8a054SScott Wood HRCWH_TSEC2M_IN_RGMII |\ 511e4c09508SScott Wood HRCWH_BIG_ENDIAN) 512e4c09508SScott Wood 513e4c09508SScott Wood #ifdef CONFIG_NAND_SPL 5146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 515e4c09508SScott Wood HRCWH_FROM_0XFFF00100 |\ 516e4c09508SScott Wood HRCWH_ROM_LOC_NAND_SP_8BIT |\ 517e4c09508SScott Wood HRCWH_RL_EXT_NAND) 518e4c09508SScott Wood #else 5196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 520e4c09508SScott Wood HRCWH_FROM_0X00000100 |\ 521e4c09508SScott Wood HRCWH_ROM_LOC_LOCAL_16BIT |\ 522e4c09508SScott Wood HRCWH_RL_EXT_LEGACY) 523e4c09508SScott Wood #endif 52496b8a054SScott Wood 52596b8a054SScott Wood /* System IO Config */ 5266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 527f986325dSRon Madrid #define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */ 52896b8a054SScott Wood 5296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_INIT 0x000000000 5306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 5311a2e203bSKim Phillips HID0_ENABLE_INSTRUCTION_CACHE | \ 53296b8a054SScott Wood HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 53396b8a054SScott Wood 5346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 53596b8a054SScott Wood 53631d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 53731d82672SBecky Bruce 53896b8a054SScott Wood /* DDR @ 0x00000000 */ 5396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) 5406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 54196b8a054SScott Wood 54296b8a054SScott Wood /* PCI @ 0x80000000 */ 5436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) 5446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 5456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 5466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 54796b8a054SScott Wood 54896b8a054SScott Wood /* PCI2 not supported on 8313 */ 5496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L (0) 5506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U (0) 5516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L (0) 5526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U (0) 55396b8a054SScott Wood 55496b8a054SScott Wood /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 5556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 5566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 55796b8a054SScott Wood 55896b8a054SScott Wood /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 559c1230980SScott Wood #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) 5606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 56196b8a054SScott Wood 5626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L (0) 5636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U (0) 56496b8a054SScott Wood 5656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 5666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 5676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 5686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 5696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 5706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 5716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 5726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 5736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 5746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 5756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 5766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 5776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 5786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 5796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 5806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 58196b8a054SScott Wood 58296b8a054SScott Wood /* 58396b8a054SScott Wood * Environment Configuration 58496b8a054SScott Wood */ 58596b8a054SScott Wood #define CONFIG_ENV_OVERWRITE 58696b8a054SScott Wood 58796b8a054SScott Wood #define CONFIG_NETDEV eth1 58896b8a054SScott Wood 58996b8a054SScott Wood #define CONFIG_HOSTNAME mpc8313erdb 59096b8a054SScott Wood #define CONFIG_ROOTPATH /nfs/root/path 59196b8a054SScott Wood #define CONFIG_BOOTFILE uImage 59296b8a054SScott Wood #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 59396b8a054SScott Wood #define CONFIG_FDTFILE mpc8313erdb.dtb 59496b8a054SScott Wood 59579f516bcSKim Phillips #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 5967fd0bea2SKim Phillips #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 59796b8a054SScott Wood #define CONFIG_BAUDRATE 115200 59896b8a054SScott Wood 59996b8a054SScott Wood #define XMK_STR(x) #x 60096b8a054SScott Wood #define MK_STR(x) XMK_STR(x) 60196b8a054SScott Wood 60296b8a054SScott Wood #define CONFIG_EXTRA_ENV_SETTINGS \ 60396b8a054SScott Wood "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 60496b8a054SScott Wood "ethprime=TSEC1\0" \ 60596b8a054SScott Wood "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 60696b8a054SScott Wood "tftpflash=tftpboot $loadaddr $uboot; " \ 60714d0a02aSWolfgang Denk "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 60814d0a02aSWolfgang Denk "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 60914d0a02aSWolfgang Denk "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 61014d0a02aSWolfgang Denk "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 61114d0a02aSWolfgang Denk "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 61279f516bcSKim Phillips "fdtaddr=780000\0" \ 61396b8a054SScott Wood "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 61496b8a054SScott Wood "console=ttyS0\0" \ 61596b8a054SScott Wood "setbootargs=setenv bootargs " \ 61696b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 61796b8a054SScott Wood "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 61896b8a054SScott Wood "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 61996b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 62096b8a054SScott Wood 62196b8a054SScott Wood #define CONFIG_NFSBOOTCOMMAND \ 62296b8a054SScott Wood "setenv rootdev /dev/nfs;" \ 62396b8a054SScott Wood "run setbootargs;" \ 62496b8a054SScott Wood "run setipargs;" \ 62596b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 62696b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 62796b8a054SScott Wood "bootm $loadaddr - $fdtaddr" 62896b8a054SScott Wood 62996b8a054SScott Wood #define CONFIG_RAMBOOTCOMMAND \ 63096b8a054SScott Wood "setenv rootdev /dev/ram;" \ 63196b8a054SScott Wood "run setbootargs;" \ 63296b8a054SScott Wood "tftp $ramdiskaddr $ramdiskfile;" \ 63396b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 63496b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 63596b8a054SScott Wood "bootm $loadaddr $ramdiskaddr $fdtaddr" 63696b8a054SScott Wood 63796b8a054SScott Wood #undef MK_STR 63896b8a054SScott Wood #undef XMK_STR 63996b8a054SScott Wood 64096b8a054SScott Wood #endif /* __CONFIG_H */ 641