196b8a054SScott Wood /* 2e8d3ca8bSScott Wood * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 396b8a054SScott Wood * 4*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 596b8a054SScott Wood */ 696b8a054SScott Wood /* 796b8a054SScott Wood * mpc8313epb board configuration file 896b8a054SScott Wood */ 996b8a054SScott Wood 1096b8a054SScott Wood #ifndef __CONFIG_H 1196b8a054SScott Wood #define __CONFIG_H 1296b8a054SScott Wood 1396b8a054SScott Wood /* 1496b8a054SScott Wood * High Level Configuration Options 1596b8a054SScott Wood */ 1696b8a054SScott Wood #define CONFIG_E300 1 170f898604SPeter Tyser #define CONFIG_MPC83xx 1 182c7920afSPeter Tyser #define CONFIG_MPC831x 1 1996b8a054SScott Wood #define CONFIG_MPC8313 1 2096b8a054SScott Wood #define CONFIG_MPC8313ERDB 1 2196b8a054SScott Wood 2222f4442dSScott Wood #ifdef CONFIG_NAND 2322f4442dSScott Wood #define CONFIG_SPL 2422f4442dSScott Wood #define CONFIG_SPL_INIT_MINIMAL 2522f4442dSScott Wood #define CONFIG_SPL_SERIAL_SUPPORT 2622f4442dSScott Wood #define CONFIG_SPL_NAND_SUPPORT 2722f4442dSScott Wood #define CONFIG_SPL_NAND_MINIMAL 2822f4442dSScott Wood #define CONFIG_SPL_FLUSH_IMAGE 2922f4442dSScott Wood #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 3022f4442dSScott Wood #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 3122f4442dSScott Wood 3222f4442dSScott Wood #ifdef CONFIG_SPL_BUILD 3322f4442dSScott Wood #define CONFIG_NS16550_MIN_FUNCTIONS 3422f4442dSScott Wood #endif 3522f4442dSScott Wood 3622f4442dSScott Wood #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ 3722f4442dSScott Wood #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 3822f4442dSScott Wood #define CONFIG_SPL_MAX_SIZE (4 * 1024) 396113d3f2SBenoît Thébaudeau #define CONFIG_SPL_PAD_TO 0x4000 4022f4442dSScott Wood 41f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 42f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 43f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 44f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 45f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 46f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 47f1c574d4SScott Wood 4822f4442dSScott Wood #ifdef CONFIG_SPL_BUILD 49f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 5022f4442dSScott Wood #endif 5122f4442dSScott Wood 5222f4442dSScott Wood #endif /* CONFIG_NAND */ 53f1c574d4SScott Wood 542ae18241SWolfgang Denk #ifndef CONFIG_SYS_TEXT_BASE 552ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFE000000 562ae18241SWolfgang Denk #endif 572ae18241SWolfgang Denk 58f1c574d4SScott Wood #ifndef CONFIG_SYS_MONITOR_BASE 59f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 60f1c574d4SScott Wood #endif 61f1c574d4SScott Wood 6296b8a054SScott Wood #define CONFIG_PCI 63842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 640914f483SBecky Bruce #define CONFIG_FSL_ELBC 1 6596b8a054SScott Wood 6689c7784eSTimur Tabi #define CONFIG_MISC_INIT_R 6789c7784eSTimur Tabi 6889c7784eSTimur Tabi /* 6989c7784eSTimur Tabi * On-board devices 704ce1e23bSYork Sun * 714ce1e23bSYork Sun * TSEC1 is VSC switch 724ce1e23bSYork Sun * TSEC2 is SoC TSEC 7389c7784eSTimur Tabi */ 7489c7784eSTimur Tabi #define CONFIG_VSC7385_ENET 754ce1e23bSYork Sun #define CONFIG_TSEC2 7689c7784eSTimur Tabi 776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 785c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 805c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 8196b8a054SScott Wood #else 8296b8a054SScott Wood #error Unknown oscillator frequency. 8396b8a054SScott Wood #endif 8496b8a054SScott Wood 8596b8a054SScott Wood #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 8696b8a054SScott Wood 870eaf8f9eSJoe Hershberger #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ 880eaf8f9eSJoe Hershberger #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */ 8996b8a054SScott Wood 906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 9196b8a054SScott Wood 9222f4442dSScott Wood #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) 936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 94e4c09508SScott Wood #endif 95e4c09508SScott Wood 966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00001000 976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x07f00000 9896b8a054SScott Wood 9996b8a054SScott Wood /* Early revs of this board will lock up hard when attempting 10096b8a054SScott Wood * to access the PMC registers, unless a JTAG debugger is 10196b8a054SScott Wood * connected, or some resistor modifications are made. 10296b8a054SScott Wood */ 1036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 10496b8a054SScott Wood 1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 1066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 10796b8a054SScott Wood 10896b8a054SScott Wood /* 10989c7784eSTimur Tabi * Device configurations 11089c7784eSTimur Tabi */ 11189c7784eSTimur Tabi 11289c7784eSTimur Tabi /* Vitesse 7385 */ 11389c7784eSTimur Tabi 11489c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 11589c7784eSTimur Tabi 1164ce1e23bSYork Sun #define CONFIG_TSEC1 11789c7784eSTimur Tabi 11889c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 11989c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFE7FE000 12089c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 12189c7784eSTimur Tabi 12289c7784eSTimur Tabi #endif 12389c7784eSTimur Tabi 12489c7784eSTimur Tabi /* 12596b8a054SScott Wood * DDR Setup 12696b8a054SScott Wood */ 1276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 13096b8a054SScott Wood 13196b8a054SScott Wood /* 13296b8a054SScott Wood * Manually set up DDR parameters, as this board does not 13396b8a054SScott Wood * seem to have the SPD connected to I2C. 13496b8a054SScott Wood */ 1356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 1362e651b24SJoe Hershberger #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 1372fef4020SJoe Hershberger | CSCONFIG_ODT_RD_NEVER \ 1382fef4020SJoe Hershberger | CSCONFIG_ODT_WR_ONLY_CURRENT \ 139261c07bcSJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 140261c07bcSJoe Hershberger | CSCONFIG_COL_BIT_10) 141e1d8ed2cSPoonam Aggrwal /* 0x80010102 */ 14296b8a054SScott Wood 1436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_3 0x00000000 1446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 14596b8a054SScott Wood | (0 << TIMING_CFG0_WRT_SHIFT) \ 14696b8a054SScott Wood | (0 << TIMING_CFG0_RRT_SHIFT) \ 14796b8a054SScott Wood | (0 << TIMING_CFG0_WWT_SHIFT) \ 14896b8a054SScott Wood | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 14996b8a054SScott Wood | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 15096b8a054SScott Wood | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 15196b8a054SScott Wood | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 15296b8a054SScott Wood /* 0x00220802 */ 1536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 154e1d8ed2cSPoonam Aggrwal | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 15596b8a054SScott Wood | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 15696b8a054SScott Wood | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 157e1d8ed2cSPoonam Aggrwal | (10 << TIMING_CFG1_REFREC_SHIFT) \ 15896b8a054SScott Wood | (3 << TIMING_CFG1_WRREC_SHIFT) \ 15996b8a054SScott Wood | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 16096b8a054SScott Wood | (2 << TIMING_CFG1_WRTORD_SHIFT)) 161e1d8ed2cSPoonam Aggrwal /* 0x3835a322 */ 1626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 163e1d8ed2cSPoonam Aggrwal | (5 << TIMING_CFG2_CPO_SHIFT) \ 16496b8a054SScott Wood | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 16596b8a054SScott Wood | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 16696b8a054SScott Wood | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 16796b8a054SScott Wood | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 168e1d8ed2cSPoonam Aggrwal | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 169e1d8ed2cSPoonam Aggrwal /* 0x129048c6 */ /* P9-45,may need tuning */ 1706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 171e1d8ed2cSPoonam Aggrwal | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 172e1d8ed2cSPoonam Aggrwal /* 0x05100500 */ 17396b8a054SScott Wood #if defined(CONFIG_DDR_2T_TIMING) 1746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 175bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1762fef4020SJoe Hershberger | SDRAM_CFG_DBW_32 \ 1772fef4020SJoe Hershberger | SDRAM_CFG_2T_EN) 1782fef4020SJoe Hershberger /* 0x43088000 */ 17996b8a054SScott Wood #else 1806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 181bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1822fef4020SJoe Hershberger | SDRAM_CFG_DBW_32) 18396b8a054SScott Wood /* 0x43080000 */ 18496b8a054SScott Wood #endif 1856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG2 0x00401000 18696b8a054SScott Wood /* set burst length to 8 for 32-bit data path */ 1876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 188e1d8ed2cSPoonam Aggrwal | (0x0632 << SDRAM_MODE_SD_SHIFT)) 189e1d8ed2cSPoonam Aggrwal /* 0x44480632 */ 1906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x8000C000 19196b8a054SScott Wood 1926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 19396b8a054SScott Wood /*0x02000000*/ 1946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 19596b8a054SScott Wood | DDRCDR_PZ_NOMZ \ 19696b8a054SScott Wood | DDRCDR_NZ_NOMZ \ 19796b8a054SScott Wood | DDRCDR_M_ODR) 19896b8a054SScott Wood 19996b8a054SScott Wood /* 20096b8a054SScott Wood * FLASH on the Local Bus 20196b8a054SScott Wood */ 2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 20300b1883aSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 2046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 2066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 2086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 20996b8a054SScott Wood 210261c07bcSJoe Hershberger #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 2117d6a0982SJoe Hershberger | BR_PS_16 /* 16 bit port */ \ 2127d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 213261c07bcSJoe Hershberger | BR_V) /* valid */ 2147d6a0982SJoe Hershberger #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 21596b8a054SScott Wood | OR_GPCM_XACS \ 21696b8a054SScott Wood | OR_GPCM_SCY_9 \ 21796b8a054SScott Wood | OR_GPCM_EHTR \ 21896b8a054SScott Wood | OR_GPCM_EAD) 21996b8a054SScott Wood /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 220261c07bcSJoe Hershberger /* window base at flash base */ 221261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2227d6a0982SJoe Hershberger /* 16 MB window size */ 2237d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 22496b8a054SScott Wood 2256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 2266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 22796b8a054SScott Wood 2286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 23096b8a054SScott Wood 231261c07bcSJoe Hershberger #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 23222f4442dSScott Wood !defined(CONFIG_SPL_BUILD) 2336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 23496b8a054SScott Wood #endif 23596b8a054SScott Wood 2366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 237261c07bcSJoe Hershberger #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 238553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 23996b8a054SScott Wood 240261c07bcSJoe Hershberger #define CONFIG_SYS_GBL_DATA_OFFSET \ 241261c07bcSJoe Hershberger (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 24396b8a054SScott Wood 2446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 2454a9932a4SKim Phillips #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 2466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 24796b8a054SScott Wood 24896b8a054SScott Wood /* 24996b8a054SScott Wood * Local Bus LCRR and LBCR regs 25096b8a054SScott Wood */ 251c7190f02SKim Phillips #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 252c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 2536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 25496b8a054SScott Wood | (0xFF << LBCR_BMT_SHIFT) \ 25596b8a054SScott Wood | 0xF) /* 0x0004ff0f */ 25696b8a054SScott Wood 257261c07bcSJoe Hershberger /* LB refresh timer prescal, 266MHz/32 */ 258261c07bcSJoe Hershberger #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 25996b8a054SScott Wood 2607817cb20SMarcel Ziswiler /* drivers/mtd/nand/nand.c */ 26122f4442dSScott Wood #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) 2626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xFFF00000 263e4c09508SScott Wood #else 2646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xE2800000 265e4c09508SScott Wood #endif 266e4c09508SScott Wood 267e8d3ca8bSScott Wood #define CONFIG_MTD_DEVICE 268e8d3ca8bSScott Wood #define CONFIG_MTD_PARTITION 269e8d3ca8bSScott Wood #define CONFIG_CMD_MTDPARTS 270e8d3ca8bSScott Wood #define MTDIDS_DEFAULT "nand0=e2800000.flash" 271e8d3ca8bSScott Wood #define MTDPARTS_DEFAULT \ 272c947c12eSScott Wood "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" 273e8d3ca8bSScott Wood 2746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_NAND_DEVICE 1 27596b8a054SScott Wood #define CONFIG_MTD_NAND_VERIFY_WRITE 276acdab5c3SScott Wood #define CONFIG_CMD_NAND 1 277acdab5c3SScott Wood #define CONFIG_NAND_FSL_ELBC 1 2786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 2797d6a0982SJoe Hershberger #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 28096b8a054SScott Wood 281e4c09508SScott Wood 2826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 2837d6a0982SJoe Hershberger | BR_DECC_CHK_GEN /* Use HW ECC */ \ 284261c07bcSJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 28596b8a054SScott Wood | BR_MS_FCM /* MSEL = FCM */ \ 28696b8a054SScott Wood | BR_V) /* valid */ 2877d6a0982SJoe Hershberger #define CONFIG_SYS_NAND_OR_PRELIM \ 2887d6a0982SJoe Hershberger (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 28996b8a054SScott Wood | OR_FCM_CSCT \ 29096b8a054SScott Wood | OR_FCM_CST \ 29196b8a054SScott Wood | OR_FCM_CHT \ 29296b8a054SScott Wood | OR_FCM_SCY_1 \ 29396b8a054SScott Wood | OR_FCM_TRLX \ 29496b8a054SScott Wood | OR_FCM_EHTR) 29596b8a054SScott Wood /* 0xFFFF8396 */ 296e4c09508SScott Wood 29722f4442dSScott Wood #ifdef CONFIG_NAND 2986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 3006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 3016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 302e4c09508SScott Wood #else 3036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 3046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 3056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 3066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 307e4c09508SScott Wood #endif 308e4c09508SScott Wood 3096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 3107d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 31196b8a054SScott Wood 3126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 3136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 314e4c09508SScott Wood 3157d6a0982SJoe Hershberger /* local bus write LED / read status buffer (BCSR) mapping */ 3167d6a0982SJoe Hershberger #define CONFIG_SYS_BCSR_ADDR 0xFA000000 3177d6a0982SJoe Hershberger #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 3187d6a0982SJoe Hershberger /* map at 0xFA000000 on LCS3 */ 3197d6a0982SJoe Hershberger #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 3207d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 3217d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 3227d6a0982SJoe Hershberger | BR_V) /* valid */ 3237d6a0982SJoe Hershberger /* 0xFA000801 */ 3247d6a0982SJoe Hershberger #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 3257d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 3267d6a0982SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 3277d6a0982SJoe Hershberger | OR_GPCM_XACS \ 3287d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 3297d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 3307d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 3317d6a0982SJoe Hershberger | OR_GPCM_EAD) 3327d6a0982SJoe Hershberger /* 0xFFFF8FF7 */ 3337d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 3347d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 33596b8a054SScott Wood 33689c7784eSTimur Tabi /* Vitesse 7385 */ 33789c7784eSTimur Tabi 33889c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 33989c7784eSTimur Tabi 3407d6a0982SJoe Hershberger /* VSC7385 Base address on LCS2 */ 3417d6a0982SJoe Hershberger #define CONFIG_SYS_VSC7385_BASE 0xF0000000 3427d6a0982SJoe Hershberger #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 3437d6a0982SJoe Hershberger 3447d6a0982SJoe Hershberger #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 3457d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 3467d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 3477d6a0982SJoe Hershberger | BR_V) /* valid */ 3487d6a0982SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 3497d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 3507d6a0982SJoe Hershberger | OR_GPCM_XACS \ 3517d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 3527d6a0982SJoe Hershberger | OR_GPCM_SETA \ 3537d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 3547d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 3557d6a0982SJoe Hershberger | OR_GPCM_EAD) 3567d6a0982SJoe Hershberger /* 0xFFFE09FF */ 3577d6a0982SJoe Hershberger 358261c07bcSJoe Hershberger /* Access window base at VSC7385 base */ 359261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 3607d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 36189c7784eSTimur Tabi 36289c7784eSTimur Tabi #endif 36389c7784eSTimur Tabi 36496b8a054SScott Wood /* pass open firmware flat tree */ 36535cc4e48SKim Phillips #define CONFIG_OF_LIBFDT 1 36696b8a054SScott Wood #define CONFIG_OF_BOARD_SETUP 1 3675b8bc606SKim Phillips #define CONFIG_OF_STDOUT_VIA_ALIAS 1 36896b8a054SScott Wood 3690eaf8f9eSJoe Hershberger #define CONFIG_MPC83XX_GPIO 1 3700eaf8f9eSJoe Hershberger #define CONFIG_CMD_GPIO 1 3710eaf8f9eSJoe Hershberger 37296b8a054SScott Wood /* 37396b8a054SScott Wood * Serial Port 37496b8a054SScott Wood */ 37596b8a054SScott Wood #define CONFIG_CONS_INDEX 1 3766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 37996b8a054SScott Wood 3806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 38196b8a054SScott Wood {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 38296b8a054SScott Wood 3836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 3846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 38596b8a054SScott Wood 38696b8a054SScott Wood /* Use the HUSH parser */ 3876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 38896b8a054SScott Wood 38996b8a054SScott Wood /* I2C */ 39096b8a054SScott Wood #define CONFIG_HARD_I2C /* I2C with hardware support*/ 39196b8a054SScott Wood #define CONFIG_FSL_I2C 39296b8a054SScott Wood #define CONFIG_I2C_MULTI_BUS 3936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 3946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 3956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ 3966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 3976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 39896b8a054SScott Wood 39996b8a054SScott Wood /* 40096b8a054SScott Wood * General PCI 40196b8a054SScott Wood * Addresses are mapped 1-1. 40296b8a054SScott Wood */ 4036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 4046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 4056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 4066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 4076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 4086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 4096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 4106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 4116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 41296b8a054SScott Wood 41396b8a054SScott Wood #define CONFIG_PCI_PNP /* do pci plug-and-play */ 4146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 41596b8a054SScott Wood 41696b8a054SScott Wood /* 41789c7784eSTimur Tabi * TSEC 41896b8a054SScott Wood */ 41996b8a054SScott Wood #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 42096b8a054SScott Wood 42189c7784eSTimur Tabi #define CONFIG_GMII /* MII PHY management */ 42289c7784eSTimur Tabi 42389c7784eSTimur Tabi #ifdef CONFIG_TSEC1 42489c7784eSTimur Tabi #define CONFIG_HAS_ETH0 42589c7784eSTimur Tabi #define CONFIG_TSEC1_NAME "TSEC0" 4266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 42789c7784eSTimur Tabi #define TSEC1_PHY_ADDR 0x1c 42889c7784eSTimur Tabi #define TSEC1_FLAGS TSEC_GIGABIT 42989c7784eSTimur Tabi #define TSEC1_PHYIDX 0 43096b8a054SScott Wood #endif 43196b8a054SScott Wood 43289c7784eSTimur Tabi #ifdef CONFIG_TSEC2 43389c7784eSTimur Tabi #define CONFIG_HAS_ETH1 434255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 4356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 43696b8a054SScott Wood #define TSEC2_PHY_ADDR 4 4373a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 43896b8a054SScott Wood #define TSEC2_PHYIDX 0 43989c7784eSTimur Tabi #endif 44089c7784eSTimur Tabi 44196b8a054SScott Wood 44296b8a054SScott Wood /* Options are: TSEC[0-1] */ 44396b8a054SScott Wood #define CONFIG_ETHPRIME "TSEC1" 44496b8a054SScott Wood 44596b8a054SScott Wood /* 44696b8a054SScott Wood * Configure on-board RTC 44796b8a054SScott Wood */ 44896b8a054SScott Wood #define CONFIG_RTC_DS1337 4496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 45096b8a054SScott Wood 45196b8a054SScott Wood /* 45296b8a054SScott Wood * Environment 45396b8a054SScott Wood */ 45422f4442dSScott Wood #if defined(CONFIG_NAND) 45551bfee19SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_NAND 1 4560e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET (512 * 1024) 4576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 4580e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 4590e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 4600e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 461261c07bcSJoe Hershberger #define CONFIG_ENV_OFFSET_REDUND \ 462261c07bcSJoe Hershberger (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 4636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif !defined(CONFIG_SYS_RAMBOOT) 4645a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 465261c07bcSJoe Hershberger #define CONFIG_ENV_ADDR \ 466261c07bcSJoe Hershberger (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4670e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 4680e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 46996b8a054SScott Wood 47096b8a054SScott Wood /* Address and size of Redundant Environment Sector */ 47196b8a054SScott Wood #else 47293f6d725SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 4736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4740e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 47596b8a054SScott Wood #endif 47696b8a054SScott Wood 47796b8a054SScott Wood #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 4786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 47996b8a054SScott Wood 4808ea5499aSJon Loeliger /* 481079a136cSJon Loeliger * BOOTP options 482079a136cSJon Loeliger */ 483079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 484079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTPATH 485079a136cSJon Loeliger #define CONFIG_BOOTP_GATEWAY 486079a136cSJon Loeliger #define CONFIG_BOOTP_HOSTNAME 487079a136cSJon Loeliger 488079a136cSJon Loeliger 489079a136cSJon Loeliger /* 4908ea5499aSJon Loeliger * Command line configuration. 4918ea5499aSJon Loeliger */ 4928ea5499aSJon Loeliger #include <config_cmd_default.h> 4938ea5499aSJon Loeliger 4948ea5499aSJon Loeliger #define CONFIG_CMD_PING 4958ea5499aSJon Loeliger #define CONFIG_CMD_DHCP 4968ea5499aSJon Loeliger #define CONFIG_CMD_I2C 4978ea5499aSJon Loeliger #define CONFIG_CMD_MII 4988ea5499aSJon Loeliger #define CONFIG_CMD_DATE 4998ea5499aSJon Loeliger #define CONFIG_CMD_PCI 5008ea5499aSJon Loeliger 50122f4442dSScott Wood #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND) 502bdab39d3SMike Frysinger #undef CONFIG_CMD_SAVEENV 5038ea5499aSJon Loeliger #undef CONFIG_CMD_LOADS 5048ea5499aSJon Loeliger #endif 50596b8a054SScott Wood 50696b8a054SScott Wood #define CONFIG_CMDLINE_EDITING 1 507a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 50896b8a054SScott Wood 50996b8a054SScott Wood /* 51096b8a054SScott Wood * Miscellaneous configurable options 51196b8a054SScott Wood */ 5126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 5136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 5146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 5156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 51696b8a054SScott Wood 517261c07bcSJoe Hershberger /* Print Buffer Size */ 518261c07bcSJoe Hershberger #define CONFIG_SYS_PBSIZE \ 519261c07bcSJoe Hershberger (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 5206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 521261c07bcSJoe Hershberger /* Boot Argument Buffer Size */ 522261c07bcSJoe Hershberger #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 5236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 52496b8a054SScott Wood 52596b8a054SScott Wood /* 52696b8a054SScott Wood * For booting Linux, the board info and command line data 5279f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 52896b8a054SScott Wood * the maximum mapped by the Linux kernel during initialization. 52996b8a054SScott Wood */ 530261c07bcSJoe Hershberger /* Initial Memory map for Linux*/ 531261c07bcSJoe Hershberger #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 53296b8a054SScott Wood 5336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 53496b8a054SScott Wood 5356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 53696b8a054SScott Wood 53796b8a054SScott Wood /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 53896b8a054SScott Wood /* 0x62040000 */ 5396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 54096b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 54196b8a054SScott Wood HRCWL_DDRCM |\ 54296b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 54396b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 54496b8a054SScott Wood HRCWL_CSB_TO_CLKIN_2X1 |\ 54596b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 54696b8a054SScott Wood 5476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 548e4c09508SScott Wood 5496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 55096b8a054SScott Wood 55196b8a054SScott Wood /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 55296b8a054SScott Wood /* 0x65040000 */ 5536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 55496b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 55596b8a054SScott Wood HRCWL_DDRCM |\ 55696b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 55796b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 55896b8a054SScott Wood HRCWL_CSB_TO_CLKIN_5X1 |\ 55996b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 56096b8a054SScott Wood 5616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 562e4c09508SScott Wood 56396b8a054SScott Wood #endif 56496b8a054SScott Wood 5656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH_BASE (\ 56696b8a054SScott Wood HRCWH_PCI_HOST |\ 56796b8a054SScott Wood HRCWH_PCI1_ARBITER_ENABLE |\ 56896b8a054SScott Wood HRCWH_CORE_ENABLE |\ 56996b8a054SScott Wood HRCWH_BOOTSEQ_DISABLE |\ 57096b8a054SScott Wood HRCWH_SW_WATCHDOG_DISABLE |\ 57196b8a054SScott Wood HRCWH_TSEC1M_IN_RGMII |\ 57296b8a054SScott Wood HRCWH_TSEC2M_IN_RGMII |\ 573e4c09508SScott Wood HRCWH_BIG_ENDIAN) 574e4c09508SScott Wood 57522f4442dSScott Wood #ifdef CONFIG_NAND 5766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 577e4c09508SScott Wood HRCWH_FROM_0XFFF00100 |\ 578e4c09508SScott Wood HRCWH_ROM_LOC_NAND_SP_8BIT |\ 579e4c09508SScott Wood HRCWH_RL_EXT_NAND) 580e4c09508SScott Wood #else 5816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 582e4c09508SScott Wood HRCWH_FROM_0X00000100 |\ 583e4c09508SScott Wood HRCWH_ROM_LOC_LOCAL_16BIT |\ 584e4c09508SScott Wood HRCWH_RL_EXT_LEGACY) 585e4c09508SScott Wood #endif 58696b8a054SScott Wood 58796b8a054SScott Wood /* System IO Config */ 5886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 5890eaf8f9eSJoe Hershberger /* Enable Internal USB Phy and GPIO on LCD Connector */ 5900eaf8f9eSJoe Hershberger #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 59196b8a054SScott Wood 5926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_INIT 0x000000000 5936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 5941a2e203bSKim Phillips HID0_ENABLE_INSTRUCTION_CACHE | \ 59596b8a054SScott Wood HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 59696b8a054SScott Wood 5976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 59896b8a054SScott Wood 59931d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 60031d82672SBecky Bruce 60196b8a054SScott Wood /* DDR @ 0x00000000 */ 60272cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 603261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 604261c07bcSJoe Hershberger | BATU_BL_256M \ 605261c07bcSJoe Hershberger | BATU_VS \ 606261c07bcSJoe Hershberger | BATU_VP) 60796b8a054SScott Wood 60896b8a054SScott Wood /* PCI @ 0x80000000 */ 60972cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 610261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 611261c07bcSJoe Hershberger | BATU_BL_256M \ 612261c07bcSJoe Hershberger | BATU_VS \ 613261c07bcSJoe Hershberger | BATU_VP) 614261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 61572cd4087SJoe Hershberger | BATL_PP_RW \ 616261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 617261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 618261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 619261c07bcSJoe Hershberger | BATU_BL_256M \ 620261c07bcSJoe Hershberger | BATU_VS \ 621261c07bcSJoe Hershberger | BATU_VP) 62296b8a054SScott Wood 62396b8a054SScott Wood /* PCI2 not supported on 8313 */ 6246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L (0) 6256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U (0) 6266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L (0) 6276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U (0) 62896b8a054SScott Wood 62996b8a054SScott Wood /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 630261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 63172cd4087SJoe Hershberger | BATL_PP_RW \ 632261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 633261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 634261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 635261c07bcSJoe Hershberger | BATU_BL_256M \ 636261c07bcSJoe Hershberger | BATU_VS \ 637261c07bcSJoe Hershberger | BATU_VP) 63896b8a054SScott Wood 63996b8a054SScott Wood /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 64072cd4087SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 6416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 64296b8a054SScott Wood 6436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L (0) 6446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U (0) 64596b8a054SScott Wood 6466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 6476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 6486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 6496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 6506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 6516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 6526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 6536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 6546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 6556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 6566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 6576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 6586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 6596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 6606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 6616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 66296b8a054SScott Wood 66396b8a054SScott Wood /* 66496b8a054SScott Wood * Environment Configuration 66596b8a054SScott Wood */ 66696b8a054SScott Wood #define CONFIG_ENV_OVERWRITE 66796b8a054SScott Wood 668261c07bcSJoe Hershberger #define CONFIG_NETDEV "eth1" 66996b8a054SScott Wood 67096b8a054SScott Wood #define CONFIG_HOSTNAME mpc8313erdb 6718b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfs/root/path" 672b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 673261c07bcSJoe Hershberger /* U-Boot image on TFTP server */ 674261c07bcSJoe Hershberger #define CONFIG_UBOOTPATH "u-boot.bin" 675261c07bcSJoe Hershberger #define CONFIG_FDTFILE "mpc8313erdb.dtb" 67696b8a054SScott Wood 677261c07bcSJoe Hershberger /* default location for tftp and bootm */ 678261c07bcSJoe Hershberger #define CONFIG_LOADADDR 800000 6797fd0bea2SKim Phillips #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 68096b8a054SScott Wood #define CONFIG_BAUDRATE 115200 68196b8a054SScott Wood 68296b8a054SScott Wood #define CONFIG_EXTRA_ENV_SETTINGS \ 683261c07bcSJoe Hershberger "netdev=" CONFIG_NETDEV "\0" \ 68496b8a054SScott Wood "ethprime=TSEC1\0" \ 685261c07bcSJoe Hershberger "uboot=" CONFIG_UBOOTPATH "\0" \ 68696b8a054SScott Wood "tftpflash=tftpboot $loadaddr $uboot; " \ 6875368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 6885368c55dSMarek Vasut " +$filesize; " \ 6895368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 6905368c55dSMarek Vasut " +$filesize; " \ 6915368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 6925368c55dSMarek Vasut " $filesize; " \ 6935368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 6945368c55dSMarek Vasut " +$filesize; " \ 6955368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 6965368c55dSMarek Vasut " $filesize\0" \ 69779f516bcSKim Phillips "fdtaddr=780000\0" \ 698261c07bcSJoe Hershberger "fdtfile=" CONFIG_FDTFILE "\0" \ 69996b8a054SScott Wood "console=ttyS0\0" \ 70096b8a054SScott Wood "setbootargs=setenv bootargs " \ 70196b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 70296b8a054SScott Wood "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 703261c07bcSJoe Hershberger "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 704261c07bcSJoe Hershberger "$netdev:off " \ 70596b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 70696b8a054SScott Wood 70796b8a054SScott Wood #define CONFIG_NFSBOOTCOMMAND \ 70896b8a054SScott Wood "setenv rootdev /dev/nfs;" \ 70996b8a054SScott Wood "run setbootargs;" \ 71096b8a054SScott Wood "run setipargs;" \ 71196b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 71296b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 71396b8a054SScott Wood "bootm $loadaddr - $fdtaddr" 71496b8a054SScott Wood 71596b8a054SScott Wood #define CONFIG_RAMBOOTCOMMAND \ 71696b8a054SScott Wood "setenv rootdev /dev/ram;" \ 71796b8a054SScott Wood "run setbootargs;" \ 71896b8a054SScott Wood "tftp $ramdiskaddr $ramdiskfile;" \ 71996b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 72096b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 72196b8a054SScott Wood "bootm $loadaddr $ramdiskaddr $fdtaddr" 72296b8a054SScott Wood 72396b8a054SScott Wood #endif /* __CONFIG_H */ 724