196b8a054SScott Wood /* 296b8a054SScott Wood * Copyright (C) Freescale Semiconductor, Inc. 2006. 396b8a054SScott Wood * 496b8a054SScott Wood * See file CREDITS for list of people who contributed to this 596b8a054SScott Wood * project. 696b8a054SScott Wood * 796b8a054SScott Wood * This program is free software; you can redistribute it and/or 896b8a054SScott Wood * modify it under the terms of the GNU General Public License as 996b8a054SScott Wood * published by the Free Software Foundation; either version 2 of 1096b8a054SScott Wood * the License, or (at your option) any later version. 1196b8a054SScott Wood * 1296b8a054SScott Wood * This program is distributed in the hope that it will be useful, 1396b8a054SScott Wood * but WITHOUT ANY WARRANTY; without even the implied warranty of 1496b8a054SScott Wood * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1596b8a054SScott Wood * GNU General Public License for more details. 1696b8a054SScott Wood * 1796b8a054SScott Wood * You should have received a copy of the GNU General Public License 1896b8a054SScott Wood * along with this program; if not, write to the Free Software 1996b8a054SScott Wood * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 2096b8a054SScott Wood * MA 02111-1307 USA 2196b8a054SScott Wood */ 2296b8a054SScott Wood /* 2396b8a054SScott Wood * mpc8313epb board configuration file 2496b8a054SScott Wood */ 2596b8a054SScott Wood 2696b8a054SScott Wood #ifndef __CONFIG_H 2796b8a054SScott Wood #define __CONFIG_H 2896b8a054SScott Wood 2996b8a054SScott Wood /* 3096b8a054SScott Wood * High Level Configuration Options 3196b8a054SScott Wood */ 3296b8a054SScott Wood #define CONFIG_E300 1 3396b8a054SScott Wood #define CONFIG_MPC83XX 1 3496b8a054SScott Wood #define CONFIG_MPC831X 1 3596b8a054SScott Wood #define CONFIG_MPC8313 1 3696b8a054SScott Wood #define CONFIG_MPC8313ERDB 1 3796b8a054SScott Wood 3896b8a054SScott Wood #define CONFIG_PCI 3996b8a054SScott Wood #define CONFIG_83XX_GENERIC_PCI 4096b8a054SScott Wood 4196b8a054SScott Wood #ifdef CFG_66MHZ 425c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 4396b8a054SScott Wood #elif defined(CFG_33MHZ) 445c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 4596b8a054SScott Wood #else 4696b8a054SScott Wood #error Unknown oscillator frequency. 4796b8a054SScott Wood #endif 4896b8a054SScott Wood 4996b8a054SScott Wood #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 5096b8a054SScott Wood 5196b8a054SScott Wood #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 5296b8a054SScott Wood 5396b8a054SScott Wood #define CFG_IMMR 0xE0000000 5496b8a054SScott Wood 5596b8a054SScott Wood #define CFG_MEMTEST_START 0x00001000 5696b8a054SScott Wood #define CFG_MEMTEST_END 0x07f00000 5796b8a054SScott Wood 5896b8a054SScott Wood /* Early revs of this board will lock up hard when attempting 5996b8a054SScott Wood * to access the PMC registers, unless a JTAG debugger is 6096b8a054SScott Wood * connected, or some resistor modifications are made. 6196b8a054SScott Wood */ 6296b8a054SScott Wood #define CFG_8313ERDB_BROKEN_PMC 1 6396b8a054SScott Wood 6496b8a054SScott Wood #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 6596b8a054SScott Wood #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 6696b8a054SScott Wood 6796b8a054SScott Wood /* 6896b8a054SScott Wood * DDR Setup 6996b8a054SScott Wood */ 7096b8a054SScott Wood #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 7196b8a054SScott Wood #define CFG_SDRAM_BASE CFG_DDR_BASE 7296b8a054SScott Wood #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 7396b8a054SScott Wood 7496b8a054SScott Wood /* 7596b8a054SScott Wood * Manually set up DDR parameters, as this board does not 7696b8a054SScott Wood * seem to have the SPD connected to I2C. 7796b8a054SScott Wood */ 7896b8a054SScott Wood #define CFG_DDR_SIZE 128 /* MB */ 7996b8a054SScott Wood #define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP \ 8096b8a054SScott Wood | 0x00040000 /* TODO */ \ 8196b8a054SScott Wood | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) 8296b8a054SScott Wood /* 0x80840102 */ 8396b8a054SScott Wood 8496b8a054SScott Wood #define CFG_DDR_TIMING_3 0x00000000 8596b8a054SScott Wood #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 8696b8a054SScott Wood | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 8796b8a054SScott Wood | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 8896b8a054SScott Wood | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 8996b8a054SScott Wood | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 9096b8a054SScott Wood | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 9196b8a054SScott Wood | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 9296b8a054SScott Wood | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 9396b8a054SScott Wood /* 0x00220802 */ 9496b8a054SScott Wood #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ 9596b8a054SScott Wood | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 9696b8a054SScott Wood | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ 9796b8a054SScott Wood | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 9896b8a054SScott Wood | (13 << TIMING_CFG1_REFREC_SHIFT ) \ 9996b8a054SScott Wood | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ 10096b8a054SScott Wood | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 10196b8a054SScott Wood | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 10296b8a054SScott Wood /* 0x3935d322 */ 10396b8a054SScott Wood #define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 10496b8a054SScott Wood | (31 << TIMING_CFG2_CPO_SHIFT ) \ 10596b8a054SScott Wood | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 10696b8a054SScott Wood | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 10796b8a054SScott Wood | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 10896b8a054SScott Wood | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 10996b8a054SScott Wood | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 11096b8a054SScott Wood /* 0x0f9048ca */ /* P9-45,may need tuning */ 11196b8a054SScott Wood #define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 11296b8a054SScott Wood | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 11396b8a054SScott Wood /* 0x03200064 */ 11496b8a054SScott Wood #if defined(CONFIG_DDR_2T_TIMING) 11596b8a054SScott Wood #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ 11696b8a054SScott Wood | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ 11796b8a054SScott Wood | SDRAM_CFG_2T_EN \ 11896b8a054SScott Wood | SDRAM_CFG_DBW_32 ) 11996b8a054SScott Wood #else 12096b8a054SScott Wood #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ 12196b8a054SScott Wood | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ 12296b8a054SScott Wood | SDRAM_CFG_32_BE ) 12396b8a054SScott Wood /* 0x43080000 */ 12496b8a054SScott Wood #endif 12596b8a054SScott Wood #define CFG_SDRAM_CFG2 0x00401000; 12696b8a054SScott Wood /* set burst length to 8 for 32-bit data path */ 12796b8a054SScott Wood #define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \ 12896b8a054SScott Wood | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) 12996b8a054SScott Wood /* 0x44400232 */ 13096b8a054SScott Wood #define CFG_DDR_MODE_2 0x8000C000; 13196b8a054SScott Wood 13296b8a054SScott Wood #define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 13396b8a054SScott Wood /*0x02000000*/ 13496b8a054SScott Wood #define CFG_DDRCDR_VALUE ( DDRCDR_EN \ 13596b8a054SScott Wood | DDRCDR_PZ_NOMZ \ 13696b8a054SScott Wood | DDRCDR_NZ_NOMZ \ 13796b8a054SScott Wood | DDRCDR_M_ODR ) 13896b8a054SScott Wood 13996b8a054SScott Wood /* 14096b8a054SScott Wood * FLASH on the Local Bus 14196b8a054SScott Wood */ 14296b8a054SScott Wood #define CFG_FLASH_CFI /* use the Common Flash Interface */ 14396b8a054SScott Wood #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 14496b8a054SScott Wood #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ 14596b8a054SScott Wood #define CFG_FLASH_SIZE 8 /* flash size in MB */ 14696b8a054SScott Wood #define CFG_FLASH_EMPTY_INFO /* display empty sectors */ 14796b8a054SScott Wood #define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 14896b8a054SScott Wood 14996b8a054SScott Wood #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ 15096b8a054SScott Wood (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 15196b8a054SScott Wood BR_V) /* valid */ 15296b8a054SScott Wood #define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \ 15396b8a054SScott Wood | OR_GPCM_XACS \ 15496b8a054SScott Wood | OR_GPCM_SCY_9 \ 15596b8a054SScott Wood | OR_GPCM_EHTR \ 15696b8a054SScott Wood | OR_GPCM_EAD ) 15796b8a054SScott Wood /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 15896b8a054SScott Wood #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ 15996b8a054SScott Wood #define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ 16096b8a054SScott Wood 16196b8a054SScott Wood #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 16296b8a054SScott Wood #define CFG_MAX_FLASH_SECT 135 /* sectors per device */ 16396b8a054SScott Wood 16496b8a054SScott Wood #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 16596b8a054SScott Wood #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 16696b8a054SScott Wood 16796b8a054SScott Wood #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 16896b8a054SScott Wood 16996b8a054SScott Wood #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 17096b8a054SScott Wood #define CFG_RAMBOOT 17196b8a054SScott Wood #endif 17296b8a054SScott Wood 17396b8a054SScott Wood #define CFG_INIT_RAM_LOCK 1 17496b8a054SScott Wood #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 17596b8a054SScott Wood #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 17696b8a054SScott Wood 17796b8a054SScott Wood #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 17896b8a054SScott Wood #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 17996b8a054SScott Wood #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 18096b8a054SScott Wood 18196b8a054SScott Wood #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 18296b8a054SScott Wood #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 18396b8a054SScott Wood 18496b8a054SScott Wood /* 18596b8a054SScott Wood * Local Bus LCRR and LBCR regs 18696b8a054SScott Wood */ 18796b8a054SScott Wood #define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */ 18896b8a054SScott Wood #define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ 18996b8a054SScott Wood | (0xFF << LBCR_BMT_SHIFT) \ 19096b8a054SScott Wood | 0xF ) /* 0x0004ff0f */ 19196b8a054SScott Wood 19296b8a054SScott Wood #define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ 19396b8a054SScott Wood 19496b8a054SScott Wood /* drivers/nand/nand.c */ 19596b8a054SScott Wood #define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ 19696b8a054SScott Wood #define CFG_MAX_NAND_DEVICE 1 19796b8a054SScott Wood #define NAND_MAX_CHIPS 1 19896b8a054SScott Wood #define CONFIG_MTD_NAND_VERIFY_WRITE 19996b8a054SScott Wood 20096b8a054SScott Wood #define CFG_BR1_PRELIM ( CFG_NAND_BASE \ 20196b8a054SScott Wood | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 20296b8a054SScott Wood | BR_PS_8 /* Port Size = 8 bit */ \ 20396b8a054SScott Wood | BR_MS_FCM /* MSEL = FCM */ \ 20496b8a054SScott Wood | BR_V ) /* valid */ 20596b8a054SScott Wood #define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ 20696b8a054SScott Wood | OR_FCM_CSCT \ 20796b8a054SScott Wood | OR_FCM_CST \ 20896b8a054SScott Wood | OR_FCM_CHT \ 20996b8a054SScott Wood | OR_FCM_SCY_1 \ 21096b8a054SScott Wood | OR_FCM_TRLX \ 21196b8a054SScott Wood | OR_FCM_EHTR ) 21296b8a054SScott Wood /* 0xFFFF8396 */ 21396b8a054SScott Wood #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE 21496b8a054SScott Wood #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 21596b8a054SScott Wood 21696b8a054SScott Wood #define CFG_VSC7385_BASE 0xF0000000 21796b8a054SScott Wood 21896b8a054SScott Wood #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 21996b8a054SScott Wood #define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ 22096b8a054SScott Wood #define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ 22196b8a054SScott Wood #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */ 22296b8a054SScott Wood #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ 22396b8a054SScott Wood 22496b8a054SScott Wood /* local bus read write buffer mapping */ 22596b8a054SScott Wood #define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ 22696b8a054SScott Wood #define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ 22796b8a054SScott Wood #define CFG_LBLAWBAR3_PRELIM 0xFA000000 22896b8a054SScott Wood #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 22996b8a054SScott Wood 23096b8a054SScott Wood /* pass open firmware flat tree */ 23196b8a054SScott Wood #define CONFIG_OF_FLAT_TREE 1 23296b8a054SScott Wood #define CONFIG_OF_BOARD_SETUP 1 23396b8a054SScott Wood 23496b8a054SScott Wood /* maximum size of the flat tree (8K) */ 23596b8a054SScott Wood #define OF_FLAT_TREE_MAX_SIZE 8192 23696b8a054SScott Wood 23796b8a054SScott Wood #define OF_CPU "PowerPC,8313@0" 23896b8a054SScott Wood #define OF_SOC "soc8313@e0000000" 23996b8a054SScott Wood #define OF_TBCLK (bd->bi_busfreq / 4) 24096b8a054SScott Wood #define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500" 24196b8a054SScott Wood 24296b8a054SScott Wood /* 24396b8a054SScott Wood * Serial Port 24496b8a054SScott Wood */ 24596b8a054SScott Wood #define CONFIG_CONS_INDEX 1 24696b8a054SScott Wood #define CFG_NS16550 24796b8a054SScott Wood #define CFG_NS16550_SERIAL 24896b8a054SScott Wood #define CFG_NS16550_REG_SIZE 1 24996b8a054SScott Wood #define CFG_NS16550_CLK get_bus_freq(0) 25096b8a054SScott Wood 25196b8a054SScott Wood #define CFG_BAUDRATE_TABLE \ 25296b8a054SScott Wood {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 25396b8a054SScott Wood 25496b8a054SScott Wood #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 25596b8a054SScott Wood #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 25696b8a054SScott Wood 25796b8a054SScott Wood /* Use the HUSH parser */ 25896b8a054SScott Wood #define CFG_HUSH_PARSER 25996b8a054SScott Wood #define CFG_PROMPT_HUSH_PS2 "> " 26096b8a054SScott Wood 26196b8a054SScott Wood /* I2C */ 26296b8a054SScott Wood #define CONFIG_HARD_I2C /* I2C with hardware support*/ 26396b8a054SScott Wood #define CONFIG_FSL_I2C 26496b8a054SScott Wood #define CONFIG_I2C_MULTI_BUS 26596b8a054SScott Wood #define CONFIG_I2C_CMD_TREE 26696b8a054SScott Wood #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 26796b8a054SScott Wood #define CFG_I2C_SLAVE 0x7F 268cdd917a4SWolfgang Denk #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 26996b8a054SScott Wood #define CFG_I2C_OFFSET 0x3000 27096b8a054SScott Wood #define CFG_I2C2_OFFSET 0x3100 27196b8a054SScott Wood 27296b8a054SScott Wood /* TSEC */ 27396b8a054SScott Wood #define CFG_TSEC1_OFFSET 0x24000 27496b8a054SScott Wood #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) 27596b8a054SScott Wood #define CFG_TSEC2_OFFSET 0x25000 27696b8a054SScott Wood #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) 27796b8a054SScott Wood #define CONFIG_NET_MULTI 27896b8a054SScott Wood 27996b8a054SScott Wood /* 28096b8a054SScott Wood * General PCI 28196b8a054SScott Wood * Addresses are mapped 1-1. 28296b8a054SScott Wood */ 28396b8a054SScott Wood #define CFG_PCI1_MEM_BASE 0x80000000 28496b8a054SScott Wood #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 28596b8a054SScott Wood #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 28696b8a054SScott Wood #define CFG_PCI1_MMIO_BASE 0x90000000 28796b8a054SScott Wood #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 28896b8a054SScott Wood #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 28996b8a054SScott Wood #define CFG_PCI1_IO_BASE 0x00000000 29096b8a054SScott Wood #define CFG_PCI1_IO_PHYS 0xE2000000 29196b8a054SScott Wood #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 29296b8a054SScott Wood 29396b8a054SScott Wood #define CONFIG_PCI_PNP /* do pci plug-and-play */ 29496b8a054SScott Wood #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 29596b8a054SScott Wood 29696b8a054SScott Wood /* 29796b8a054SScott Wood * TSEC configuration 29896b8a054SScott Wood */ 29996b8a054SScott Wood #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 30096b8a054SScott Wood 30196b8a054SScott Wood #ifndef CONFIG_NET_MULTI 30296b8a054SScott Wood #define CONFIG_NET_MULTI 1 30396b8a054SScott Wood #endif 30496b8a054SScott Wood 30596b8a054SScott Wood #define CONFIG_GMII 1 /* MII PHY management */ 306255a3577SKim Phillips #define CONFIG_TSEC1 1 30796b8a054SScott Wood 308255a3577SKim Phillips #define CONFIG_TSEC1_NAME "TSEC0" 309255a3577SKim Phillips #define CONFIG_TSEC2 1 310255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 31196b8a054SScott Wood #define TSEC1_PHY_ADDR 0x1c 31296b8a054SScott Wood #define TSEC2_PHY_ADDR 4 3133a79013eSAndy Fleming #define TSEC1_FLAGS TSEC_GIGABIT 3143a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 31596b8a054SScott Wood #define TSEC1_PHYIDX 0 31696b8a054SScott Wood #define TSEC2_PHYIDX 0 31796b8a054SScott Wood 31896b8a054SScott Wood /* Options are: TSEC[0-1] */ 31996b8a054SScott Wood #define CONFIG_ETHPRIME "TSEC1" 32096b8a054SScott Wood 32196b8a054SScott Wood /* 32296b8a054SScott Wood * Configure on-board RTC 32396b8a054SScott Wood */ 32496b8a054SScott Wood #define CONFIG_RTC_DS1337 32596b8a054SScott Wood #define CFG_I2C_RTC_ADDR 0x68 32696b8a054SScott Wood 32796b8a054SScott Wood /* 32896b8a054SScott Wood * Environment 32996b8a054SScott Wood */ 33096b8a054SScott Wood #ifndef CFG_RAMBOOT 33196b8a054SScott Wood #define CFG_ENV_IS_IN_FLASH 1 33296b8a054SScott Wood #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) 33396b8a054SScott Wood #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 33496b8a054SScott Wood #define CFG_ENV_SIZE 0x2000 33596b8a054SScott Wood 33696b8a054SScott Wood /* Address and size of Redundant Environment Sector */ 33796b8a054SScott Wood #else 33896b8a054SScott Wood #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 33996b8a054SScott Wood #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 34096b8a054SScott Wood #define CFG_ENV_SIZE 0x2000 34196b8a054SScott Wood #endif 34296b8a054SScott Wood 34396b8a054SScott Wood #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 34496b8a054SScott Wood #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 34596b8a054SScott Wood 3468ea5499aSJon Loeliger /* 347079a136cSJon Loeliger * BOOTP options 348079a136cSJon Loeliger */ 349079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 350079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTPATH 351079a136cSJon Loeliger #define CONFIG_BOOTP_GATEWAY 352079a136cSJon Loeliger #define CONFIG_BOOTP_HOSTNAME 353079a136cSJon Loeliger 354079a136cSJon Loeliger 355079a136cSJon Loeliger /* 3568ea5499aSJon Loeliger * Command line configuration. 3578ea5499aSJon Loeliger */ 3588ea5499aSJon Loeliger #include <config_cmd_default.h> 3598ea5499aSJon Loeliger 3608ea5499aSJon Loeliger #define CONFIG_CMD_PING 3618ea5499aSJon Loeliger #define CONFIG_CMD_DHCP 3628ea5499aSJon Loeliger #define CONFIG_CMD_I2C 3638ea5499aSJon Loeliger #define CONFIG_CMD_MII 3648ea5499aSJon Loeliger #define CONFIG_CMD_DATE 3658ea5499aSJon Loeliger #define CONFIG_CMD_PCI 3668ea5499aSJon Loeliger 3678ea5499aSJon Loeliger #if defined(CFG_RAMBOOT) 3688ea5499aSJon Loeliger #undef CONFIG_CMD_ENV 3698ea5499aSJon Loeliger #undef CONFIG_CMD_LOADS 3708ea5499aSJon Loeliger #endif 37196b8a054SScott Wood 37296b8a054SScott Wood #define CONFIG_CMDLINE_EDITING 1 37396b8a054SScott Wood 37496b8a054SScott Wood 37596b8a054SScott Wood /* 37696b8a054SScott Wood * Miscellaneous configurable options 37796b8a054SScott Wood */ 37896b8a054SScott Wood #define CFG_LONGHELP /* undef to save memory */ 37996b8a054SScott Wood #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 38096b8a054SScott Wood #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 38196b8a054SScott Wood #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 38296b8a054SScott Wood 38396b8a054SScott Wood #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 38496b8a054SScott Wood #define CFG_MAXARGS 16 /* max number of command args */ 38596b8a054SScott Wood #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 38696b8a054SScott Wood #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 38796b8a054SScott Wood 38896b8a054SScott Wood /* 38996b8a054SScott Wood * For booting Linux, the board info and command line data 39096b8a054SScott Wood * have to be in the first 8 MB of memory, since this is 39196b8a054SScott Wood * the maximum mapped by the Linux kernel during initialization. 39296b8a054SScott Wood */ 39396b8a054SScott Wood #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 39496b8a054SScott Wood 39596b8a054SScott Wood /* Cache Configuration */ 39696b8a054SScott Wood #define CFG_DCACHE_SIZE 16384 39796b8a054SScott Wood #define CFG_CACHELINE_SIZE 32 39896b8a054SScott Wood #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 39996b8a054SScott Wood 40096b8a054SScott Wood #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 40196b8a054SScott Wood 40296b8a054SScott Wood #ifdef CFG_66MHZ 40396b8a054SScott Wood 40496b8a054SScott Wood /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 40596b8a054SScott Wood /* 0x62040000 */ 40696b8a054SScott Wood #define CFG_HRCW_LOW (\ 40796b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 40896b8a054SScott Wood HRCWL_DDRCM |\ 40996b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 41096b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 41196b8a054SScott Wood HRCWL_CSB_TO_CLKIN_2X1 |\ 41296b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 41396b8a054SScott Wood 41496b8a054SScott Wood #elif defined(CFG_33MHZ) 41596b8a054SScott Wood 41696b8a054SScott Wood /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 41796b8a054SScott Wood /* 0x65040000 */ 41896b8a054SScott Wood #define CFG_HRCW_LOW (\ 41996b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 42096b8a054SScott Wood HRCWL_DDRCM |\ 42196b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 42296b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 42396b8a054SScott Wood HRCWL_CSB_TO_CLKIN_5X1 |\ 42496b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 42596b8a054SScott Wood 42696b8a054SScott Wood #endif 42796b8a054SScott Wood 42896b8a054SScott Wood /* 0xa0606c00 */ 42996b8a054SScott Wood #define CFG_HRCW_HIGH (\ 43096b8a054SScott Wood HRCWH_PCI_HOST |\ 43196b8a054SScott Wood HRCWH_PCI1_ARBITER_ENABLE |\ 43296b8a054SScott Wood HRCWH_CORE_ENABLE |\ 43396b8a054SScott Wood HRCWH_FROM_0X00000100 |\ 43496b8a054SScott Wood HRCWH_BOOTSEQ_DISABLE |\ 43596b8a054SScott Wood HRCWH_SW_WATCHDOG_DISABLE |\ 43696b8a054SScott Wood HRCWH_ROM_LOC_LOCAL_16BIT |\ 43796b8a054SScott Wood HRCWH_RL_EXT_LEGACY |\ 43896b8a054SScott Wood HRCWH_TSEC1M_IN_RGMII |\ 43996b8a054SScott Wood HRCWH_TSEC2M_IN_RGMII |\ 44096b8a054SScott Wood HRCWH_BIG_ENDIAN |\ 44196b8a054SScott Wood HRCWH_LALE_NORMAL) 44296b8a054SScott Wood 44396b8a054SScott Wood /* System IO Config */ 44496b8a054SScott Wood #define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 44596b8a054SScott Wood #define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ 44696b8a054SScott Wood 44796b8a054SScott Wood #define CFG_HID0_INIT 0x000000000 44896b8a054SScott Wood #define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 44996b8a054SScott Wood HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 45096b8a054SScott Wood 45196b8a054SScott Wood #define CFG_HID2 HID2_HBE 45296b8a054SScott Wood 45396b8a054SScott Wood /* DDR @ 0x00000000 */ 45496b8a054SScott Wood #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) 45596b8a054SScott Wood #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 45696b8a054SScott Wood 45796b8a054SScott Wood /* PCI @ 0x80000000 */ 45896b8a054SScott Wood #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10) 45996b8a054SScott Wood #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 46096b8a054SScott Wood #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 46196b8a054SScott Wood #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 46296b8a054SScott Wood 46396b8a054SScott Wood /* PCI2 not supported on 8313 */ 46496b8a054SScott Wood #define CFG_IBAT3L (0) 46596b8a054SScott Wood #define CFG_IBAT3U (0) 46696b8a054SScott Wood #define CFG_IBAT4L (0) 46796b8a054SScott Wood #define CFG_IBAT4U (0) 46896b8a054SScott Wood 46996b8a054SScott Wood /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 47096b8a054SScott Wood #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 47196b8a054SScott Wood #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 47296b8a054SScott Wood 47396b8a054SScott Wood /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 47496b8a054SScott Wood #define CFG_IBAT6L (0xF0000000 | BATL_PP_10) 47596b8a054SScott Wood #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 47696b8a054SScott Wood 47796b8a054SScott Wood #define CFG_IBAT7L (0) 47896b8a054SScott Wood #define CFG_IBAT7U (0) 47996b8a054SScott Wood 48096b8a054SScott Wood #define CFG_DBAT0L CFG_IBAT0L 48196b8a054SScott Wood #define CFG_DBAT0U CFG_IBAT0U 48296b8a054SScott Wood #define CFG_DBAT1L CFG_IBAT1L 48396b8a054SScott Wood #define CFG_DBAT1U CFG_IBAT1U 48496b8a054SScott Wood #define CFG_DBAT2L CFG_IBAT2L 48596b8a054SScott Wood #define CFG_DBAT2U CFG_IBAT2U 48696b8a054SScott Wood #define CFG_DBAT3L CFG_IBAT3L 48796b8a054SScott Wood #define CFG_DBAT3U CFG_IBAT3U 48896b8a054SScott Wood #define CFG_DBAT4L CFG_IBAT4L 48996b8a054SScott Wood #define CFG_DBAT4U CFG_IBAT4U 49096b8a054SScott Wood #define CFG_DBAT5L CFG_IBAT5L 49196b8a054SScott Wood #define CFG_DBAT5U CFG_IBAT5U 49296b8a054SScott Wood #define CFG_DBAT6L CFG_IBAT6L 49396b8a054SScott Wood #define CFG_DBAT6U CFG_IBAT6U 49496b8a054SScott Wood #define CFG_DBAT7L CFG_IBAT7L 49596b8a054SScott Wood #define CFG_DBAT7U CFG_IBAT7U 49696b8a054SScott Wood 49796b8a054SScott Wood /* 49896b8a054SScott Wood * Internal Definitions 49996b8a054SScott Wood * 50096b8a054SScott Wood * Boot Flags 50196b8a054SScott Wood */ 50296b8a054SScott Wood #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 50396b8a054SScott Wood #define BOOTFLAG_WARM 0x02 /* Software reboot */ 50496b8a054SScott Wood 50596b8a054SScott Wood /* 50696b8a054SScott Wood * Environment Configuration 50796b8a054SScott Wood */ 50896b8a054SScott Wood #define CONFIG_ENV_OVERWRITE 50996b8a054SScott Wood 51096b8a054SScott Wood #define CONFIG_ETHADDR 00:E0:0C:00:95:01 51196b8a054SScott Wood #define CONFIG_HAS_ETH1 512*10327dc5SAndy Fleming #define CONFIG_HAS_ETH0 51396b8a054SScott Wood #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 51496b8a054SScott Wood 51596b8a054SScott Wood #define CONFIG_IPADDR 10.0.0.2 51696b8a054SScott Wood #define CONFIG_SERVERIP 10.0.0.1 51796b8a054SScott Wood #define CONFIG_GATEWAYIP 10.0.0.1 51896b8a054SScott Wood #define CONFIG_NETMASK 255.0.0.0 51996b8a054SScott Wood #define CONFIG_NETDEV eth1 52096b8a054SScott Wood 52196b8a054SScott Wood #define CONFIG_HOSTNAME mpc8313erdb 52296b8a054SScott Wood #define CONFIG_ROOTPATH /nfs/root/path 52396b8a054SScott Wood #define CONFIG_BOOTFILE uImage 52496b8a054SScott Wood #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 52596b8a054SScott Wood #define CONFIG_FDTFILE mpc8313erdb.dtb 52696b8a054SScott Wood 52796b8a054SScott Wood #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 52896b8a054SScott Wood #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 52996b8a054SScott Wood #define CONFIG_BAUDRATE 115200 53096b8a054SScott Wood 53196b8a054SScott Wood #define XMK_STR(x) #x 53296b8a054SScott Wood #define MK_STR(x) XMK_STR(x) 53396b8a054SScott Wood 53496b8a054SScott Wood #define CONFIG_EXTRA_ENV_SETTINGS \ 53596b8a054SScott Wood "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 53696b8a054SScott Wood "ethprime=TSEC1\0" \ 53796b8a054SScott Wood "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 53896b8a054SScott Wood "tftpflash=tftpboot $loadaddr $uboot; " \ 53996b8a054SScott Wood "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 54096b8a054SScott Wood "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 54196b8a054SScott Wood "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 54296b8a054SScott Wood "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 54396b8a054SScott Wood "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 54496b8a054SScott Wood "fdtaddr=400000\0" \ 54596b8a054SScott Wood "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 54696b8a054SScott Wood "console=ttyS0\0" \ 54796b8a054SScott Wood "setbootargs=setenv bootargs " \ 54896b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 54996b8a054SScott Wood "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 55096b8a054SScott Wood "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 55196b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 55296b8a054SScott Wood 55396b8a054SScott Wood #define CONFIG_NFSBOOTCOMMAND \ 55496b8a054SScott Wood "setenv rootdev /dev/nfs;" \ 55596b8a054SScott Wood "run setbootargs;" \ 55696b8a054SScott Wood "run setipargs;" \ 55796b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 55896b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 55996b8a054SScott Wood "bootm $loadaddr - $fdtaddr" 56096b8a054SScott Wood 56196b8a054SScott Wood #define CONFIG_RAMBOOTCOMMAND \ 56296b8a054SScott Wood "setenv rootdev /dev/ram;" \ 56396b8a054SScott Wood "run setbootargs;" \ 56496b8a054SScott Wood "tftp $ramdiskaddr $ramdiskfile;" \ 56596b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 56696b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 56796b8a054SScott Wood "bootm $loadaddr $ramdiskaddr $fdtaddr" 56896b8a054SScott Wood 56996b8a054SScott Wood #undef MK_STR 57096b8a054SScott Wood #undef XMK_STR 57196b8a054SScott Wood 57296b8a054SScott Wood #endif /* __CONFIG_H */ 573