1 /* 2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC830x 1 /* MPC830x family */ 17 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 18 #define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ 19 20 #define CONFIG_SYS_TEXT_BASE 0xFE000000 21 22 #define CONFIG_MISC_INIT_R 23 24 #ifdef CONFIG_MMC 25 #define CONFIG_FSL_ESDHC 26 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 27 #define CONFIG_SYS_FSL_ESDHC_USE_PIO 28 #endif 29 30 /* 31 * On-board devices 32 * 33 * TSEC1 is SoC TSEC 34 * TSEC2 is VSC switch 35 */ 36 #define CONFIG_TSEC1 37 #define CONFIG_VSC7385_ENET 38 39 /* 40 * System Clock Setup 41 */ 42 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 43 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 44 45 /* 46 * Hardware Reset Configuration Word 47 * if CLKIN is 66.66MHz, then 48 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 49 * We choose the A type silicon as default, so the core is 400Mhz. 50 */ 51 #define CONFIG_SYS_HRCW_LOW (\ 52 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 53 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 54 HRCWL_SVCOD_DIV_2 |\ 55 HRCWL_CSB_TO_CLKIN_4X1 |\ 56 HRCWL_CORE_TO_CSB_3X1) 57 /* 58 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 59 * in 8308's HRCWH according to the manual, but original Freescale's 60 * code has them and I've expirienced some problems using the board 61 * with BDI3000 attached when I've tried to set these bits to zero 62 * (UART doesn't work after the 'reset run' command). 63 */ 64 #define CONFIG_SYS_HRCW_HIGH (\ 65 HRCWH_PCI_HOST |\ 66 HRCWH_PCI1_ARBITER_ENABLE |\ 67 HRCWH_CORE_ENABLE |\ 68 HRCWH_FROM_0X00000100 |\ 69 HRCWH_BOOTSEQ_DISABLE |\ 70 HRCWH_SW_WATCHDOG_DISABLE |\ 71 HRCWH_ROM_LOC_LOCAL_16BIT |\ 72 HRCWH_RL_EXT_LEGACY |\ 73 HRCWH_TSEC1M_IN_RGMII |\ 74 HRCWH_TSEC2M_IN_RGMII |\ 75 HRCWH_BIG_ENDIAN) 76 77 /* 78 * System IO Config 79 */ 80 #define CONFIG_SYS_SICRH (\ 81 SICRH_ESDHC_A_SD |\ 82 SICRH_ESDHC_B_SD |\ 83 SICRH_ESDHC_C_SD |\ 84 SICRH_GPIO_A_TSEC2 |\ 85 SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ 86 SICRH_IEEE1588_A_GPIO |\ 87 SICRH_USB |\ 88 SICRH_GTM_GPIO |\ 89 SICRH_IEEE1588_B_GPIO |\ 90 SICRH_ETSEC2_CRS |\ 91 SICRH_GPIOSEL_1 |\ 92 SICRH_TMROBI_V3P3 |\ 93 SICRH_TSOBI1_V2P5 |\ 94 SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ 95 #define CONFIG_SYS_SICRL (\ 96 SICRL_SPI_PF0 |\ 97 SICRL_UART_PF0 |\ 98 SICRL_IRQ_PF0 |\ 99 SICRL_I2C2_PF0 |\ 100 SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ 101 102 /* 103 * IMMR new address 104 */ 105 #define CONFIG_SYS_IMMR 0xE0000000 106 107 /* 108 * SERDES 109 */ 110 #define CONFIG_FSL_SERDES 111 #define CONFIG_FSL_SERDES1 0xe3000 112 113 /* 114 * Arbiter Setup 115 */ 116 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 117 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 118 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 119 120 /* 121 * DDR Setup 122 */ 123 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 124 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 125 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 126 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 127 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 128 | DDRCDR_PZ_LOZ \ 129 | DDRCDR_NZ_LOZ \ 130 | DDRCDR_ODT \ 131 | DDRCDR_Q_DRN) 132 /* 0x7b880001 */ 133 /* 134 * Manually set up DDR parameters 135 * consist of two chips HY5PS12621BFP-C4 from HYNIX 136 */ 137 138 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 139 140 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 141 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 142 | CSCONFIG_ODT_RD_NEVER \ 143 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 144 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 145 /* 0x80010102 */ 146 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 147 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 148 | (0 << TIMING_CFG0_WRT_SHIFT) \ 149 | (0 << TIMING_CFG0_RRT_SHIFT) \ 150 | (0 << TIMING_CFG0_WWT_SHIFT) \ 151 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 152 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 153 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 154 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 155 /* 0x00220802 */ 156 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 157 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 158 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 159 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 160 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 161 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 162 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 163 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 164 /* 0x27256222 */ 165 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 166 | (4 << TIMING_CFG2_CPO_SHIFT) \ 167 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 168 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 169 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 170 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 171 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 172 /* 0x121048c5 */ 173 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 174 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 175 /* 0x03600100 */ 176 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 177 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 178 | SDRAM_CFG_DBW_32) 179 /* 0x43080000 */ 180 181 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 182 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 183 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 184 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 185 #define CONFIG_SYS_DDR_MODE2 0x00000000 186 187 /* 188 * Memory test 189 */ 190 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 191 #define CONFIG_SYS_MEMTEST_END 0x07f00000 192 193 /* 194 * The reserved memory 195 */ 196 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 197 198 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 199 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 200 201 /* 202 * Initial RAM Base Address Setup 203 */ 204 #define CONFIG_SYS_INIT_RAM_LOCK 1 205 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 206 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 207 #define CONFIG_SYS_GBL_DATA_OFFSET \ 208 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 209 210 /* 211 * Local Bus Configuration & Clock Setup 212 */ 213 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 214 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 215 #define CONFIG_SYS_LBC_LBCR 0x00040000 216 217 /* 218 * FLASH on the Local Bus 219 */ 220 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 221 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 222 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 223 224 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 225 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 226 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 227 228 /* Window base at flash base */ 229 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 230 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 231 232 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 233 | BR_PS_16 /* 16 bit port */ \ 234 | BR_MS_GPCM /* MSEL = GPCM */ \ 235 | BR_V) /* valid */ 236 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 237 | OR_UPM_XAM \ 238 | OR_GPCM_CSNT \ 239 | OR_GPCM_ACS_DIV2 \ 240 | OR_GPCM_XACS \ 241 | OR_GPCM_SCY_15 \ 242 | OR_GPCM_TRLX_SET \ 243 | OR_GPCM_EHTR_SET) 244 245 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 246 /* 127 64KB sectors and 8 8KB top sectors per device */ 247 #define CONFIG_SYS_MAX_FLASH_SECT 135 248 249 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 250 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 251 252 /* 253 * NAND Flash on the Local Bus 254 */ 255 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 256 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ 257 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 258 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 259 | BR_PS_8 /* 8 bit Port */ \ 260 | BR_MS_FCM /* MSEL = FCM */ \ 261 | BR_V) /* valid */ 262 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 263 | OR_FCM_CSCT \ 264 | OR_FCM_CST \ 265 | OR_FCM_CHT \ 266 | OR_FCM_SCY_1 \ 267 | OR_FCM_TRLX \ 268 | OR_FCM_EHTR) 269 /* 0xFFFF8396 */ 270 271 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 272 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 273 274 #ifdef CONFIG_VSC7385_ENET 275 #define CONFIG_TSEC2 276 /* VSC7385 Base address on CS2 */ 277 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 278 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 279 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 280 | BR_PS_8 /* 8-bit port */ \ 281 | BR_MS_GPCM /* MSEL = GPCM */ \ 282 | BR_V) /* valid */ 283 /* 0xF0000801 */ 284 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 285 | OR_GPCM_CSNT \ 286 | OR_GPCM_XACS \ 287 | OR_GPCM_SCY_15 \ 288 | OR_GPCM_SETA \ 289 | OR_GPCM_TRLX_SET \ 290 | OR_GPCM_EHTR_SET) 291 /* 0xFFFE09FF */ 292 /* Access window base at VSC7385 base */ 293 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 294 /* Access window size 128K */ 295 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 296 /* The flash address and size of the VSC7385 firmware image */ 297 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 298 #define CONFIG_VSC7385_IMAGE_SIZE 8192 299 #endif 300 /* 301 * Serial Port 302 */ 303 #define CONFIG_CONS_INDEX 1 304 #define CONFIG_SYS_NS16550_SERIAL 305 #define CONFIG_SYS_NS16550_REG_SIZE 1 306 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 307 308 #define CONFIG_SYS_BAUDRATE_TABLE \ 309 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 310 311 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 312 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 313 314 /* I2C */ 315 #define CONFIG_SYS_I2C 316 #define CONFIG_SYS_I2C_FSL 317 #define CONFIG_SYS_FSL_I2C_SPEED 400000 318 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 319 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 320 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 321 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 322 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 323 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 324 325 /* 326 * SPI on header J8 327 * 328 * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) 329 * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. 330 */ 331 #ifdef CONFIG_MPC8XXX_SPI 332 #define CONFIG_USE_SPIFLASH 333 #endif 334 335 /* 336 * Board info - revision and where boot from 337 */ 338 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 339 340 /* 341 * Config on-board RTC 342 */ 343 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 344 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 345 346 /* 347 * General PCI 348 * Addresses are mapped 1-1. 349 */ 350 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 351 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 352 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 353 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 354 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 355 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 356 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 357 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 358 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 359 360 /* enable PCIE clock */ 361 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 362 363 #define CONFIG_PCI_INDIRECT_BRIDGE 364 #define CONFIG_PCIE 365 366 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 367 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 368 369 /* 370 * TSEC 371 */ 372 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 373 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 374 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 375 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 376 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 377 378 /* 379 * TSEC ethernet configuration 380 */ 381 #define CONFIG_MII 1 /* MII PHY management */ 382 #define CONFIG_TSEC1_NAME "eTSEC0" 383 #define CONFIG_TSEC2_NAME "eTSEC1" 384 #define TSEC1_PHY_ADDR 2 385 #define TSEC2_PHY_ADDR 1 386 #define TSEC1_PHYIDX 0 387 #define TSEC2_PHYIDX 0 388 #define TSEC1_FLAGS TSEC_GIGABIT 389 #define TSEC2_FLAGS TSEC_GIGABIT 390 391 /* Options are: eTSEC[0-1] */ 392 #define CONFIG_ETHPRIME "eTSEC0" 393 394 /* 395 * Environment 396 */ 397 #define CONFIG_ENV_IS_IN_FLASH 1 398 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 399 CONFIG_SYS_MONITOR_LEN) 400 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 401 #define CONFIG_ENV_SIZE 0x2000 402 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 403 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 404 405 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 406 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 407 408 /* 409 * BOOTP options 410 */ 411 #define CONFIG_BOOTP_BOOTFILESIZE 412 #define CONFIG_BOOTP_BOOTPATH 413 #define CONFIG_BOOTP_GATEWAY 414 #define CONFIG_BOOTP_HOSTNAME 415 416 /* 417 * Command line configuration. 418 */ 419 #define CONFIG_CMD_PCI 420 421 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 422 423 /* 424 * Miscellaneous configurable options 425 */ 426 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 427 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 428 429 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 430 431 /* Print Buffer Size */ 432 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 433 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 434 /* Boot Argument Buffer Size */ 435 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 436 437 /* 438 * For booting Linux, the board info and command line data 439 * have to be in the first 256 MB of memory, since this is 440 * the maximum mapped by the Linux kernel during initialization. 441 */ 442 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 443 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 444 445 /* 446 * Core HID Setup 447 */ 448 #define CONFIG_SYS_HID0_INIT 0x000000000 449 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 450 HID0_ENABLE_INSTRUCTION_CACHE | \ 451 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 452 #define CONFIG_SYS_HID2 HID2_HBE 453 454 /* 455 * MMU Setup 456 */ 457 458 /* DDR: cache cacheable */ 459 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 460 BATL_MEMCOHERENCE) 461 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 462 BATU_VS | BATU_VP) 463 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 464 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 465 466 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 467 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 468 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 469 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 470 BATU_VP) 471 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 472 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 473 474 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 475 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 476 BATL_MEMCOHERENCE) 477 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 478 BATU_VS | BATU_VP) 479 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 480 BATL_CACHEINHIBIT | \ 481 BATL_GUARDEDSTORAGE) 482 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 483 484 /* Stack in dcache: cacheable, no memory coherence */ 485 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 486 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 487 BATU_VS | BATU_VP) 488 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 489 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 490 491 /* 492 * Environment Configuration 493 */ 494 495 #define CONFIG_ENV_OVERWRITE 496 497 #if defined(CONFIG_TSEC_ENET) 498 #define CONFIG_HAS_ETH0 499 #define CONFIG_HAS_ETH1 500 #endif 501 502 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 503 504 505 #define CONFIG_EXTRA_ENV_SETTINGS \ 506 "netdev=eth0\0" \ 507 "consoledev=ttyS0\0" \ 508 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 509 "nfsroot=${serverip}:${rootpath}\0" \ 510 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 511 "addip=setenv bootargs ${bootargs} " \ 512 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 513 ":${hostname}:${netdev}:off panic=1\0" \ 514 "addtty=setenv bootargs ${bootargs}" \ 515 " console=${consoledev},${baudrate}\0" \ 516 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 517 "addmisc=setenv bootargs ${bootargs}\0" \ 518 "kernel_addr=FE080000\0" \ 519 "fdt_addr=FE280000\0" \ 520 "ramdisk_addr=FE290000\0" \ 521 "u-boot=mpc8308rdb/u-boot.bin\0" \ 522 "kernel_addr_r=1000000\0" \ 523 "fdt_addr_r=C00000\0" \ 524 "hostname=mpc8308rdb\0" \ 525 "bootfile=mpc8308rdb/uImage\0" \ 526 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ 527 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 528 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 529 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 530 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 531 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 532 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 533 "tftp ${fdt_addr_r} ${fdtfile};" \ 534 "run nfsargs addip addtty addmtd addmisc;" \ 535 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 536 "bootcmd=run flash_self\0" \ 537 "load=tftp ${loadaddr} ${u-boot}\0" \ 538 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 539 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 540 " +${filesize};cp.b ${fileaddr} " \ 541 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 542 "upd=run load update\0" \ 543 544 #endif /* __CONFIG_H */ 545