1 /* 2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC830x 1 /* MPC830x family */ 17 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 18 #define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ 19 20 #define CONFIG_SYS_TEXT_BASE 0xFE000000 21 22 #define CONFIG_MISC_INIT_R 23 24 #ifdef CONFIG_MMC 25 #define CONFIG_FSL_ESDHC 26 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 27 #define CONFIG_SYS_FSL_ESDHC_USE_PIO 28 29 #define CONFIG_GENERIC_MMC 30 #endif 31 32 /* 33 * On-board devices 34 * 35 * TSEC1 is SoC TSEC 36 * TSEC2 is VSC switch 37 */ 38 #define CONFIG_TSEC1 39 #define CONFIG_VSC7385_ENET 40 41 /* 42 * System Clock Setup 43 */ 44 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 45 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 46 47 /* 48 * Hardware Reset Configuration Word 49 * if CLKIN is 66.66MHz, then 50 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 51 * We choose the A type silicon as default, so the core is 400Mhz. 52 */ 53 #define CONFIG_SYS_HRCW_LOW (\ 54 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 55 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 56 HRCWL_SVCOD_DIV_2 |\ 57 HRCWL_CSB_TO_CLKIN_4X1 |\ 58 HRCWL_CORE_TO_CSB_3X1) 59 /* 60 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 61 * in 8308's HRCWH according to the manual, but original Freescale's 62 * code has them and I've expirienced some problems using the board 63 * with BDI3000 attached when I've tried to set these bits to zero 64 * (UART doesn't work after the 'reset run' command). 65 */ 66 #define CONFIG_SYS_HRCW_HIGH (\ 67 HRCWH_PCI_HOST |\ 68 HRCWH_PCI1_ARBITER_ENABLE |\ 69 HRCWH_CORE_ENABLE |\ 70 HRCWH_FROM_0X00000100 |\ 71 HRCWH_BOOTSEQ_DISABLE |\ 72 HRCWH_SW_WATCHDOG_DISABLE |\ 73 HRCWH_ROM_LOC_LOCAL_16BIT |\ 74 HRCWH_RL_EXT_LEGACY |\ 75 HRCWH_TSEC1M_IN_RGMII |\ 76 HRCWH_TSEC2M_IN_RGMII |\ 77 HRCWH_BIG_ENDIAN) 78 79 /* 80 * System IO Config 81 */ 82 #define CONFIG_SYS_SICRH (\ 83 SICRH_ESDHC_A_SD |\ 84 SICRH_ESDHC_B_SD |\ 85 SICRH_ESDHC_C_SD |\ 86 SICRH_GPIO_A_TSEC2 |\ 87 SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ 88 SICRH_IEEE1588_A_GPIO |\ 89 SICRH_USB |\ 90 SICRH_GTM_GPIO |\ 91 SICRH_IEEE1588_B_GPIO |\ 92 SICRH_ETSEC2_CRS |\ 93 SICRH_GPIOSEL_1 |\ 94 SICRH_TMROBI_V3P3 |\ 95 SICRH_TSOBI1_V2P5 |\ 96 SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ 97 #define CONFIG_SYS_SICRL (\ 98 SICRL_SPI_PF0 |\ 99 SICRL_UART_PF0 |\ 100 SICRL_IRQ_PF0 |\ 101 SICRL_I2C2_PF0 |\ 102 SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ 103 104 /* 105 * IMMR new address 106 */ 107 #define CONFIG_SYS_IMMR 0xE0000000 108 109 /* 110 * SERDES 111 */ 112 #define CONFIG_FSL_SERDES 113 #define CONFIG_FSL_SERDES1 0xe3000 114 115 /* 116 * Arbiter Setup 117 */ 118 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 119 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 120 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 121 122 /* 123 * DDR Setup 124 */ 125 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 126 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 127 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 128 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 129 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 130 | DDRCDR_PZ_LOZ \ 131 | DDRCDR_NZ_LOZ \ 132 | DDRCDR_ODT \ 133 | DDRCDR_Q_DRN) 134 /* 0x7b880001 */ 135 /* 136 * Manually set up DDR parameters 137 * consist of two chips HY5PS12621BFP-C4 from HYNIX 138 */ 139 140 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 141 142 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 143 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 144 | CSCONFIG_ODT_RD_NEVER \ 145 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 146 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 147 /* 0x80010102 */ 148 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 149 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 150 | (0 << TIMING_CFG0_WRT_SHIFT) \ 151 | (0 << TIMING_CFG0_RRT_SHIFT) \ 152 | (0 << TIMING_CFG0_WWT_SHIFT) \ 153 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 154 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 155 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 156 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 157 /* 0x00220802 */ 158 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 159 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 160 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 161 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 162 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 163 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 164 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 165 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 166 /* 0x27256222 */ 167 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 168 | (4 << TIMING_CFG2_CPO_SHIFT) \ 169 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 170 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 171 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 172 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 173 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 174 /* 0x121048c5 */ 175 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 176 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 177 /* 0x03600100 */ 178 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 179 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 180 | SDRAM_CFG_DBW_32) 181 /* 0x43080000 */ 182 183 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 184 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 185 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 186 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 187 #define CONFIG_SYS_DDR_MODE2 0x00000000 188 189 /* 190 * Memory test 191 */ 192 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 193 #define CONFIG_SYS_MEMTEST_END 0x07f00000 194 195 /* 196 * The reserved memory 197 */ 198 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 199 200 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 201 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 202 203 /* 204 * Initial RAM Base Address Setup 205 */ 206 #define CONFIG_SYS_INIT_RAM_LOCK 1 207 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 208 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 209 #define CONFIG_SYS_GBL_DATA_OFFSET \ 210 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 211 212 /* 213 * Local Bus Configuration & Clock Setup 214 */ 215 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 216 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 217 #define CONFIG_SYS_LBC_LBCR 0x00040000 218 219 /* 220 * FLASH on the Local Bus 221 */ 222 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 223 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 224 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 225 226 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 227 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 228 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 229 230 /* Window base at flash base */ 231 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 232 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 233 234 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 235 | BR_PS_16 /* 16 bit port */ \ 236 | BR_MS_GPCM /* MSEL = GPCM */ \ 237 | BR_V) /* valid */ 238 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 239 | OR_UPM_XAM \ 240 | OR_GPCM_CSNT \ 241 | OR_GPCM_ACS_DIV2 \ 242 | OR_GPCM_XACS \ 243 | OR_GPCM_SCY_15 \ 244 | OR_GPCM_TRLX_SET \ 245 | OR_GPCM_EHTR_SET) 246 247 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 248 /* 127 64KB sectors and 8 8KB top sectors per device */ 249 #define CONFIG_SYS_MAX_FLASH_SECT 135 250 251 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 252 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 253 254 /* 255 * NAND Flash on the Local Bus 256 */ 257 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 258 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ 259 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 260 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 261 | BR_PS_8 /* 8 bit Port */ \ 262 | BR_MS_FCM /* MSEL = FCM */ \ 263 | BR_V) /* valid */ 264 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 265 | OR_FCM_CSCT \ 266 | OR_FCM_CST \ 267 | OR_FCM_CHT \ 268 | OR_FCM_SCY_1 \ 269 | OR_FCM_TRLX \ 270 | OR_FCM_EHTR) 271 /* 0xFFFF8396 */ 272 273 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 274 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 275 276 #ifdef CONFIG_VSC7385_ENET 277 #define CONFIG_TSEC2 278 /* VSC7385 Base address on CS2 */ 279 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 280 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 281 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 282 | BR_PS_8 /* 8-bit port */ \ 283 | BR_MS_GPCM /* MSEL = GPCM */ \ 284 | BR_V) /* valid */ 285 /* 0xF0000801 */ 286 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 287 | OR_GPCM_CSNT \ 288 | OR_GPCM_XACS \ 289 | OR_GPCM_SCY_15 \ 290 | OR_GPCM_SETA \ 291 | OR_GPCM_TRLX_SET \ 292 | OR_GPCM_EHTR_SET) 293 /* 0xFFFE09FF */ 294 /* Access window base at VSC7385 base */ 295 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 296 /* Access window size 128K */ 297 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 298 /* The flash address and size of the VSC7385 firmware image */ 299 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 300 #define CONFIG_VSC7385_IMAGE_SIZE 8192 301 #endif 302 /* 303 * Serial Port 304 */ 305 #define CONFIG_CONS_INDEX 1 306 #define CONFIG_SYS_NS16550_SERIAL 307 #define CONFIG_SYS_NS16550_REG_SIZE 1 308 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 309 310 #define CONFIG_SYS_BAUDRATE_TABLE \ 311 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 312 313 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 314 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 315 316 /* I2C */ 317 #define CONFIG_SYS_I2C 318 #define CONFIG_SYS_I2C_FSL 319 #define CONFIG_SYS_FSL_I2C_SPEED 400000 320 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 321 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 322 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 323 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 324 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 325 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 326 327 /* 328 * SPI on header J8 329 * 330 * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) 331 * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. 332 */ 333 #ifdef CONFIG_MPC8XXX_SPI 334 #define CONFIG_USE_SPIFLASH 335 #endif 336 337 /* 338 * Board info - revision and where boot from 339 */ 340 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 341 342 /* 343 * Config on-board RTC 344 */ 345 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 346 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 347 348 /* 349 * General PCI 350 * Addresses are mapped 1-1. 351 */ 352 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 353 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 354 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 355 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 356 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 357 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 358 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 359 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 360 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 361 362 /* enable PCIE clock */ 363 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 364 365 #define CONFIG_PCI_INDIRECT_BRIDGE 366 #define CONFIG_PCIE 367 368 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 369 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 370 371 /* 372 * TSEC 373 */ 374 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 375 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 376 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 377 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 378 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 379 380 /* 381 * TSEC ethernet configuration 382 */ 383 #define CONFIG_MII 1 /* MII PHY management */ 384 #define CONFIG_TSEC1_NAME "eTSEC0" 385 #define CONFIG_TSEC2_NAME "eTSEC1" 386 #define TSEC1_PHY_ADDR 2 387 #define TSEC2_PHY_ADDR 1 388 #define TSEC1_PHYIDX 0 389 #define TSEC2_PHYIDX 0 390 #define TSEC1_FLAGS TSEC_GIGABIT 391 #define TSEC2_FLAGS TSEC_GIGABIT 392 393 /* Options are: eTSEC[0-1] */ 394 #define CONFIG_ETHPRIME "eTSEC0" 395 396 /* 397 * Environment 398 */ 399 #define CONFIG_ENV_IS_IN_FLASH 1 400 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 401 CONFIG_SYS_MONITOR_LEN) 402 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 403 #define CONFIG_ENV_SIZE 0x2000 404 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 405 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 406 407 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 408 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 409 410 /* 411 * BOOTP options 412 */ 413 #define CONFIG_BOOTP_BOOTFILESIZE 414 #define CONFIG_BOOTP_BOOTPATH 415 #define CONFIG_BOOTP_GATEWAY 416 #define CONFIG_BOOTP_HOSTNAME 417 418 /* 419 * Command line configuration. 420 */ 421 #define CONFIG_CMD_DATE 422 #define CONFIG_CMD_PCI 423 424 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 425 426 /* 427 * Miscellaneous configurable options 428 */ 429 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 430 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 431 432 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 433 434 /* Print Buffer Size */ 435 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 436 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 437 /* Boot Argument Buffer Size */ 438 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 439 440 /* 441 * For booting Linux, the board info and command line data 442 * have to be in the first 256 MB of memory, since this is 443 * the maximum mapped by the Linux kernel during initialization. 444 */ 445 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 446 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 447 448 /* 449 * Core HID Setup 450 */ 451 #define CONFIG_SYS_HID0_INIT 0x000000000 452 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 453 HID0_ENABLE_INSTRUCTION_CACHE | \ 454 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 455 #define CONFIG_SYS_HID2 HID2_HBE 456 457 /* 458 * MMU Setup 459 */ 460 461 /* DDR: cache cacheable */ 462 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 463 BATL_MEMCOHERENCE) 464 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 465 BATU_VS | BATU_VP) 466 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 467 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 468 469 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 470 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 471 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 472 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 473 BATU_VP) 474 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 475 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 476 477 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 478 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 479 BATL_MEMCOHERENCE) 480 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 481 BATU_VS | BATU_VP) 482 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 483 BATL_CACHEINHIBIT | \ 484 BATL_GUARDEDSTORAGE) 485 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 486 487 /* Stack in dcache: cacheable, no memory coherence */ 488 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 489 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 490 BATU_VS | BATU_VP) 491 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 492 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 493 494 /* 495 * Environment Configuration 496 */ 497 498 #define CONFIG_ENV_OVERWRITE 499 500 #if defined(CONFIG_TSEC_ENET) 501 #define CONFIG_HAS_ETH0 502 #define CONFIG_HAS_ETH1 503 #endif 504 505 #define CONFIG_BAUDRATE 115200 506 507 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 508 509 510 #define CONFIG_EXTRA_ENV_SETTINGS \ 511 "netdev=eth0\0" \ 512 "consoledev=ttyS0\0" \ 513 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 514 "nfsroot=${serverip}:${rootpath}\0" \ 515 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 516 "addip=setenv bootargs ${bootargs} " \ 517 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 518 ":${hostname}:${netdev}:off panic=1\0" \ 519 "addtty=setenv bootargs ${bootargs}" \ 520 " console=${consoledev},${baudrate}\0" \ 521 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 522 "addmisc=setenv bootargs ${bootargs}\0" \ 523 "kernel_addr=FE080000\0" \ 524 "fdt_addr=FE280000\0" \ 525 "ramdisk_addr=FE290000\0" \ 526 "u-boot=mpc8308rdb/u-boot.bin\0" \ 527 "kernel_addr_r=1000000\0" \ 528 "fdt_addr_r=C00000\0" \ 529 "hostname=mpc8308rdb\0" \ 530 "bootfile=mpc8308rdb/uImage\0" \ 531 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ 532 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 533 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 534 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 535 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 536 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 537 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 538 "tftp ${fdt_addr_r} ${fdtfile};" \ 539 "run nfsargs addip addtty addmtd addmisc;" \ 540 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 541 "bootcmd=run flash_self\0" \ 542 "load=tftp ${loadaddr} ${u-boot}\0" \ 543 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 544 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 545 " +${filesize};cp.b ${fileaddr} " \ 546 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 547 "upd=run load update\0" \ 548 549 #endif /* __CONFIG_H */ 550