1 /* 2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC830x 1 /* MPC830x family */ 17 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 18 19 #define CONFIG_MISC_INIT_R 20 21 #ifdef CONFIG_MMC 22 #define CONFIG_FSL_ESDHC 23 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 24 #define CONFIG_SYS_FSL_ESDHC_USE_PIO 25 #endif 26 27 /* 28 * On-board devices 29 * 30 * TSEC1 is SoC TSEC 31 * TSEC2 is VSC switch 32 */ 33 #define CONFIG_TSEC1 34 #define CONFIG_VSC7385_ENET 35 36 /* 37 * System Clock Setup 38 */ 39 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 40 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 41 42 /* 43 * Hardware Reset Configuration Word 44 * if CLKIN is 66.66MHz, then 45 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 46 * We choose the A type silicon as default, so the core is 400Mhz. 47 */ 48 #define CONFIG_SYS_HRCW_LOW (\ 49 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 50 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 51 HRCWL_SVCOD_DIV_2 |\ 52 HRCWL_CSB_TO_CLKIN_4X1 |\ 53 HRCWL_CORE_TO_CSB_3X1) 54 /* 55 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 56 * in 8308's HRCWH according to the manual, but original Freescale's 57 * code has them and I've expirienced some problems using the board 58 * with BDI3000 attached when I've tried to set these bits to zero 59 * (UART doesn't work after the 'reset run' command). 60 */ 61 #define CONFIG_SYS_HRCW_HIGH (\ 62 HRCWH_PCI_HOST |\ 63 HRCWH_PCI1_ARBITER_ENABLE |\ 64 HRCWH_CORE_ENABLE |\ 65 HRCWH_FROM_0X00000100 |\ 66 HRCWH_BOOTSEQ_DISABLE |\ 67 HRCWH_SW_WATCHDOG_DISABLE |\ 68 HRCWH_ROM_LOC_LOCAL_16BIT |\ 69 HRCWH_RL_EXT_LEGACY |\ 70 HRCWH_TSEC1M_IN_RGMII |\ 71 HRCWH_TSEC2M_IN_RGMII |\ 72 HRCWH_BIG_ENDIAN) 73 74 /* 75 * System IO Config 76 */ 77 #define CONFIG_SYS_SICRH (\ 78 SICRH_ESDHC_A_SD |\ 79 SICRH_ESDHC_B_SD |\ 80 SICRH_ESDHC_C_SD |\ 81 SICRH_GPIO_A_TSEC2 |\ 82 SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ 83 SICRH_IEEE1588_A_GPIO |\ 84 SICRH_USB |\ 85 SICRH_GTM_GPIO |\ 86 SICRH_IEEE1588_B_GPIO |\ 87 SICRH_ETSEC2_CRS |\ 88 SICRH_GPIOSEL_1 |\ 89 SICRH_TMROBI_V3P3 |\ 90 SICRH_TSOBI1_V2P5 |\ 91 SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ 92 #define CONFIG_SYS_SICRL (\ 93 SICRL_SPI_PF0 |\ 94 SICRL_UART_PF0 |\ 95 SICRL_IRQ_PF0 |\ 96 SICRL_I2C2_PF0 |\ 97 SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ 98 99 /* 100 * IMMR new address 101 */ 102 #define CONFIG_SYS_IMMR 0xE0000000 103 104 /* 105 * SERDES 106 */ 107 #define CONFIG_FSL_SERDES 108 #define CONFIG_FSL_SERDES1 0xe3000 109 110 /* 111 * Arbiter Setup 112 */ 113 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 114 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 115 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 116 117 /* 118 * DDR Setup 119 */ 120 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 121 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 122 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 123 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 124 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 125 | DDRCDR_PZ_LOZ \ 126 | DDRCDR_NZ_LOZ \ 127 | DDRCDR_ODT \ 128 | DDRCDR_Q_DRN) 129 /* 0x7b880001 */ 130 /* 131 * Manually set up DDR parameters 132 * consist of two chips HY5PS12621BFP-C4 from HYNIX 133 */ 134 135 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 136 137 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 138 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 139 | CSCONFIG_ODT_RD_NEVER \ 140 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 141 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 142 /* 0x80010102 */ 143 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 144 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 145 | (0 << TIMING_CFG0_WRT_SHIFT) \ 146 | (0 << TIMING_CFG0_RRT_SHIFT) \ 147 | (0 << TIMING_CFG0_WWT_SHIFT) \ 148 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 149 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 150 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 151 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 152 /* 0x00220802 */ 153 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 154 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 155 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 156 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 157 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 158 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 159 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 160 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 161 /* 0x27256222 */ 162 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 163 | (4 << TIMING_CFG2_CPO_SHIFT) \ 164 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 165 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 166 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 167 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 168 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 169 /* 0x121048c5 */ 170 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 171 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 172 /* 0x03600100 */ 173 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 174 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 175 | SDRAM_CFG_DBW_32) 176 /* 0x43080000 */ 177 178 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 179 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 180 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 181 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 182 #define CONFIG_SYS_DDR_MODE2 0x00000000 183 184 /* 185 * Memory test 186 */ 187 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 188 #define CONFIG_SYS_MEMTEST_END 0x07f00000 189 190 /* 191 * The reserved memory 192 */ 193 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 194 195 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 196 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 197 198 /* 199 * Initial RAM Base Address Setup 200 */ 201 #define CONFIG_SYS_INIT_RAM_LOCK 1 202 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 203 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 204 #define CONFIG_SYS_GBL_DATA_OFFSET \ 205 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 206 207 /* 208 * Local Bus Configuration & Clock Setup 209 */ 210 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 211 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 212 #define CONFIG_SYS_LBC_LBCR 0x00040000 213 214 /* 215 * FLASH on the Local Bus 216 */ 217 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 218 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 219 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 220 221 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 222 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 223 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 224 225 /* Window base at flash base */ 226 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 227 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 228 229 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 230 | BR_PS_16 /* 16 bit port */ \ 231 | BR_MS_GPCM /* MSEL = GPCM */ \ 232 | BR_V) /* valid */ 233 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 234 | OR_UPM_XAM \ 235 | OR_GPCM_CSNT \ 236 | OR_GPCM_ACS_DIV2 \ 237 | OR_GPCM_XACS \ 238 | OR_GPCM_SCY_15 \ 239 | OR_GPCM_TRLX_SET \ 240 | OR_GPCM_EHTR_SET) 241 242 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 243 /* 127 64KB sectors and 8 8KB top sectors per device */ 244 #define CONFIG_SYS_MAX_FLASH_SECT 135 245 246 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 247 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 248 249 /* 250 * NAND Flash on the Local Bus 251 */ 252 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 253 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ 254 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 255 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 256 | BR_PS_8 /* 8 bit Port */ \ 257 | BR_MS_FCM /* MSEL = FCM */ \ 258 | BR_V) /* valid */ 259 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 260 | OR_FCM_CSCT \ 261 | OR_FCM_CST \ 262 | OR_FCM_CHT \ 263 | OR_FCM_SCY_1 \ 264 | OR_FCM_TRLX \ 265 | OR_FCM_EHTR) 266 /* 0xFFFF8396 */ 267 268 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 269 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 270 271 #ifdef CONFIG_VSC7385_ENET 272 #define CONFIG_TSEC2 273 /* VSC7385 Base address on CS2 */ 274 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 275 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 276 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 277 | BR_PS_8 /* 8-bit port */ \ 278 | BR_MS_GPCM /* MSEL = GPCM */ \ 279 | BR_V) /* valid */ 280 /* 0xF0000801 */ 281 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 282 | OR_GPCM_CSNT \ 283 | OR_GPCM_XACS \ 284 | OR_GPCM_SCY_15 \ 285 | OR_GPCM_SETA \ 286 | OR_GPCM_TRLX_SET \ 287 | OR_GPCM_EHTR_SET) 288 /* 0xFFFE09FF */ 289 /* Access window base at VSC7385 base */ 290 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 291 /* Access window size 128K */ 292 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 293 /* The flash address and size of the VSC7385 firmware image */ 294 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 295 #define CONFIG_VSC7385_IMAGE_SIZE 8192 296 #endif 297 /* 298 * Serial Port 299 */ 300 #define CONFIG_CONS_INDEX 1 301 #define CONFIG_SYS_NS16550_SERIAL 302 #define CONFIG_SYS_NS16550_REG_SIZE 1 303 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 304 305 #define CONFIG_SYS_BAUDRATE_TABLE \ 306 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 307 308 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 309 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 310 311 /* I2C */ 312 #define CONFIG_SYS_I2C 313 #define CONFIG_SYS_I2C_FSL 314 #define CONFIG_SYS_FSL_I2C_SPEED 400000 315 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 316 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 317 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 318 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 319 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 320 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 321 322 /* 323 * SPI on header J8 324 * 325 * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) 326 * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. 327 */ 328 #ifdef CONFIG_MPC8XXX_SPI 329 #define CONFIG_USE_SPIFLASH 330 #endif 331 332 /* 333 * Board info - revision and where boot from 334 */ 335 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 336 337 /* 338 * Config on-board RTC 339 */ 340 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 341 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 342 343 /* 344 * General PCI 345 * Addresses are mapped 1-1. 346 */ 347 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 348 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 349 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 350 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 351 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 352 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 353 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 354 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 355 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 356 357 /* enable PCIE clock */ 358 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 359 360 #define CONFIG_PCI_INDIRECT_BRIDGE 361 #define CONFIG_PCIE 362 363 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 364 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 365 366 /* 367 * TSEC 368 */ 369 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 370 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 371 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 372 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 373 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 374 375 /* 376 * TSEC ethernet configuration 377 */ 378 #define CONFIG_MII 1 /* MII PHY management */ 379 #define CONFIG_TSEC1_NAME "eTSEC0" 380 #define CONFIG_TSEC2_NAME "eTSEC1" 381 #define TSEC1_PHY_ADDR 2 382 #define TSEC2_PHY_ADDR 1 383 #define TSEC1_PHYIDX 0 384 #define TSEC2_PHYIDX 0 385 #define TSEC1_FLAGS TSEC_GIGABIT 386 #define TSEC2_FLAGS TSEC_GIGABIT 387 388 /* Options are: eTSEC[0-1] */ 389 #define CONFIG_ETHPRIME "eTSEC0" 390 391 /* 392 * Environment 393 */ 394 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 395 CONFIG_SYS_MONITOR_LEN) 396 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 397 #define CONFIG_ENV_SIZE 0x2000 398 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 399 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 400 401 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 402 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 403 404 /* 405 * BOOTP options 406 */ 407 #define CONFIG_BOOTP_BOOTFILESIZE 408 #define CONFIG_BOOTP_BOOTPATH 409 #define CONFIG_BOOTP_GATEWAY 410 #define CONFIG_BOOTP_HOSTNAME 411 412 /* 413 * Command line configuration. 414 */ 415 416 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 417 418 /* 419 * Miscellaneous configurable options 420 */ 421 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 422 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 423 424 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 425 426 /* Boot Argument Buffer Size */ 427 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 428 429 /* 430 * For booting Linux, the board info and command line data 431 * have to be in the first 256 MB of memory, since this is 432 * the maximum mapped by the Linux kernel during initialization. 433 */ 434 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 435 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 436 437 /* 438 * Core HID Setup 439 */ 440 #define CONFIG_SYS_HID0_INIT 0x000000000 441 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 442 HID0_ENABLE_INSTRUCTION_CACHE | \ 443 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 444 #define CONFIG_SYS_HID2 HID2_HBE 445 446 /* 447 * MMU Setup 448 */ 449 450 /* DDR: cache cacheable */ 451 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 452 BATL_MEMCOHERENCE) 453 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 454 BATU_VS | BATU_VP) 455 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 456 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 457 458 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 459 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 460 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 461 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 462 BATU_VP) 463 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 464 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 465 466 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 467 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 468 BATL_MEMCOHERENCE) 469 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 470 BATU_VS | BATU_VP) 471 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 472 BATL_CACHEINHIBIT | \ 473 BATL_GUARDEDSTORAGE) 474 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 475 476 /* Stack in dcache: cacheable, no memory coherence */ 477 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 478 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 479 BATU_VS | BATU_VP) 480 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 481 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 482 483 /* 484 * Environment Configuration 485 */ 486 487 #define CONFIG_ENV_OVERWRITE 488 489 #if defined(CONFIG_TSEC_ENET) 490 #define CONFIG_HAS_ETH0 491 #define CONFIG_HAS_ETH1 492 #endif 493 494 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 495 496 497 #define CONFIG_EXTRA_ENV_SETTINGS \ 498 "netdev=eth0\0" \ 499 "consoledev=ttyS0\0" \ 500 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 501 "nfsroot=${serverip}:${rootpath}\0" \ 502 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 503 "addip=setenv bootargs ${bootargs} " \ 504 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 505 ":${hostname}:${netdev}:off panic=1\0" \ 506 "addtty=setenv bootargs ${bootargs}" \ 507 " console=${consoledev},${baudrate}\0" \ 508 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 509 "addmisc=setenv bootargs ${bootargs}\0" \ 510 "kernel_addr=FE080000\0" \ 511 "fdt_addr=FE280000\0" \ 512 "ramdisk_addr=FE290000\0" \ 513 "u-boot=mpc8308rdb/u-boot.bin\0" \ 514 "kernel_addr_r=1000000\0" \ 515 "fdt_addr_r=C00000\0" \ 516 "hostname=mpc8308rdb\0" \ 517 "bootfile=mpc8308rdb/uImage\0" \ 518 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ 519 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 520 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 521 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 522 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 523 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 524 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 525 "tftp ${fdt_addr_r} ${fdtfile};" \ 526 "run nfsargs addip addtty addmtd addmisc;" \ 527 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 528 "bootcmd=run flash_self\0" \ 529 "load=tftp ${loadaddr} ${u-boot}\0" \ 530 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 531 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 532 " +${filesize};cp.b ${fileaddr} " \ 533 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 534 "upd=run load update\0" \ 535 536 #endif /* __CONFIG_H */ 537