1 /* 2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_DISPLAY_BOARDINFO 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_E300 1 /* E300 family */ 18 #define CONFIG_MPC830x 1 /* MPC830x family */ 19 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 20 #define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ 21 22 #define CONFIG_SYS_TEXT_BASE 0xFE000000 23 24 #define CONFIG_MISC_INIT_R 25 26 /* new uImage format support */ 27 #define CONFIG_FIT 1 28 #define CONFIG_FIT_VERBOSE 1 29 30 #define CONFIG_MMC 1 31 32 #ifdef CONFIG_MMC 33 #define CONFIG_FSL_ESDHC 34 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 35 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 36 #define CONFIG_SYS_FSL_ESDHC_USE_PIO 37 38 #define CONFIG_CMD_MMC 39 #define CONFIG_GENERIC_MMC 40 #define CONFIG_CMD_FAT 41 #define CONFIG_DOS_PARTITION 42 #endif 43 44 /* 45 * On-board devices 46 * 47 * TSEC1 is SoC TSEC 48 * TSEC2 is VSC switch 49 */ 50 #define CONFIG_TSEC1 51 #define CONFIG_VSC7385_ENET 52 53 /* 54 * System Clock Setup 55 */ 56 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 57 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 58 59 /* 60 * Hardware Reset Configuration Word 61 * if CLKIN is 66.66MHz, then 62 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 63 * We choose the A type silicon as default, so the core is 400Mhz. 64 */ 65 #define CONFIG_SYS_HRCW_LOW (\ 66 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 67 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 68 HRCWL_SVCOD_DIV_2 |\ 69 HRCWL_CSB_TO_CLKIN_4X1 |\ 70 HRCWL_CORE_TO_CSB_3X1) 71 /* 72 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 73 * in 8308's HRCWH according to the manual, but original Freescale's 74 * code has them and I've expirienced some problems using the board 75 * with BDI3000 attached when I've tried to set these bits to zero 76 * (UART doesn't work after the 'reset run' command). 77 */ 78 #define CONFIG_SYS_HRCW_HIGH (\ 79 HRCWH_PCI_HOST |\ 80 HRCWH_PCI1_ARBITER_ENABLE |\ 81 HRCWH_CORE_ENABLE |\ 82 HRCWH_FROM_0X00000100 |\ 83 HRCWH_BOOTSEQ_DISABLE |\ 84 HRCWH_SW_WATCHDOG_DISABLE |\ 85 HRCWH_ROM_LOC_LOCAL_16BIT |\ 86 HRCWH_RL_EXT_LEGACY |\ 87 HRCWH_TSEC1M_IN_RGMII |\ 88 HRCWH_TSEC2M_IN_RGMII |\ 89 HRCWH_BIG_ENDIAN) 90 91 /* 92 * System IO Config 93 */ 94 #define CONFIG_SYS_SICRH (\ 95 SICRH_ESDHC_A_SD |\ 96 SICRH_ESDHC_B_SD |\ 97 SICRH_ESDHC_C_SD |\ 98 SICRH_GPIO_A_TSEC2 |\ 99 SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ 100 SICRH_IEEE1588_A_GPIO |\ 101 SICRH_USB |\ 102 SICRH_GTM_GPIO |\ 103 SICRH_IEEE1588_B_GPIO |\ 104 SICRH_ETSEC2_CRS |\ 105 SICRH_GPIOSEL_1 |\ 106 SICRH_TMROBI_V3P3 |\ 107 SICRH_TSOBI1_V2P5 |\ 108 SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ 109 #define CONFIG_SYS_SICRL (\ 110 SICRL_SPI_PF0 |\ 111 SICRL_UART_PF0 |\ 112 SICRL_IRQ_PF0 |\ 113 SICRL_I2C2_PF0 |\ 114 SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ 115 116 /* 117 * IMMR new address 118 */ 119 #define CONFIG_SYS_IMMR 0xE0000000 120 121 /* 122 * SERDES 123 */ 124 #define CONFIG_FSL_SERDES 125 #define CONFIG_FSL_SERDES1 0xe3000 126 127 /* 128 * Arbiter Setup 129 */ 130 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 131 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 132 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 133 134 /* 135 * DDR Setup 136 */ 137 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 138 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 139 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 140 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 141 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 142 | DDRCDR_PZ_LOZ \ 143 | DDRCDR_NZ_LOZ \ 144 | DDRCDR_ODT \ 145 | DDRCDR_Q_DRN) 146 /* 0x7b880001 */ 147 /* 148 * Manually set up DDR parameters 149 * consist of two chips HY5PS12621BFP-C4 from HYNIX 150 */ 151 152 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 153 154 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 155 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 156 | CSCONFIG_ODT_RD_NEVER \ 157 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 158 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 159 /* 0x80010102 */ 160 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 161 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 162 | (0 << TIMING_CFG0_WRT_SHIFT) \ 163 | (0 << TIMING_CFG0_RRT_SHIFT) \ 164 | (0 << TIMING_CFG0_WWT_SHIFT) \ 165 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 166 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 167 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 168 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 169 /* 0x00220802 */ 170 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 171 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 172 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 173 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 174 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 175 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 176 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 177 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 178 /* 0x27256222 */ 179 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 180 | (4 << TIMING_CFG2_CPO_SHIFT) \ 181 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 182 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 183 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 184 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 185 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 186 /* 0x121048c5 */ 187 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 188 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 189 /* 0x03600100 */ 190 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 191 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 192 | SDRAM_CFG_DBW_32) 193 /* 0x43080000 */ 194 195 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 196 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 197 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 198 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 199 #define CONFIG_SYS_DDR_MODE2 0x00000000 200 201 /* 202 * Memory test 203 */ 204 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 205 #define CONFIG_SYS_MEMTEST_END 0x07f00000 206 207 /* 208 * The reserved memory 209 */ 210 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 211 212 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 213 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 214 215 /* 216 * Initial RAM Base Address Setup 217 */ 218 #define CONFIG_SYS_INIT_RAM_LOCK 1 219 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 220 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 221 #define CONFIG_SYS_GBL_DATA_OFFSET \ 222 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 223 224 /* 225 * Local Bus Configuration & Clock Setup 226 */ 227 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 228 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 229 #define CONFIG_SYS_LBC_LBCR 0x00040000 230 231 /* 232 * FLASH on the Local Bus 233 */ 234 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 235 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 236 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 237 238 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 239 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 240 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 241 242 /* Window base at flash base */ 243 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 244 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 245 246 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 247 | BR_PS_16 /* 16 bit port */ \ 248 | BR_MS_GPCM /* MSEL = GPCM */ \ 249 | BR_V) /* valid */ 250 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 251 | OR_UPM_XAM \ 252 | OR_GPCM_CSNT \ 253 | OR_GPCM_ACS_DIV2 \ 254 | OR_GPCM_XACS \ 255 | OR_GPCM_SCY_15 \ 256 | OR_GPCM_TRLX_SET \ 257 | OR_GPCM_EHTR_SET) 258 259 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 260 /* 127 64KB sectors and 8 8KB top sectors per device */ 261 #define CONFIG_SYS_MAX_FLASH_SECT 135 262 263 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 264 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 265 266 /* 267 * NAND Flash on the Local Bus 268 */ 269 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 270 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ 271 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 272 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 273 | BR_PS_8 /* 8 bit Port */ \ 274 | BR_MS_FCM /* MSEL = FCM */ \ 275 | BR_V) /* valid */ 276 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 277 | OR_FCM_CSCT \ 278 | OR_FCM_CST \ 279 | OR_FCM_CHT \ 280 | OR_FCM_SCY_1 \ 281 | OR_FCM_TRLX \ 282 | OR_FCM_EHTR) 283 /* 0xFFFF8396 */ 284 285 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 286 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 287 288 #ifdef CONFIG_VSC7385_ENET 289 #define CONFIG_TSEC2 290 /* VSC7385 Base address on CS2 */ 291 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 292 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 293 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 294 | BR_PS_8 /* 8-bit port */ \ 295 | BR_MS_GPCM /* MSEL = GPCM */ \ 296 | BR_V) /* valid */ 297 /* 0xF0000801 */ 298 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 299 | OR_GPCM_CSNT \ 300 | OR_GPCM_XACS \ 301 | OR_GPCM_SCY_15 \ 302 | OR_GPCM_SETA \ 303 | OR_GPCM_TRLX_SET \ 304 | OR_GPCM_EHTR_SET) 305 /* 0xFFFE09FF */ 306 /* Access window base at VSC7385 base */ 307 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 308 /* Access window size 128K */ 309 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 310 /* The flash address and size of the VSC7385 firmware image */ 311 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 312 #define CONFIG_VSC7385_IMAGE_SIZE 8192 313 #endif 314 /* 315 * Serial Port 316 */ 317 #define CONFIG_CONS_INDEX 1 318 #define CONFIG_SYS_NS16550 319 #define CONFIG_SYS_NS16550_SERIAL 320 #define CONFIG_SYS_NS16550_REG_SIZE 1 321 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 322 323 #define CONFIG_SYS_BAUDRATE_TABLE \ 324 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 325 326 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 327 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 328 329 /* Use the HUSH parser */ 330 #define CONFIG_SYS_HUSH_PARSER 331 332 /* Pass open firmware flat tree */ 333 #define CONFIG_OF_LIBFDT 1 334 #define CONFIG_OF_BOARD_SETUP 1 335 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 336 337 /* I2C */ 338 #define CONFIG_SYS_I2C 339 #define CONFIG_SYS_I2C_FSL 340 #define CONFIG_SYS_FSL_I2C_SPEED 400000 341 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 342 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 343 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 344 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 345 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 346 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 347 348 /* 349 * SPI on header J8 350 * 351 * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) 352 * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. 353 */ 354 #ifdef CONFIG_MPC8XXX_SPI 355 #define CONFIG_CMD_SPI 356 #define CONFIG_USE_SPIFLASH 357 #define CONFIG_SPI_FLASH_SPANSION 358 #define CONFIG_CMD_SF 359 #endif 360 361 /* 362 * Board info - revision and where boot from 363 */ 364 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 365 366 /* 367 * Config on-board RTC 368 */ 369 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 370 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 371 372 /* 373 * General PCI 374 * Addresses are mapped 1-1. 375 */ 376 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 377 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 378 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 379 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 380 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 381 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 382 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 383 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 384 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 385 386 /* enable PCIE clock */ 387 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 388 389 #define CONFIG_PCI 390 #define CONFIG_PCI_INDIRECT_BRIDGE 391 #define CONFIG_PCIE 392 393 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 394 395 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 396 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 397 398 /* 399 * TSEC 400 */ 401 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 402 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 403 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 404 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 405 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 406 407 /* 408 * TSEC ethernet configuration 409 */ 410 #define CONFIG_MII 1 /* MII PHY management */ 411 #define CONFIG_TSEC1_NAME "eTSEC0" 412 #define CONFIG_TSEC2_NAME "eTSEC1" 413 #define TSEC1_PHY_ADDR 2 414 #define TSEC2_PHY_ADDR 1 415 #define TSEC1_PHYIDX 0 416 #define TSEC2_PHYIDX 0 417 #define TSEC1_FLAGS TSEC_GIGABIT 418 #define TSEC2_FLAGS TSEC_GIGABIT 419 420 /* Options are: eTSEC[0-1] */ 421 #define CONFIG_ETHPRIME "eTSEC0" 422 423 /* 424 * Environment 425 */ 426 #define CONFIG_ENV_IS_IN_FLASH 1 427 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 428 CONFIG_SYS_MONITOR_LEN) 429 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 430 #define CONFIG_ENV_SIZE 0x2000 431 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 432 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 433 434 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 435 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 436 437 /* 438 * BOOTP options 439 */ 440 #define CONFIG_BOOTP_BOOTFILESIZE 441 #define CONFIG_BOOTP_BOOTPATH 442 #define CONFIG_BOOTP_GATEWAY 443 #define CONFIG_BOOTP_HOSTNAME 444 445 /* 446 * Command line configuration. 447 */ 448 #define CONFIG_CMD_DATE 449 #define CONFIG_CMD_DHCP 450 #define CONFIG_CMD_I2C 451 #define CONFIG_CMD_MII 452 #define CONFIG_CMD_PCI 453 #define CONFIG_CMD_PING 454 455 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 456 457 /* 458 * Miscellaneous configurable options 459 */ 460 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 461 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 462 463 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 464 465 /* Print Buffer Size */ 466 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 467 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 468 /* Boot Argument Buffer Size */ 469 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 470 471 /* 472 * For booting Linux, the board info and command line data 473 * have to be in the first 256 MB of memory, since this is 474 * the maximum mapped by the Linux kernel during initialization. 475 */ 476 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 477 478 /* 479 * Core HID Setup 480 */ 481 #define CONFIG_SYS_HID0_INIT 0x000000000 482 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 483 HID0_ENABLE_INSTRUCTION_CACHE | \ 484 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 485 #define CONFIG_SYS_HID2 HID2_HBE 486 487 /* 488 * MMU Setup 489 */ 490 491 /* DDR: cache cacheable */ 492 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 493 BATL_MEMCOHERENCE) 494 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 495 BATU_VS | BATU_VP) 496 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 497 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 498 499 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 500 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 501 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 502 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 503 BATU_VP) 504 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 505 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 506 507 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 508 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 509 BATL_MEMCOHERENCE) 510 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 511 BATU_VS | BATU_VP) 512 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 513 BATL_CACHEINHIBIT | \ 514 BATL_GUARDEDSTORAGE) 515 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 516 517 /* Stack in dcache: cacheable, no memory coherence */ 518 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 519 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 520 BATU_VS | BATU_VP) 521 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 522 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 523 524 /* 525 * Environment Configuration 526 */ 527 528 #define CONFIG_ENV_OVERWRITE 529 530 #if defined(CONFIG_TSEC_ENET) 531 #define CONFIG_HAS_ETH0 532 #define CONFIG_HAS_ETH1 533 #endif 534 535 #define CONFIG_BAUDRATE 115200 536 537 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 538 539 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 540 541 #define CONFIG_EXTRA_ENV_SETTINGS \ 542 "netdev=eth0\0" \ 543 "consoledev=ttyS0\0" \ 544 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 545 "nfsroot=${serverip}:${rootpath}\0" \ 546 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 547 "addip=setenv bootargs ${bootargs} " \ 548 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 549 ":${hostname}:${netdev}:off panic=1\0" \ 550 "addtty=setenv bootargs ${bootargs}" \ 551 " console=${consoledev},${baudrate}\0" \ 552 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 553 "addmisc=setenv bootargs ${bootargs}\0" \ 554 "kernel_addr=FE080000\0" \ 555 "fdt_addr=FE280000\0" \ 556 "ramdisk_addr=FE290000\0" \ 557 "u-boot=mpc8308rdb/u-boot.bin\0" \ 558 "kernel_addr_r=1000000\0" \ 559 "fdt_addr_r=C00000\0" \ 560 "hostname=mpc8308rdb\0" \ 561 "bootfile=mpc8308rdb/uImage\0" \ 562 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ 563 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 564 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 565 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 566 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 567 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 568 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 569 "tftp ${fdt_addr_r} ${fdtfile};" \ 570 "run nfsargs addip addtty addmtd addmisc;" \ 571 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 572 "bootcmd=run flash_self\0" \ 573 "load=tftp ${loadaddr} ${u-boot}\0" \ 574 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 575 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 576 " +${filesize};cp.b ${fileaddr} " \ 577 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 578 "upd=run load update\0" \ 579 580 #endif /* __CONFIG_H */ 581