1 /* 2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19 #define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 23 #define CONFIG_MISC_INIT_R 24 25 /* new uImage format support */ 26 #define CONFIG_FIT 1 27 #define CONFIG_FIT_VERBOSE 1 28 29 #define CONFIG_MMC 1 30 31 #ifdef CONFIG_MMC 32 #define CONFIG_FSL_ESDHC 33 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 34 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 35 #define CONFIG_SYS_FSL_ESDHC_USE_PIO 36 37 #define CONFIG_CMD_MMC 38 #define CONFIG_GENERIC_MMC 39 #define CONFIG_CMD_FAT 40 #define CONFIG_DOS_PARTITION 41 #endif 42 43 /* 44 * On-board devices 45 * 46 * TSEC1 is SoC TSEC 47 * TSEC2 is VSC switch 48 */ 49 #define CONFIG_TSEC1 50 #define CONFIG_VSC7385_ENET 51 52 /* 53 * System Clock Setup 54 */ 55 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 56 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 57 58 /* 59 * Hardware Reset Configuration Word 60 * if CLKIN is 66.66MHz, then 61 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 62 * We choose the A type silicon as default, so the core is 400Mhz. 63 */ 64 #define CONFIG_SYS_HRCW_LOW (\ 65 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 66 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 67 HRCWL_SVCOD_DIV_2 |\ 68 HRCWL_CSB_TO_CLKIN_4X1 |\ 69 HRCWL_CORE_TO_CSB_3X1) 70 /* 71 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 72 * in 8308's HRCWH according to the manual, but original Freescale's 73 * code has them and I've expirienced some problems using the board 74 * with BDI3000 attached when I've tried to set these bits to zero 75 * (UART doesn't work after the 'reset run' command). 76 */ 77 #define CONFIG_SYS_HRCW_HIGH (\ 78 HRCWH_PCI_HOST |\ 79 HRCWH_PCI1_ARBITER_ENABLE |\ 80 HRCWH_CORE_ENABLE |\ 81 HRCWH_FROM_0X00000100 |\ 82 HRCWH_BOOTSEQ_DISABLE |\ 83 HRCWH_SW_WATCHDOG_DISABLE |\ 84 HRCWH_ROM_LOC_LOCAL_16BIT |\ 85 HRCWH_RL_EXT_LEGACY |\ 86 HRCWH_TSEC1M_IN_RGMII |\ 87 HRCWH_TSEC2M_IN_RGMII |\ 88 HRCWH_BIG_ENDIAN) 89 90 /* 91 * System IO Config 92 */ 93 #define CONFIG_SYS_SICRH (\ 94 SICRH_ESDHC_A_SD |\ 95 SICRH_ESDHC_B_SD |\ 96 SICRH_ESDHC_C_SD |\ 97 SICRH_GPIO_A_TSEC2 |\ 98 SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ 99 SICRH_IEEE1588_A_GPIO |\ 100 SICRH_USB |\ 101 SICRH_GTM_GPIO |\ 102 SICRH_IEEE1588_B_GPIO |\ 103 SICRH_ETSEC2_CRS |\ 104 SICRH_GPIOSEL_1 |\ 105 SICRH_TMROBI_V3P3 |\ 106 SICRH_TSOBI1_V2P5 |\ 107 SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ 108 #define CONFIG_SYS_SICRL (\ 109 SICRL_SPI_PF0 |\ 110 SICRL_UART_PF0 |\ 111 SICRL_IRQ_PF0 |\ 112 SICRL_I2C2_PF0 |\ 113 SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ 114 115 /* 116 * IMMR new address 117 */ 118 #define CONFIG_SYS_IMMR 0xE0000000 119 120 /* 121 * SERDES 122 */ 123 #define CONFIG_FSL_SERDES 124 #define CONFIG_FSL_SERDES1 0xe3000 125 126 /* 127 * Arbiter Setup 128 */ 129 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 130 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 131 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 132 133 /* 134 * DDR Setup 135 */ 136 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 137 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 138 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 139 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 140 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 141 | DDRCDR_PZ_LOZ \ 142 | DDRCDR_NZ_LOZ \ 143 | DDRCDR_ODT \ 144 | DDRCDR_Q_DRN) 145 /* 0x7b880001 */ 146 /* 147 * Manually set up DDR parameters 148 * consist of two chips HY5PS12621BFP-C4 from HYNIX 149 */ 150 151 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 152 153 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 154 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 155 | CSCONFIG_ODT_RD_NEVER \ 156 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 157 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 158 /* 0x80010102 */ 159 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 160 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 161 | (0 << TIMING_CFG0_WRT_SHIFT) \ 162 | (0 << TIMING_CFG0_RRT_SHIFT) \ 163 | (0 << TIMING_CFG0_WWT_SHIFT) \ 164 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 165 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 166 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 167 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 168 /* 0x00220802 */ 169 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 170 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 171 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 172 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 173 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 174 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 175 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 176 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 177 /* 0x27256222 */ 178 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 179 | (4 << TIMING_CFG2_CPO_SHIFT) \ 180 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 181 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 182 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 183 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 184 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 185 /* 0x121048c5 */ 186 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 187 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 188 /* 0x03600100 */ 189 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 190 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 191 | SDRAM_CFG_DBW_32) 192 /* 0x43080000 */ 193 194 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 195 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 196 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 197 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 198 #define CONFIG_SYS_DDR_MODE2 0x00000000 199 200 /* 201 * Memory test 202 */ 203 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 204 #define CONFIG_SYS_MEMTEST_END 0x07f00000 205 206 /* 207 * The reserved memory 208 */ 209 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 210 211 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 212 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 213 214 /* 215 * Initial RAM Base Address Setup 216 */ 217 #define CONFIG_SYS_INIT_RAM_LOCK 1 218 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 219 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 220 #define CONFIG_SYS_GBL_DATA_OFFSET \ 221 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 222 223 /* 224 * Local Bus Configuration & Clock Setup 225 */ 226 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 227 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 228 #define CONFIG_SYS_LBC_LBCR 0x00040000 229 230 /* 231 * FLASH on the Local Bus 232 */ 233 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 234 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 235 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 236 237 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 238 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 239 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 240 241 /* Window base at flash base */ 242 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 243 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 244 245 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 246 | BR_PS_16 /* 16 bit port */ \ 247 | BR_MS_GPCM /* MSEL = GPCM */ \ 248 | BR_V) /* valid */ 249 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 250 | OR_UPM_XAM \ 251 | OR_GPCM_CSNT \ 252 | OR_GPCM_ACS_DIV2 \ 253 | OR_GPCM_XACS \ 254 | OR_GPCM_SCY_15 \ 255 | OR_GPCM_TRLX_SET \ 256 | OR_GPCM_EHTR_SET) 257 258 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 259 /* 127 64KB sectors and 8 8KB top sectors per device */ 260 #define CONFIG_SYS_MAX_FLASH_SECT 135 261 262 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 263 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 264 265 /* 266 * NAND Flash on the Local Bus 267 */ 268 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 269 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ 270 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 271 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 272 | BR_PS_8 /* 8 bit Port */ \ 273 | BR_MS_FCM /* MSEL = FCM */ \ 274 | BR_V) /* valid */ 275 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 276 | OR_FCM_CSCT \ 277 | OR_FCM_CST \ 278 | OR_FCM_CHT \ 279 | OR_FCM_SCY_1 \ 280 | OR_FCM_TRLX \ 281 | OR_FCM_EHTR) 282 /* 0xFFFF8396 */ 283 284 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 285 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 286 287 #ifdef CONFIG_VSC7385_ENET 288 #define CONFIG_TSEC2 289 /* VSC7385 Base address on CS2 */ 290 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 291 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 292 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 293 | BR_PS_8 /* 8-bit port */ \ 294 | BR_MS_GPCM /* MSEL = GPCM */ \ 295 | BR_V) /* valid */ 296 /* 0xF0000801 */ 297 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 298 | OR_GPCM_CSNT \ 299 | OR_GPCM_XACS \ 300 | OR_GPCM_SCY_15 \ 301 | OR_GPCM_SETA \ 302 | OR_GPCM_TRLX_SET \ 303 | OR_GPCM_EHTR_SET) 304 /* 0xFFFE09FF */ 305 /* Access window base at VSC7385 base */ 306 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 307 /* Access window size 128K */ 308 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 309 /* The flash address and size of the VSC7385 firmware image */ 310 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 311 #define CONFIG_VSC7385_IMAGE_SIZE 8192 312 #endif 313 /* 314 * Serial Port 315 */ 316 #define CONFIG_CONS_INDEX 1 317 #define CONFIG_SYS_NS16550 318 #define CONFIG_SYS_NS16550_SERIAL 319 #define CONFIG_SYS_NS16550_REG_SIZE 1 320 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 321 322 #define CONFIG_SYS_BAUDRATE_TABLE \ 323 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 324 325 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 326 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 327 328 /* Use the HUSH parser */ 329 #define CONFIG_SYS_HUSH_PARSER 330 331 /* Pass open firmware flat tree */ 332 #define CONFIG_OF_LIBFDT 1 333 #define CONFIG_OF_BOARD_SETUP 1 334 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 335 336 /* I2C */ 337 #define CONFIG_SYS_I2C 338 #define CONFIG_SYS_I2C_FSL 339 #define CONFIG_SYS_FSL_I2C_SPEED 400000 340 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 341 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 342 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 343 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 344 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 345 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 346 347 /* 348 * SPI on header J8 349 * 350 * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) 351 * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. 352 */ 353 #ifdef CONFIG_MPC8XXX_SPI 354 #define CONFIG_CMD_SPI 355 #define CONFIG_USE_SPIFLASH 356 #define CONFIG_SPI_FLASH 357 #define CONFIG_SPI_FLASH_SPANSION 358 #define CONFIG_CMD_SF 359 #endif 360 361 /* 362 * Board info - revision and where boot from 363 */ 364 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 365 366 /* 367 * Config on-board RTC 368 */ 369 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 370 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 371 372 /* 373 * General PCI 374 * Addresses are mapped 1-1. 375 */ 376 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 377 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 378 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 379 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 380 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 381 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 382 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 383 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 384 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 385 386 /* enable PCIE clock */ 387 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 388 389 #define CONFIG_PCI 390 #define CONFIG_PCI_INDIRECT_BRIDGE 391 #define CONFIG_PCIE 392 393 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 394 395 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 396 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 397 398 /* 399 * TSEC 400 */ 401 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 402 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 403 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 404 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 405 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 406 407 /* 408 * TSEC ethernet configuration 409 */ 410 #define CONFIG_MII 1 /* MII PHY management */ 411 #define CONFIG_TSEC1_NAME "eTSEC0" 412 #define CONFIG_TSEC2_NAME "eTSEC1" 413 #define TSEC1_PHY_ADDR 2 414 #define TSEC2_PHY_ADDR 1 415 #define TSEC1_PHYIDX 0 416 #define TSEC2_PHYIDX 0 417 #define TSEC1_FLAGS TSEC_GIGABIT 418 #define TSEC2_FLAGS TSEC_GIGABIT 419 420 /* Options are: eTSEC[0-1] */ 421 #define CONFIG_ETHPRIME "eTSEC0" 422 423 /* 424 * Environment 425 */ 426 #define CONFIG_ENV_IS_IN_FLASH 1 427 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 428 CONFIG_SYS_MONITOR_LEN) 429 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 430 #define CONFIG_ENV_SIZE 0x2000 431 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 432 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 433 434 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 435 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 436 437 /* 438 * BOOTP options 439 */ 440 #define CONFIG_BOOTP_BOOTFILESIZE 441 #define CONFIG_BOOTP_BOOTPATH 442 #define CONFIG_BOOTP_GATEWAY 443 #define CONFIG_BOOTP_HOSTNAME 444 445 /* 446 * Command line configuration. 447 */ 448 #include <config_cmd_default.h> 449 450 #define CONFIG_CMD_DATE 451 #define CONFIG_CMD_DHCP 452 #define CONFIG_CMD_I2C 453 #define CONFIG_CMD_MII 454 #define CONFIG_CMD_NET 455 #define CONFIG_CMD_PCI 456 #define CONFIG_CMD_PING 457 458 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 459 460 /* 461 * Miscellaneous configurable options 462 */ 463 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 464 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 465 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 466 467 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 468 469 /* Print Buffer Size */ 470 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 471 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 472 /* Boot Argument Buffer Size */ 473 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 474 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 475 476 /* 477 * For booting Linux, the board info and command line data 478 * have to be in the first 256 MB of memory, since this is 479 * the maximum mapped by the Linux kernel during initialization. 480 */ 481 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 482 483 /* 484 * Core HID Setup 485 */ 486 #define CONFIG_SYS_HID0_INIT 0x000000000 487 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 488 HID0_ENABLE_INSTRUCTION_CACHE | \ 489 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 490 #define CONFIG_SYS_HID2 HID2_HBE 491 492 /* 493 * MMU Setup 494 */ 495 496 /* DDR: cache cacheable */ 497 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 498 BATL_MEMCOHERENCE) 499 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 500 BATU_VS | BATU_VP) 501 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 502 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 503 504 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 505 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 506 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 507 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 508 BATU_VP) 509 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 510 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 511 512 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 513 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 514 BATL_MEMCOHERENCE) 515 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 516 BATU_VS | BATU_VP) 517 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 518 BATL_CACHEINHIBIT | \ 519 BATL_GUARDEDSTORAGE) 520 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 521 522 /* Stack in dcache: cacheable, no memory coherence */ 523 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 524 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 525 BATU_VS | BATU_VP) 526 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 527 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 528 529 /* 530 * Environment Configuration 531 */ 532 533 #define CONFIG_ENV_OVERWRITE 534 535 #if defined(CONFIG_TSEC_ENET) 536 #define CONFIG_HAS_ETH0 537 #define CONFIG_HAS_ETH1 538 #endif 539 540 #define CONFIG_BAUDRATE 115200 541 542 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 543 544 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 545 546 #define CONFIG_EXTRA_ENV_SETTINGS \ 547 "netdev=eth0\0" \ 548 "consoledev=ttyS0\0" \ 549 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 550 "nfsroot=${serverip}:${rootpath}\0" \ 551 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 552 "addip=setenv bootargs ${bootargs} " \ 553 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 554 ":${hostname}:${netdev}:off panic=1\0" \ 555 "addtty=setenv bootargs ${bootargs}" \ 556 " console=${consoledev},${baudrate}\0" \ 557 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 558 "addmisc=setenv bootargs ${bootargs}\0" \ 559 "kernel_addr=FE080000\0" \ 560 "fdt_addr=FE280000\0" \ 561 "ramdisk_addr=FE290000\0" \ 562 "u-boot=mpc8308rdb/u-boot.bin\0" \ 563 "kernel_addr_r=1000000\0" \ 564 "fdt_addr_r=C00000\0" \ 565 "hostname=mpc8308rdb\0" \ 566 "bootfile=mpc8308rdb/uImage\0" \ 567 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ 568 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 569 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 570 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 571 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 572 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 573 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 574 "tftp ${fdt_addr_r} ${fdtfile};" \ 575 "run nfsargs addip addtty addmtd addmisc;" \ 576 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 577 "bootcmd=run flash_self\0" \ 578 "load=tftp ${loadaddr} ${u-boot}\0" \ 579 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 580 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 581 " +${filesize};cp.b ${fileaddr} " \ 582 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 583 "upd=run load update\0" \ 584 585 #endif /* __CONFIG_H */ 586