1 /* 2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_SYS_GENERIC_BOARD 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 /* 16 * High Level Configuration Options 17 */ 18 #define CONFIG_E300 1 /* E300 family */ 19 #define CONFIG_MPC830x 1 /* MPC830x family */ 20 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 21 #define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ 22 23 #define CONFIG_SYS_TEXT_BASE 0xFE000000 24 25 #define CONFIG_MISC_INIT_R 26 27 /* new uImage format support */ 28 #define CONFIG_FIT 1 29 #define CONFIG_FIT_VERBOSE 1 30 31 #define CONFIG_MMC 1 32 33 #ifdef CONFIG_MMC 34 #define CONFIG_FSL_ESDHC 35 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 36 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 37 #define CONFIG_SYS_FSL_ESDHC_USE_PIO 38 39 #define CONFIG_CMD_MMC 40 #define CONFIG_GENERIC_MMC 41 #define CONFIG_CMD_FAT 42 #define CONFIG_DOS_PARTITION 43 #endif 44 45 /* 46 * On-board devices 47 * 48 * TSEC1 is SoC TSEC 49 * TSEC2 is VSC switch 50 */ 51 #define CONFIG_TSEC1 52 #define CONFIG_VSC7385_ENET 53 54 /* 55 * System Clock Setup 56 */ 57 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 58 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 59 60 /* 61 * Hardware Reset Configuration Word 62 * if CLKIN is 66.66MHz, then 63 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 64 * We choose the A type silicon as default, so the core is 400Mhz. 65 */ 66 #define CONFIG_SYS_HRCW_LOW (\ 67 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 68 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 69 HRCWL_SVCOD_DIV_2 |\ 70 HRCWL_CSB_TO_CLKIN_4X1 |\ 71 HRCWL_CORE_TO_CSB_3X1) 72 /* 73 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 74 * in 8308's HRCWH according to the manual, but original Freescale's 75 * code has them and I've expirienced some problems using the board 76 * with BDI3000 attached when I've tried to set these bits to zero 77 * (UART doesn't work after the 'reset run' command). 78 */ 79 #define CONFIG_SYS_HRCW_HIGH (\ 80 HRCWH_PCI_HOST |\ 81 HRCWH_PCI1_ARBITER_ENABLE |\ 82 HRCWH_CORE_ENABLE |\ 83 HRCWH_FROM_0X00000100 |\ 84 HRCWH_BOOTSEQ_DISABLE |\ 85 HRCWH_SW_WATCHDOG_DISABLE |\ 86 HRCWH_ROM_LOC_LOCAL_16BIT |\ 87 HRCWH_RL_EXT_LEGACY |\ 88 HRCWH_TSEC1M_IN_RGMII |\ 89 HRCWH_TSEC2M_IN_RGMII |\ 90 HRCWH_BIG_ENDIAN) 91 92 /* 93 * System IO Config 94 */ 95 #define CONFIG_SYS_SICRH (\ 96 SICRH_ESDHC_A_SD |\ 97 SICRH_ESDHC_B_SD |\ 98 SICRH_ESDHC_C_SD |\ 99 SICRH_GPIO_A_TSEC2 |\ 100 SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ 101 SICRH_IEEE1588_A_GPIO |\ 102 SICRH_USB |\ 103 SICRH_GTM_GPIO |\ 104 SICRH_IEEE1588_B_GPIO |\ 105 SICRH_ETSEC2_CRS |\ 106 SICRH_GPIOSEL_1 |\ 107 SICRH_TMROBI_V3P3 |\ 108 SICRH_TSOBI1_V2P5 |\ 109 SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ 110 #define CONFIG_SYS_SICRL (\ 111 SICRL_SPI_PF0 |\ 112 SICRL_UART_PF0 |\ 113 SICRL_IRQ_PF0 |\ 114 SICRL_I2C2_PF0 |\ 115 SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ 116 117 /* 118 * IMMR new address 119 */ 120 #define CONFIG_SYS_IMMR 0xE0000000 121 122 /* 123 * SERDES 124 */ 125 #define CONFIG_FSL_SERDES 126 #define CONFIG_FSL_SERDES1 0xe3000 127 128 /* 129 * Arbiter Setup 130 */ 131 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 132 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 133 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 134 135 /* 136 * DDR Setup 137 */ 138 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 139 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 140 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 141 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 142 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 143 | DDRCDR_PZ_LOZ \ 144 | DDRCDR_NZ_LOZ \ 145 | DDRCDR_ODT \ 146 | DDRCDR_Q_DRN) 147 /* 0x7b880001 */ 148 /* 149 * Manually set up DDR parameters 150 * consist of two chips HY5PS12621BFP-C4 from HYNIX 151 */ 152 153 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 154 155 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 156 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 157 | CSCONFIG_ODT_RD_NEVER \ 158 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 159 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 160 /* 0x80010102 */ 161 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 162 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 163 | (0 << TIMING_CFG0_WRT_SHIFT) \ 164 | (0 << TIMING_CFG0_RRT_SHIFT) \ 165 | (0 << TIMING_CFG0_WWT_SHIFT) \ 166 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 167 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 168 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 169 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 170 /* 0x00220802 */ 171 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 172 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 173 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 174 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 175 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 176 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 177 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 178 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 179 /* 0x27256222 */ 180 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 181 | (4 << TIMING_CFG2_CPO_SHIFT) \ 182 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 183 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 184 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 185 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 186 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 187 /* 0x121048c5 */ 188 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 189 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 190 /* 0x03600100 */ 191 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 192 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 193 | SDRAM_CFG_DBW_32) 194 /* 0x43080000 */ 195 196 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 197 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 198 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 199 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 200 #define CONFIG_SYS_DDR_MODE2 0x00000000 201 202 /* 203 * Memory test 204 */ 205 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 206 #define CONFIG_SYS_MEMTEST_END 0x07f00000 207 208 /* 209 * The reserved memory 210 */ 211 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 212 213 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 214 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 215 216 /* 217 * Initial RAM Base Address Setup 218 */ 219 #define CONFIG_SYS_INIT_RAM_LOCK 1 220 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 221 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 222 #define CONFIG_SYS_GBL_DATA_OFFSET \ 223 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 224 225 /* 226 * Local Bus Configuration & Clock Setup 227 */ 228 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 229 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 230 #define CONFIG_SYS_LBC_LBCR 0x00040000 231 232 /* 233 * FLASH on the Local Bus 234 */ 235 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 236 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 237 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 238 239 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 240 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 241 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 242 243 /* Window base at flash base */ 244 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 245 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 246 247 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 248 | BR_PS_16 /* 16 bit port */ \ 249 | BR_MS_GPCM /* MSEL = GPCM */ \ 250 | BR_V) /* valid */ 251 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 252 | OR_UPM_XAM \ 253 | OR_GPCM_CSNT \ 254 | OR_GPCM_ACS_DIV2 \ 255 | OR_GPCM_XACS \ 256 | OR_GPCM_SCY_15 \ 257 | OR_GPCM_TRLX_SET \ 258 | OR_GPCM_EHTR_SET) 259 260 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 261 /* 127 64KB sectors and 8 8KB top sectors per device */ 262 #define CONFIG_SYS_MAX_FLASH_SECT 135 263 264 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 265 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 266 267 /* 268 * NAND Flash on the Local Bus 269 */ 270 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 271 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ 272 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 273 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 274 | BR_PS_8 /* 8 bit Port */ \ 275 | BR_MS_FCM /* MSEL = FCM */ \ 276 | BR_V) /* valid */ 277 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 278 | OR_FCM_CSCT \ 279 | OR_FCM_CST \ 280 | OR_FCM_CHT \ 281 | OR_FCM_SCY_1 \ 282 | OR_FCM_TRLX \ 283 | OR_FCM_EHTR) 284 /* 0xFFFF8396 */ 285 286 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 287 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 288 289 #ifdef CONFIG_VSC7385_ENET 290 #define CONFIG_TSEC2 291 /* VSC7385 Base address on CS2 */ 292 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 293 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 294 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 295 | BR_PS_8 /* 8-bit port */ \ 296 | BR_MS_GPCM /* MSEL = GPCM */ \ 297 | BR_V) /* valid */ 298 /* 0xF0000801 */ 299 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 300 | OR_GPCM_CSNT \ 301 | OR_GPCM_XACS \ 302 | OR_GPCM_SCY_15 \ 303 | OR_GPCM_SETA \ 304 | OR_GPCM_TRLX_SET \ 305 | OR_GPCM_EHTR_SET) 306 /* 0xFFFE09FF */ 307 /* Access window base at VSC7385 base */ 308 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 309 /* Access window size 128K */ 310 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 311 /* The flash address and size of the VSC7385 firmware image */ 312 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 313 #define CONFIG_VSC7385_IMAGE_SIZE 8192 314 #endif 315 /* 316 * Serial Port 317 */ 318 #define CONFIG_CONS_INDEX 1 319 #define CONFIG_SYS_NS16550 320 #define CONFIG_SYS_NS16550_SERIAL 321 #define CONFIG_SYS_NS16550_REG_SIZE 1 322 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 323 324 #define CONFIG_SYS_BAUDRATE_TABLE \ 325 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 326 327 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 328 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 329 330 /* Use the HUSH parser */ 331 #define CONFIG_SYS_HUSH_PARSER 332 333 /* Pass open firmware flat tree */ 334 #define CONFIG_OF_LIBFDT 1 335 #define CONFIG_OF_BOARD_SETUP 1 336 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 337 338 /* I2C */ 339 #define CONFIG_SYS_I2C 340 #define CONFIG_SYS_I2C_FSL 341 #define CONFIG_SYS_FSL_I2C_SPEED 400000 342 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 343 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 344 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 345 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 346 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 347 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 348 349 /* 350 * SPI on header J8 351 * 352 * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) 353 * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. 354 */ 355 #ifdef CONFIG_MPC8XXX_SPI 356 #define CONFIG_CMD_SPI 357 #define CONFIG_USE_SPIFLASH 358 #define CONFIG_SPI_FLASH 359 #define CONFIG_SPI_FLASH_SPANSION 360 #define CONFIG_CMD_SF 361 #endif 362 363 /* 364 * Board info - revision and where boot from 365 */ 366 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 367 368 /* 369 * Config on-board RTC 370 */ 371 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 372 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 373 374 /* 375 * General PCI 376 * Addresses are mapped 1-1. 377 */ 378 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 379 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 380 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 381 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 382 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 383 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 384 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 385 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 386 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 387 388 /* enable PCIE clock */ 389 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 390 391 #define CONFIG_PCI 392 #define CONFIG_PCI_INDIRECT_BRIDGE 393 #define CONFIG_PCIE 394 395 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 396 397 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 398 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 399 400 /* 401 * TSEC 402 */ 403 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 404 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 405 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 406 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 407 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 408 409 /* 410 * TSEC ethernet configuration 411 */ 412 #define CONFIG_MII 1 /* MII PHY management */ 413 #define CONFIG_TSEC1_NAME "eTSEC0" 414 #define CONFIG_TSEC2_NAME "eTSEC1" 415 #define TSEC1_PHY_ADDR 2 416 #define TSEC2_PHY_ADDR 1 417 #define TSEC1_PHYIDX 0 418 #define TSEC2_PHYIDX 0 419 #define TSEC1_FLAGS TSEC_GIGABIT 420 #define TSEC2_FLAGS TSEC_GIGABIT 421 422 /* Options are: eTSEC[0-1] */ 423 #define CONFIG_ETHPRIME "eTSEC0" 424 425 /* 426 * Environment 427 */ 428 #define CONFIG_ENV_IS_IN_FLASH 1 429 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 430 CONFIG_SYS_MONITOR_LEN) 431 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 432 #define CONFIG_ENV_SIZE 0x2000 433 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 434 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 435 436 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 437 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 438 439 /* 440 * BOOTP options 441 */ 442 #define CONFIG_BOOTP_BOOTFILESIZE 443 #define CONFIG_BOOTP_BOOTPATH 444 #define CONFIG_BOOTP_GATEWAY 445 #define CONFIG_BOOTP_HOSTNAME 446 447 /* 448 * Command line configuration. 449 */ 450 #include <config_cmd_default.h> 451 452 #define CONFIG_CMD_DATE 453 #define CONFIG_CMD_DHCP 454 #define CONFIG_CMD_I2C 455 #define CONFIG_CMD_MII 456 #define CONFIG_CMD_PCI 457 #define CONFIG_CMD_PING 458 459 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 460 461 /* 462 * Miscellaneous configurable options 463 */ 464 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 465 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 466 467 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 468 469 /* Print Buffer Size */ 470 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 471 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 472 /* Boot Argument Buffer Size */ 473 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 474 475 /* 476 * For booting Linux, the board info and command line data 477 * have to be in the first 256 MB of memory, since this is 478 * the maximum mapped by the Linux kernel during initialization. 479 */ 480 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 481 482 /* 483 * Core HID Setup 484 */ 485 #define CONFIG_SYS_HID0_INIT 0x000000000 486 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 487 HID0_ENABLE_INSTRUCTION_CACHE | \ 488 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 489 #define CONFIG_SYS_HID2 HID2_HBE 490 491 /* 492 * MMU Setup 493 */ 494 495 /* DDR: cache cacheable */ 496 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 497 BATL_MEMCOHERENCE) 498 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 499 BATU_VS | BATU_VP) 500 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 501 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 502 503 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 504 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 505 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 506 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 507 BATU_VP) 508 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 509 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 510 511 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 512 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 513 BATL_MEMCOHERENCE) 514 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 515 BATU_VS | BATU_VP) 516 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 517 BATL_CACHEINHIBIT | \ 518 BATL_GUARDEDSTORAGE) 519 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 520 521 /* Stack in dcache: cacheable, no memory coherence */ 522 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 523 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 524 BATU_VS | BATU_VP) 525 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 526 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 527 528 /* 529 * Environment Configuration 530 */ 531 532 #define CONFIG_ENV_OVERWRITE 533 534 #if defined(CONFIG_TSEC_ENET) 535 #define CONFIG_HAS_ETH0 536 #define CONFIG_HAS_ETH1 537 #endif 538 539 #define CONFIG_BAUDRATE 115200 540 541 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 542 543 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 544 545 #define CONFIG_EXTRA_ENV_SETTINGS \ 546 "netdev=eth0\0" \ 547 "consoledev=ttyS0\0" \ 548 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 549 "nfsroot=${serverip}:${rootpath}\0" \ 550 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 551 "addip=setenv bootargs ${bootargs} " \ 552 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 553 ":${hostname}:${netdev}:off panic=1\0" \ 554 "addtty=setenv bootargs ${bootargs}" \ 555 " console=${consoledev},${baudrate}\0" \ 556 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 557 "addmisc=setenv bootargs ${bootargs}\0" \ 558 "kernel_addr=FE080000\0" \ 559 "fdt_addr=FE280000\0" \ 560 "ramdisk_addr=FE290000\0" \ 561 "u-boot=mpc8308rdb/u-boot.bin\0" \ 562 "kernel_addr_r=1000000\0" \ 563 "fdt_addr_r=C00000\0" \ 564 "hostname=mpc8308rdb\0" \ 565 "bootfile=mpc8308rdb/uImage\0" \ 566 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ 567 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 568 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 569 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 570 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 571 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 572 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 573 "tftp ${fdt_addr_r} ${fdtfile};" \ 574 "run nfsargs addip addtty addmtd addmisc;" \ 575 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 576 "bootcmd=run flash_self\0" \ 577 "load=tftp ${loadaddr} ${u-boot}\0" \ 578 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 579 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 580 " +${filesize};cp.b ${fileaddr} " \ 581 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 582 "upd=run load update\0" \ 583 584 #endif /* __CONFIG_H */ 585