1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 5 * 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 /* 12 * High Level Configuration Options 13 */ 14 #define CONFIG_E300 1 /* E300 family */ 15 #define CONFIG_MPC830x 1 /* MPC830x family */ 16 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 17 18 #ifdef CONFIG_MMC 19 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 20 #define CONFIG_SYS_FSL_ESDHC_USE_PIO 21 #endif 22 23 /* 24 * On-board devices 25 * 26 * TSEC1 is SoC TSEC 27 * TSEC2 is VSC switch 28 */ 29 #define CONFIG_TSEC1 30 #define CONFIG_VSC7385_ENET 31 32 /* 33 * System Clock Setup 34 */ 35 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 36 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 37 38 /* 39 * Hardware Reset Configuration Word 40 * if CLKIN is 66.66MHz, then 41 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 42 * We choose the A type silicon as default, so the core is 400Mhz. 43 */ 44 #define CONFIG_SYS_HRCW_LOW (\ 45 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 46 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 47 HRCWL_SVCOD_DIV_2 |\ 48 HRCWL_CSB_TO_CLKIN_4X1 |\ 49 HRCWL_CORE_TO_CSB_3X1) 50 /* 51 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 52 * in 8308's HRCWH according to the manual, but original Freescale's 53 * code has them and I've expirienced some problems using the board 54 * with BDI3000 attached when I've tried to set these bits to zero 55 * (UART doesn't work after the 'reset run' command). 56 */ 57 #define CONFIG_SYS_HRCW_HIGH (\ 58 HRCWH_PCI_HOST |\ 59 HRCWH_PCI1_ARBITER_ENABLE |\ 60 HRCWH_CORE_ENABLE |\ 61 HRCWH_FROM_0X00000100 |\ 62 HRCWH_BOOTSEQ_DISABLE |\ 63 HRCWH_SW_WATCHDOG_DISABLE |\ 64 HRCWH_ROM_LOC_LOCAL_16BIT |\ 65 HRCWH_RL_EXT_LEGACY |\ 66 HRCWH_TSEC1M_IN_RGMII |\ 67 HRCWH_TSEC2M_IN_RGMII |\ 68 HRCWH_BIG_ENDIAN) 69 70 /* 71 * System IO Config 72 */ 73 #define CONFIG_SYS_SICRH (\ 74 SICRH_ESDHC_A_SD |\ 75 SICRH_ESDHC_B_SD |\ 76 SICRH_ESDHC_C_SD |\ 77 SICRH_GPIO_A_TSEC2 |\ 78 SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ 79 SICRH_IEEE1588_A_GPIO |\ 80 SICRH_USB |\ 81 SICRH_GTM_GPIO |\ 82 SICRH_IEEE1588_B_GPIO |\ 83 SICRH_ETSEC2_CRS |\ 84 SICRH_GPIOSEL_1 |\ 85 SICRH_TMROBI_V3P3 |\ 86 SICRH_TSOBI1_V2P5 |\ 87 SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ 88 #define CONFIG_SYS_SICRL (\ 89 SICRL_SPI_PF0 |\ 90 SICRL_UART_PF0 |\ 91 SICRL_IRQ_PF0 |\ 92 SICRL_I2C2_PF0 |\ 93 SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ 94 95 /* 96 * IMMR new address 97 */ 98 #define CONFIG_SYS_IMMR 0xE0000000 99 100 /* 101 * SERDES 102 */ 103 #define CONFIG_FSL_SERDES 104 #define CONFIG_FSL_SERDES1 0xe3000 105 106 /* 107 * Arbiter Setup 108 */ 109 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 110 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 111 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 112 113 /* 114 * DDR Setup 115 */ 116 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 117 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 118 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 119 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 120 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 121 | DDRCDR_PZ_LOZ \ 122 | DDRCDR_NZ_LOZ \ 123 | DDRCDR_ODT \ 124 | DDRCDR_Q_DRN) 125 /* 0x7b880001 */ 126 /* 127 * Manually set up DDR parameters 128 * consist of two chips HY5PS12621BFP-C4 from HYNIX 129 */ 130 131 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 132 133 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 134 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 135 | CSCONFIG_ODT_RD_NEVER \ 136 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 137 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 138 /* 0x80010102 */ 139 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 140 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 141 | (0 << TIMING_CFG0_WRT_SHIFT) \ 142 | (0 << TIMING_CFG0_RRT_SHIFT) \ 143 | (0 << TIMING_CFG0_WWT_SHIFT) \ 144 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 145 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 146 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 147 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 148 /* 0x00220802 */ 149 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 150 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 151 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 152 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 153 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 154 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 155 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 156 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 157 /* 0x27256222 */ 158 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 159 | (4 << TIMING_CFG2_CPO_SHIFT) \ 160 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 161 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 162 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 163 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 164 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 165 /* 0x121048c5 */ 166 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 167 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 168 /* 0x03600100 */ 169 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 170 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 171 | SDRAM_CFG_DBW_32) 172 /* 0x43080000 */ 173 174 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 175 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 176 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 177 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 178 #define CONFIG_SYS_DDR_MODE2 0x00000000 179 180 /* 181 * Memory test 182 */ 183 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 184 #define CONFIG_SYS_MEMTEST_END 0x07f00000 185 186 /* 187 * The reserved memory 188 */ 189 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 190 191 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 192 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 193 194 /* 195 * Initial RAM Base Address Setup 196 */ 197 #define CONFIG_SYS_INIT_RAM_LOCK 1 198 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 199 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 200 #define CONFIG_SYS_GBL_DATA_OFFSET \ 201 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 202 203 /* 204 * Local Bus Configuration & Clock Setup 205 */ 206 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 207 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 208 #define CONFIG_SYS_LBC_LBCR 0x00040000 209 210 /* 211 * FLASH on the Local Bus 212 */ 213 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 214 215 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 216 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 217 218 /* Window base at flash base */ 219 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 220 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 221 222 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 223 | BR_PS_16 /* 16 bit port */ \ 224 | BR_MS_GPCM /* MSEL = GPCM */ \ 225 | BR_V) /* valid */ 226 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 227 | OR_UPM_XAM \ 228 | OR_GPCM_CSNT \ 229 | OR_GPCM_ACS_DIV2 \ 230 | OR_GPCM_XACS \ 231 | OR_GPCM_SCY_15 \ 232 | OR_GPCM_TRLX_SET \ 233 | OR_GPCM_EHTR_SET) 234 235 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 236 /* 127 64KB sectors and 8 8KB top sectors per device */ 237 #define CONFIG_SYS_MAX_FLASH_SECT 135 238 239 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 240 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 241 242 /* 243 * NAND Flash on the Local Bus 244 */ 245 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 246 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ 247 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 248 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 249 | BR_PS_8 /* 8 bit Port */ \ 250 | BR_MS_FCM /* MSEL = FCM */ \ 251 | BR_V) /* valid */ 252 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 253 | OR_FCM_CSCT \ 254 | OR_FCM_CST \ 255 | OR_FCM_CHT \ 256 | OR_FCM_SCY_1 \ 257 | OR_FCM_TRLX \ 258 | OR_FCM_EHTR) 259 /* 0xFFFF8396 */ 260 261 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 262 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 263 264 #ifdef CONFIG_VSC7385_ENET 265 #define CONFIG_TSEC2 266 /* VSC7385 Base address on CS2 */ 267 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 268 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 269 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 270 | BR_PS_8 /* 8-bit port */ \ 271 | BR_MS_GPCM /* MSEL = GPCM */ \ 272 | BR_V) /* valid */ 273 /* 0xF0000801 */ 274 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 275 | OR_GPCM_CSNT \ 276 | OR_GPCM_XACS \ 277 | OR_GPCM_SCY_15 \ 278 | OR_GPCM_SETA \ 279 | OR_GPCM_TRLX_SET \ 280 | OR_GPCM_EHTR_SET) 281 /* 0xFFFE09FF */ 282 /* Access window base at VSC7385 base */ 283 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 284 /* Access window size 128K */ 285 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 286 /* The flash address and size of the VSC7385 firmware image */ 287 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 288 #define CONFIG_VSC7385_IMAGE_SIZE 8192 289 #endif 290 /* 291 * Serial Port 292 */ 293 #define CONFIG_SYS_NS16550_SERIAL 294 #define CONFIG_SYS_NS16550_REG_SIZE 1 295 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 296 297 #define CONFIG_SYS_BAUDRATE_TABLE \ 298 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 299 300 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 301 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 302 303 /* I2C */ 304 #define CONFIG_SYS_I2C 305 #define CONFIG_SYS_I2C_FSL 306 #define CONFIG_SYS_FSL_I2C_SPEED 400000 307 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 308 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 309 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 310 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 311 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 312 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 313 314 /* 315 * SPI on header J8 316 * 317 * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) 318 * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. 319 */ 320 #ifdef CONFIG_MPC8XXX_SPI 321 #define CONFIG_USE_SPIFLASH 322 #endif 323 324 /* 325 * Board info - revision and where boot from 326 */ 327 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 328 329 /* 330 * Config on-board RTC 331 */ 332 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 333 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 334 335 /* 336 * General PCI 337 * Addresses are mapped 1-1. 338 */ 339 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 340 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 341 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 342 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 343 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 344 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 345 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 346 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 347 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 348 349 /* enable PCIE clock */ 350 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 351 352 #define CONFIG_PCI_INDIRECT_BRIDGE 353 #define CONFIG_PCIE 354 355 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 356 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 357 358 /* 359 * TSEC 360 */ 361 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 362 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 363 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 364 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 365 366 /* 367 * TSEC ethernet configuration 368 */ 369 #define CONFIG_TSEC1_NAME "eTSEC0" 370 #define CONFIG_TSEC2_NAME "eTSEC1" 371 #define TSEC1_PHY_ADDR 2 372 #define TSEC2_PHY_ADDR 1 373 #define TSEC1_PHYIDX 0 374 #define TSEC2_PHYIDX 0 375 #define TSEC1_FLAGS TSEC_GIGABIT 376 #define TSEC2_FLAGS TSEC_GIGABIT 377 378 /* Options are: eTSEC[0-1] */ 379 #define CONFIG_ETHPRIME "eTSEC0" 380 381 /* 382 * Environment 383 */ 384 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 385 CONFIG_SYS_MONITOR_LEN) 386 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 387 #define CONFIG_ENV_SIZE 0x2000 388 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 389 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 390 391 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 392 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 393 394 /* 395 * BOOTP options 396 */ 397 #define CONFIG_BOOTP_BOOTFILESIZE 398 399 /* 400 * Command line configuration. 401 */ 402 403 /* 404 * Miscellaneous configurable options 405 */ 406 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 407 408 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 409 410 /* Boot Argument Buffer Size */ 411 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 412 413 /* 414 * For booting Linux, the board info and command line data 415 * have to be in the first 256 MB of memory, since this is 416 * the maximum mapped by the Linux kernel during initialization. 417 */ 418 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 419 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 420 421 /* 422 * Core HID Setup 423 */ 424 #define CONFIG_SYS_HID0_INIT 0x000000000 425 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 426 HID0_ENABLE_INSTRUCTION_CACHE | \ 427 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 428 #define CONFIG_SYS_HID2 HID2_HBE 429 430 /* 431 * MMU Setup 432 */ 433 434 /* DDR: cache cacheable */ 435 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 436 BATL_MEMCOHERENCE) 437 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 438 BATU_VS | BATU_VP) 439 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 440 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 441 442 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 443 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 444 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 445 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 446 BATU_VP) 447 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 448 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 449 450 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 451 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 452 BATL_MEMCOHERENCE) 453 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 454 BATU_VS | BATU_VP) 455 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 456 BATL_CACHEINHIBIT | \ 457 BATL_GUARDEDSTORAGE) 458 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 459 460 /* Stack in dcache: cacheable, no memory coherence */ 461 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 462 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 463 BATU_VS | BATU_VP) 464 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 465 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 466 467 /* 468 * Environment Configuration 469 */ 470 471 #define CONFIG_ENV_OVERWRITE 472 473 #if defined(CONFIG_TSEC_ENET) 474 #define CONFIG_HAS_ETH0 475 #define CONFIG_HAS_ETH1 476 #endif 477 478 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 479 480 481 #define CONFIG_EXTRA_ENV_SETTINGS \ 482 "netdev=eth0\0" \ 483 "consoledev=ttyS0\0" \ 484 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 485 "nfsroot=${serverip}:${rootpath}\0" \ 486 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 487 "addip=setenv bootargs ${bootargs} " \ 488 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 489 ":${hostname}:${netdev}:off panic=1\0" \ 490 "addtty=setenv bootargs ${bootargs}" \ 491 " console=${consoledev},${baudrate}\0" \ 492 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 493 "addmisc=setenv bootargs ${bootargs}\0" \ 494 "kernel_addr=FE080000\0" \ 495 "fdt_addr=FE280000\0" \ 496 "ramdisk_addr=FE290000\0" \ 497 "u-boot=mpc8308rdb/u-boot.bin\0" \ 498 "kernel_addr_r=1000000\0" \ 499 "fdt_addr_r=C00000\0" \ 500 "hostname=mpc8308rdb\0" \ 501 "bootfile=mpc8308rdb/uImage\0" \ 502 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ 503 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 504 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 505 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 506 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 507 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 508 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 509 "tftp ${fdt_addr_r} ${fdtfile};" \ 510 "run nfsargs addip addtty addmtd addmisc;" \ 511 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 512 "bootcmd=run flash_self\0" \ 513 "load=tftp ${loadaddr} ${u-boot}\0" \ 514 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 515 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 516 " +${filesize};cp.b ${fileaddr} " \ 517 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 518 "upd=run load update\0" \ 519 520 #endif /* __CONFIG_H */ 521