1 /* 2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC830x 1 /* MPC830x family */ 17 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 18 #define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ 19 20 #define CONFIG_SYS_TEXT_BASE 0xFE000000 21 22 #define CONFIG_MISC_INIT_R 23 24 /* new uImage format support */ 25 #define CONFIG_FIT 1 26 #define CONFIG_FIT_VERBOSE 1 27 28 #define CONFIG_MMC 1 29 30 #ifdef CONFIG_MMC 31 #define CONFIG_FSL_ESDHC 32 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 33 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 34 #define CONFIG_SYS_FSL_ESDHC_USE_PIO 35 36 #define CONFIG_CMD_MMC 37 #define CONFIG_GENERIC_MMC 38 #define CONFIG_CMD_FAT 39 #define CONFIG_DOS_PARTITION 40 #endif 41 42 /* 43 * On-board devices 44 * 45 * TSEC1 is SoC TSEC 46 * TSEC2 is VSC switch 47 */ 48 #define CONFIG_TSEC1 49 #define CONFIG_VSC7385_ENET 50 51 /* 52 * System Clock Setup 53 */ 54 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 55 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 56 57 /* 58 * Hardware Reset Configuration Word 59 * if CLKIN is 66.66MHz, then 60 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 61 * We choose the A type silicon as default, so the core is 400Mhz. 62 */ 63 #define CONFIG_SYS_HRCW_LOW (\ 64 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 65 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 66 HRCWL_SVCOD_DIV_2 |\ 67 HRCWL_CSB_TO_CLKIN_4X1 |\ 68 HRCWL_CORE_TO_CSB_3X1) 69 /* 70 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 71 * in 8308's HRCWH according to the manual, but original Freescale's 72 * code has them and I've expirienced some problems using the board 73 * with BDI3000 attached when I've tried to set these bits to zero 74 * (UART doesn't work after the 'reset run' command). 75 */ 76 #define CONFIG_SYS_HRCW_HIGH (\ 77 HRCWH_PCI_HOST |\ 78 HRCWH_PCI1_ARBITER_ENABLE |\ 79 HRCWH_CORE_ENABLE |\ 80 HRCWH_FROM_0X00000100 |\ 81 HRCWH_BOOTSEQ_DISABLE |\ 82 HRCWH_SW_WATCHDOG_DISABLE |\ 83 HRCWH_ROM_LOC_LOCAL_16BIT |\ 84 HRCWH_RL_EXT_LEGACY |\ 85 HRCWH_TSEC1M_IN_RGMII |\ 86 HRCWH_TSEC2M_IN_RGMII |\ 87 HRCWH_BIG_ENDIAN) 88 89 /* 90 * System IO Config 91 */ 92 #define CONFIG_SYS_SICRH (\ 93 SICRH_ESDHC_A_SD |\ 94 SICRH_ESDHC_B_SD |\ 95 SICRH_ESDHC_C_SD |\ 96 SICRH_GPIO_A_TSEC2 |\ 97 SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ 98 SICRH_IEEE1588_A_GPIO |\ 99 SICRH_USB |\ 100 SICRH_GTM_GPIO |\ 101 SICRH_IEEE1588_B_GPIO |\ 102 SICRH_ETSEC2_CRS |\ 103 SICRH_GPIOSEL_1 |\ 104 SICRH_TMROBI_V3P3 |\ 105 SICRH_TSOBI1_V2P5 |\ 106 SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ 107 #define CONFIG_SYS_SICRL (\ 108 SICRL_SPI_PF0 |\ 109 SICRL_UART_PF0 |\ 110 SICRL_IRQ_PF0 |\ 111 SICRL_I2C2_PF0 |\ 112 SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ 113 114 /* 115 * IMMR new address 116 */ 117 #define CONFIG_SYS_IMMR 0xE0000000 118 119 /* 120 * SERDES 121 */ 122 #define CONFIG_FSL_SERDES 123 #define CONFIG_FSL_SERDES1 0xe3000 124 125 /* 126 * Arbiter Setup 127 */ 128 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 129 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 130 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 131 132 /* 133 * DDR Setup 134 */ 135 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 136 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 137 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 138 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 139 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 140 | DDRCDR_PZ_LOZ \ 141 | DDRCDR_NZ_LOZ \ 142 | DDRCDR_ODT \ 143 | DDRCDR_Q_DRN) 144 /* 0x7b880001 */ 145 /* 146 * Manually set up DDR parameters 147 * consist of two chips HY5PS12621BFP-C4 from HYNIX 148 */ 149 150 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 151 152 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 153 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 154 | CSCONFIG_ODT_RD_NEVER \ 155 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 156 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 157 /* 0x80010102 */ 158 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 159 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 160 | (0 << TIMING_CFG0_WRT_SHIFT) \ 161 | (0 << TIMING_CFG0_RRT_SHIFT) \ 162 | (0 << TIMING_CFG0_WWT_SHIFT) \ 163 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 164 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 165 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 166 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 167 /* 0x00220802 */ 168 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 169 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 170 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 171 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 172 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 173 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 174 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 175 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 176 /* 0x27256222 */ 177 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 178 | (4 << TIMING_CFG2_CPO_SHIFT) \ 179 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 180 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 181 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 182 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 183 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 184 /* 0x121048c5 */ 185 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 186 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 187 /* 0x03600100 */ 188 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 189 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 190 | SDRAM_CFG_DBW_32) 191 /* 0x43080000 */ 192 193 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 194 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 195 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 196 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 197 #define CONFIG_SYS_DDR_MODE2 0x00000000 198 199 /* 200 * Memory test 201 */ 202 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 203 #define CONFIG_SYS_MEMTEST_END 0x07f00000 204 205 /* 206 * The reserved memory 207 */ 208 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 209 210 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 211 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 212 213 /* 214 * Initial RAM Base Address Setup 215 */ 216 #define CONFIG_SYS_INIT_RAM_LOCK 1 217 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 218 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 219 #define CONFIG_SYS_GBL_DATA_OFFSET \ 220 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 221 222 /* 223 * Local Bus Configuration & Clock Setup 224 */ 225 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 226 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 227 #define CONFIG_SYS_LBC_LBCR 0x00040000 228 229 /* 230 * FLASH on the Local Bus 231 */ 232 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 233 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 234 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 235 236 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 237 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 238 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 239 240 /* Window base at flash base */ 241 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 242 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 243 244 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 245 | BR_PS_16 /* 16 bit port */ \ 246 | BR_MS_GPCM /* MSEL = GPCM */ \ 247 | BR_V) /* valid */ 248 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 249 | OR_UPM_XAM \ 250 | OR_GPCM_CSNT \ 251 | OR_GPCM_ACS_DIV2 \ 252 | OR_GPCM_XACS \ 253 | OR_GPCM_SCY_15 \ 254 | OR_GPCM_TRLX_SET \ 255 | OR_GPCM_EHTR_SET) 256 257 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 258 /* 127 64KB sectors and 8 8KB top sectors per device */ 259 #define CONFIG_SYS_MAX_FLASH_SECT 135 260 261 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 262 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 263 264 /* 265 * NAND Flash on the Local Bus 266 */ 267 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 268 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ 269 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 270 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 271 | BR_PS_8 /* 8 bit Port */ \ 272 | BR_MS_FCM /* MSEL = FCM */ \ 273 | BR_V) /* valid */ 274 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 275 | OR_FCM_CSCT \ 276 | OR_FCM_CST \ 277 | OR_FCM_CHT \ 278 | OR_FCM_SCY_1 \ 279 | OR_FCM_TRLX \ 280 | OR_FCM_EHTR) 281 /* 0xFFFF8396 */ 282 283 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 284 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 285 286 #ifdef CONFIG_VSC7385_ENET 287 #define CONFIG_TSEC2 288 /* VSC7385 Base address on CS2 */ 289 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 290 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 291 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 292 | BR_PS_8 /* 8-bit port */ \ 293 | BR_MS_GPCM /* MSEL = GPCM */ \ 294 | BR_V) /* valid */ 295 /* 0xF0000801 */ 296 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 297 | OR_GPCM_CSNT \ 298 | OR_GPCM_XACS \ 299 | OR_GPCM_SCY_15 \ 300 | OR_GPCM_SETA \ 301 | OR_GPCM_TRLX_SET \ 302 | OR_GPCM_EHTR_SET) 303 /* 0xFFFE09FF */ 304 /* Access window base at VSC7385 base */ 305 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 306 /* Access window size 128K */ 307 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 308 /* The flash address and size of the VSC7385 firmware image */ 309 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 310 #define CONFIG_VSC7385_IMAGE_SIZE 8192 311 #endif 312 /* 313 * Serial Port 314 */ 315 #define CONFIG_CONS_INDEX 1 316 #define CONFIG_SYS_NS16550 317 #define CONFIG_SYS_NS16550_SERIAL 318 #define CONFIG_SYS_NS16550_REG_SIZE 1 319 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 320 321 #define CONFIG_SYS_BAUDRATE_TABLE \ 322 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 323 324 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 325 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 326 327 /* Use the HUSH parser */ 328 #define CONFIG_SYS_HUSH_PARSER 329 330 /* Pass open firmware flat tree */ 331 #define CONFIG_OF_LIBFDT 1 332 #define CONFIG_OF_BOARD_SETUP 1 333 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 334 335 /* I2C */ 336 #define CONFIG_SYS_I2C 337 #define CONFIG_SYS_I2C_FSL 338 #define CONFIG_SYS_FSL_I2C_SPEED 400000 339 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 340 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 341 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 342 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 343 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 344 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 345 346 /* 347 * SPI on header J8 348 * 349 * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) 350 * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. 351 */ 352 #ifdef CONFIG_MPC8XXX_SPI 353 #define CONFIG_CMD_SPI 354 #define CONFIG_USE_SPIFLASH 355 #define CONFIG_SPI_FLASH 356 #define CONFIG_SPI_FLASH_SPANSION 357 #define CONFIG_CMD_SF 358 #endif 359 360 /* 361 * Board info - revision and where boot from 362 */ 363 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 364 365 /* 366 * Config on-board RTC 367 */ 368 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 369 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 370 371 /* 372 * General PCI 373 * Addresses are mapped 1-1. 374 */ 375 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 376 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 377 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 378 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 379 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 380 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 381 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 382 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 383 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 384 385 /* enable PCIE clock */ 386 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 387 388 #define CONFIG_PCI 389 #define CONFIG_PCI_INDIRECT_BRIDGE 390 #define CONFIG_PCIE 391 392 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 393 394 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 395 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 396 397 /* 398 * TSEC 399 */ 400 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 401 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 402 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 403 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 404 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 405 406 /* 407 * TSEC ethernet configuration 408 */ 409 #define CONFIG_MII 1 /* MII PHY management */ 410 #define CONFIG_TSEC1_NAME "eTSEC0" 411 #define CONFIG_TSEC2_NAME "eTSEC1" 412 #define TSEC1_PHY_ADDR 2 413 #define TSEC2_PHY_ADDR 1 414 #define TSEC1_PHYIDX 0 415 #define TSEC2_PHYIDX 0 416 #define TSEC1_FLAGS TSEC_GIGABIT 417 #define TSEC2_FLAGS TSEC_GIGABIT 418 419 /* Options are: eTSEC[0-1] */ 420 #define CONFIG_ETHPRIME "eTSEC0" 421 422 /* 423 * Environment 424 */ 425 #define CONFIG_ENV_IS_IN_FLASH 1 426 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 427 CONFIG_SYS_MONITOR_LEN) 428 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 429 #define CONFIG_ENV_SIZE 0x2000 430 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 431 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 432 433 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 434 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 435 436 /* 437 * BOOTP options 438 */ 439 #define CONFIG_BOOTP_BOOTFILESIZE 440 #define CONFIG_BOOTP_BOOTPATH 441 #define CONFIG_BOOTP_GATEWAY 442 #define CONFIG_BOOTP_HOSTNAME 443 444 /* 445 * Command line configuration. 446 */ 447 #include <config_cmd_default.h> 448 449 #define CONFIG_CMD_DATE 450 #define CONFIG_CMD_DHCP 451 #define CONFIG_CMD_I2C 452 #define CONFIG_CMD_MII 453 #define CONFIG_CMD_NET 454 #define CONFIG_CMD_PCI 455 #define CONFIG_CMD_PING 456 457 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 458 459 /* 460 * Miscellaneous configurable options 461 */ 462 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 463 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 464 465 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 466 467 /* Print Buffer Size */ 468 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 469 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 470 /* Boot Argument Buffer Size */ 471 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 472 473 /* 474 * For booting Linux, the board info and command line data 475 * have to be in the first 256 MB of memory, since this is 476 * the maximum mapped by the Linux kernel during initialization. 477 */ 478 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 479 480 /* 481 * Core HID Setup 482 */ 483 #define CONFIG_SYS_HID0_INIT 0x000000000 484 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 485 HID0_ENABLE_INSTRUCTION_CACHE | \ 486 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 487 #define CONFIG_SYS_HID2 HID2_HBE 488 489 /* 490 * MMU Setup 491 */ 492 493 /* DDR: cache cacheable */ 494 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 495 BATL_MEMCOHERENCE) 496 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 497 BATU_VS | BATU_VP) 498 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 499 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 500 501 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 502 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 503 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 504 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 505 BATU_VP) 506 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 507 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 508 509 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 510 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 511 BATL_MEMCOHERENCE) 512 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 513 BATU_VS | BATU_VP) 514 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 515 BATL_CACHEINHIBIT | \ 516 BATL_GUARDEDSTORAGE) 517 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 518 519 /* Stack in dcache: cacheable, no memory coherence */ 520 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 521 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 522 BATU_VS | BATU_VP) 523 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 524 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 525 526 /* 527 * Environment Configuration 528 */ 529 530 #define CONFIG_ENV_OVERWRITE 531 532 #if defined(CONFIG_TSEC_ENET) 533 #define CONFIG_HAS_ETH0 534 #define CONFIG_HAS_ETH1 535 #endif 536 537 #define CONFIG_BAUDRATE 115200 538 539 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 540 541 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 542 543 #define CONFIG_EXTRA_ENV_SETTINGS \ 544 "netdev=eth0\0" \ 545 "consoledev=ttyS0\0" \ 546 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 547 "nfsroot=${serverip}:${rootpath}\0" \ 548 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 549 "addip=setenv bootargs ${bootargs} " \ 550 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 551 ":${hostname}:${netdev}:off panic=1\0" \ 552 "addtty=setenv bootargs ${bootargs}" \ 553 " console=${consoledev},${baudrate}\0" \ 554 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 555 "addmisc=setenv bootargs ${bootargs}\0" \ 556 "kernel_addr=FE080000\0" \ 557 "fdt_addr=FE280000\0" \ 558 "ramdisk_addr=FE290000\0" \ 559 "u-boot=mpc8308rdb/u-boot.bin\0" \ 560 "kernel_addr_r=1000000\0" \ 561 "fdt_addr_r=C00000\0" \ 562 "hostname=mpc8308rdb\0" \ 563 "bootfile=mpc8308rdb/uImage\0" \ 564 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ 565 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 566 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 567 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 568 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 569 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 570 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 571 "tftp ${fdt_addr_r} ${fdtfile};" \ 572 "run nfsargs addip addtty addmtd addmisc;" \ 573 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 574 "bootcmd=run flash_self\0" \ 575 "load=tftp ${loadaddr} ${u-boot}\0" \ 576 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 577 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 578 " +${filesize};cp.b ${fileaddr} " \ 579 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 580 "upd=run load update\0" \ 581 582 #endif /* __CONFIG_H */ 583