1 /* 2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC830x 1 /* MPC830x family */ 17 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 18 #define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ 19 20 #define CONFIG_SYS_TEXT_BASE 0xFE000000 21 22 #define CONFIG_MISC_INIT_R 23 24 #define CONFIG_MMC 1 25 26 #ifdef CONFIG_MMC 27 #define CONFIG_FSL_ESDHC 28 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 29 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 30 #define CONFIG_SYS_FSL_ESDHC_USE_PIO 31 32 #define CONFIG_GENERIC_MMC 33 #define CONFIG_DOS_PARTITION 34 #endif 35 36 /* 37 * On-board devices 38 * 39 * TSEC1 is SoC TSEC 40 * TSEC2 is VSC switch 41 */ 42 #define CONFIG_TSEC1 43 #define CONFIG_VSC7385_ENET 44 45 /* 46 * System Clock Setup 47 */ 48 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 49 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 50 51 /* 52 * Hardware Reset Configuration Word 53 * if CLKIN is 66.66MHz, then 54 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 55 * We choose the A type silicon as default, so the core is 400Mhz. 56 */ 57 #define CONFIG_SYS_HRCW_LOW (\ 58 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 59 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 60 HRCWL_SVCOD_DIV_2 |\ 61 HRCWL_CSB_TO_CLKIN_4X1 |\ 62 HRCWL_CORE_TO_CSB_3X1) 63 /* 64 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 65 * in 8308's HRCWH according to the manual, but original Freescale's 66 * code has them and I've expirienced some problems using the board 67 * with BDI3000 attached when I've tried to set these bits to zero 68 * (UART doesn't work after the 'reset run' command). 69 */ 70 #define CONFIG_SYS_HRCW_HIGH (\ 71 HRCWH_PCI_HOST |\ 72 HRCWH_PCI1_ARBITER_ENABLE |\ 73 HRCWH_CORE_ENABLE |\ 74 HRCWH_FROM_0X00000100 |\ 75 HRCWH_BOOTSEQ_DISABLE |\ 76 HRCWH_SW_WATCHDOG_DISABLE |\ 77 HRCWH_ROM_LOC_LOCAL_16BIT |\ 78 HRCWH_RL_EXT_LEGACY |\ 79 HRCWH_TSEC1M_IN_RGMII |\ 80 HRCWH_TSEC2M_IN_RGMII |\ 81 HRCWH_BIG_ENDIAN) 82 83 /* 84 * System IO Config 85 */ 86 #define CONFIG_SYS_SICRH (\ 87 SICRH_ESDHC_A_SD |\ 88 SICRH_ESDHC_B_SD |\ 89 SICRH_ESDHC_C_SD |\ 90 SICRH_GPIO_A_TSEC2 |\ 91 SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ 92 SICRH_IEEE1588_A_GPIO |\ 93 SICRH_USB |\ 94 SICRH_GTM_GPIO |\ 95 SICRH_IEEE1588_B_GPIO |\ 96 SICRH_ETSEC2_CRS |\ 97 SICRH_GPIOSEL_1 |\ 98 SICRH_TMROBI_V3P3 |\ 99 SICRH_TSOBI1_V2P5 |\ 100 SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ 101 #define CONFIG_SYS_SICRL (\ 102 SICRL_SPI_PF0 |\ 103 SICRL_UART_PF0 |\ 104 SICRL_IRQ_PF0 |\ 105 SICRL_I2C2_PF0 |\ 106 SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ 107 108 /* 109 * IMMR new address 110 */ 111 #define CONFIG_SYS_IMMR 0xE0000000 112 113 /* 114 * SERDES 115 */ 116 #define CONFIG_FSL_SERDES 117 #define CONFIG_FSL_SERDES1 0xe3000 118 119 /* 120 * Arbiter Setup 121 */ 122 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 123 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 124 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 125 126 /* 127 * DDR Setup 128 */ 129 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 130 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 131 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 132 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 133 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 134 | DDRCDR_PZ_LOZ \ 135 | DDRCDR_NZ_LOZ \ 136 | DDRCDR_ODT \ 137 | DDRCDR_Q_DRN) 138 /* 0x7b880001 */ 139 /* 140 * Manually set up DDR parameters 141 * consist of two chips HY5PS12621BFP-C4 from HYNIX 142 */ 143 144 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 145 146 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 147 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 148 | CSCONFIG_ODT_RD_NEVER \ 149 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 150 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 151 /* 0x80010102 */ 152 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 153 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 154 | (0 << TIMING_CFG0_WRT_SHIFT) \ 155 | (0 << TIMING_CFG0_RRT_SHIFT) \ 156 | (0 << TIMING_CFG0_WWT_SHIFT) \ 157 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 158 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 159 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 160 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 161 /* 0x00220802 */ 162 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 163 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 164 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 165 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 166 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 167 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 168 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 169 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 170 /* 0x27256222 */ 171 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 172 | (4 << TIMING_CFG2_CPO_SHIFT) \ 173 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 174 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 175 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 176 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 177 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 178 /* 0x121048c5 */ 179 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 180 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 181 /* 0x03600100 */ 182 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 183 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 184 | SDRAM_CFG_DBW_32) 185 /* 0x43080000 */ 186 187 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 188 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 189 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 190 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 191 #define CONFIG_SYS_DDR_MODE2 0x00000000 192 193 /* 194 * Memory test 195 */ 196 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 197 #define CONFIG_SYS_MEMTEST_END 0x07f00000 198 199 /* 200 * The reserved memory 201 */ 202 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 203 204 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 205 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 206 207 /* 208 * Initial RAM Base Address Setup 209 */ 210 #define CONFIG_SYS_INIT_RAM_LOCK 1 211 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 212 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 213 #define CONFIG_SYS_GBL_DATA_OFFSET \ 214 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 215 216 /* 217 * Local Bus Configuration & Clock Setup 218 */ 219 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 220 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 221 #define CONFIG_SYS_LBC_LBCR 0x00040000 222 223 /* 224 * FLASH on the Local Bus 225 */ 226 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 227 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 228 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 229 230 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 231 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 232 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 233 234 /* Window base at flash base */ 235 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 236 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 237 238 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 239 | BR_PS_16 /* 16 bit port */ \ 240 | BR_MS_GPCM /* MSEL = GPCM */ \ 241 | BR_V) /* valid */ 242 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 243 | OR_UPM_XAM \ 244 | OR_GPCM_CSNT \ 245 | OR_GPCM_ACS_DIV2 \ 246 | OR_GPCM_XACS \ 247 | OR_GPCM_SCY_15 \ 248 | OR_GPCM_TRLX_SET \ 249 | OR_GPCM_EHTR_SET) 250 251 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 252 /* 127 64KB sectors and 8 8KB top sectors per device */ 253 #define CONFIG_SYS_MAX_FLASH_SECT 135 254 255 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 256 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 257 258 /* 259 * NAND Flash on the Local Bus 260 */ 261 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 262 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ 263 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 264 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 265 | BR_PS_8 /* 8 bit Port */ \ 266 | BR_MS_FCM /* MSEL = FCM */ \ 267 | BR_V) /* valid */ 268 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 269 | OR_FCM_CSCT \ 270 | OR_FCM_CST \ 271 | OR_FCM_CHT \ 272 | OR_FCM_SCY_1 \ 273 | OR_FCM_TRLX \ 274 | OR_FCM_EHTR) 275 /* 0xFFFF8396 */ 276 277 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 278 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 279 280 #ifdef CONFIG_VSC7385_ENET 281 #define CONFIG_TSEC2 282 /* VSC7385 Base address on CS2 */ 283 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 284 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 285 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 286 | BR_PS_8 /* 8-bit port */ \ 287 | BR_MS_GPCM /* MSEL = GPCM */ \ 288 | BR_V) /* valid */ 289 /* 0xF0000801 */ 290 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 291 | OR_GPCM_CSNT \ 292 | OR_GPCM_XACS \ 293 | OR_GPCM_SCY_15 \ 294 | OR_GPCM_SETA \ 295 | OR_GPCM_TRLX_SET \ 296 | OR_GPCM_EHTR_SET) 297 /* 0xFFFE09FF */ 298 /* Access window base at VSC7385 base */ 299 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 300 /* Access window size 128K */ 301 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 302 /* The flash address and size of the VSC7385 firmware image */ 303 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 304 #define CONFIG_VSC7385_IMAGE_SIZE 8192 305 #endif 306 /* 307 * Serial Port 308 */ 309 #define CONFIG_CONS_INDEX 1 310 #define CONFIG_SYS_NS16550_SERIAL 311 #define CONFIG_SYS_NS16550_REG_SIZE 1 312 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 313 314 #define CONFIG_SYS_BAUDRATE_TABLE \ 315 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 316 317 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 318 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 319 320 /* I2C */ 321 #define CONFIG_SYS_I2C 322 #define CONFIG_SYS_I2C_FSL 323 #define CONFIG_SYS_FSL_I2C_SPEED 400000 324 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 325 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 326 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 327 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 328 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 329 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 330 331 /* 332 * SPI on header J8 333 * 334 * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) 335 * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. 336 */ 337 #ifdef CONFIG_MPC8XXX_SPI 338 #define CONFIG_USE_SPIFLASH 339 #endif 340 341 /* 342 * Board info - revision and where boot from 343 */ 344 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 345 346 /* 347 * Config on-board RTC 348 */ 349 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 350 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 351 352 /* 353 * General PCI 354 * Addresses are mapped 1-1. 355 */ 356 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 357 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 358 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 359 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 360 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 361 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 362 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 363 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 364 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 365 366 /* enable PCIE clock */ 367 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 368 369 #define CONFIG_PCI_INDIRECT_BRIDGE 370 #define CONFIG_PCIE 371 372 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 373 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 374 375 /* 376 * TSEC 377 */ 378 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 379 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 380 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 381 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 382 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 383 384 /* 385 * TSEC ethernet configuration 386 */ 387 #define CONFIG_MII 1 /* MII PHY management */ 388 #define CONFIG_TSEC1_NAME "eTSEC0" 389 #define CONFIG_TSEC2_NAME "eTSEC1" 390 #define TSEC1_PHY_ADDR 2 391 #define TSEC2_PHY_ADDR 1 392 #define TSEC1_PHYIDX 0 393 #define TSEC2_PHYIDX 0 394 #define TSEC1_FLAGS TSEC_GIGABIT 395 #define TSEC2_FLAGS TSEC_GIGABIT 396 397 /* Options are: eTSEC[0-1] */ 398 #define CONFIG_ETHPRIME "eTSEC0" 399 400 /* 401 * Environment 402 */ 403 #define CONFIG_ENV_IS_IN_FLASH 1 404 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 405 CONFIG_SYS_MONITOR_LEN) 406 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 407 #define CONFIG_ENV_SIZE 0x2000 408 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 409 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 410 411 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 412 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 413 414 /* 415 * BOOTP options 416 */ 417 #define CONFIG_BOOTP_BOOTFILESIZE 418 #define CONFIG_BOOTP_BOOTPATH 419 #define CONFIG_BOOTP_GATEWAY 420 #define CONFIG_BOOTP_HOSTNAME 421 422 /* 423 * Command line configuration. 424 */ 425 #define CONFIG_CMD_DATE 426 #define CONFIG_CMD_PCI 427 428 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 429 430 /* 431 * Miscellaneous configurable options 432 */ 433 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 434 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 435 436 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 437 438 /* Print Buffer Size */ 439 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 440 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 441 /* Boot Argument Buffer Size */ 442 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 443 444 /* 445 * For booting Linux, the board info and command line data 446 * have to be in the first 256 MB of memory, since this is 447 * the maximum mapped by the Linux kernel during initialization. 448 */ 449 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 450 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 451 452 /* 453 * Core HID Setup 454 */ 455 #define CONFIG_SYS_HID0_INIT 0x000000000 456 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 457 HID0_ENABLE_INSTRUCTION_CACHE | \ 458 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 459 #define CONFIG_SYS_HID2 HID2_HBE 460 461 /* 462 * MMU Setup 463 */ 464 465 /* DDR: cache cacheable */ 466 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 467 BATL_MEMCOHERENCE) 468 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 469 BATU_VS | BATU_VP) 470 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 471 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 472 473 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 474 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 475 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 476 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 477 BATU_VP) 478 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 479 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 480 481 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 482 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 483 BATL_MEMCOHERENCE) 484 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 485 BATU_VS | BATU_VP) 486 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 487 BATL_CACHEINHIBIT | \ 488 BATL_GUARDEDSTORAGE) 489 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 490 491 /* Stack in dcache: cacheable, no memory coherence */ 492 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 493 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 494 BATU_VS | BATU_VP) 495 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 496 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 497 498 /* 499 * Environment Configuration 500 */ 501 502 #define CONFIG_ENV_OVERWRITE 503 504 #if defined(CONFIG_TSEC_ENET) 505 #define CONFIG_HAS_ETH0 506 #define CONFIG_HAS_ETH1 507 #endif 508 509 #define CONFIG_BAUDRATE 115200 510 511 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 512 513 514 #define CONFIG_EXTRA_ENV_SETTINGS \ 515 "netdev=eth0\0" \ 516 "consoledev=ttyS0\0" \ 517 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 518 "nfsroot=${serverip}:${rootpath}\0" \ 519 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 520 "addip=setenv bootargs ${bootargs} " \ 521 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 522 ":${hostname}:${netdev}:off panic=1\0" \ 523 "addtty=setenv bootargs ${bootargs}" \ 524 " console=${consoledev},${baudrate}\0" \ 525 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 526 "addmisc=setenv bootargs ${bootargs}\0" \ 527 "kernel_addr=FE080000\0" \ 528 "fdt_addr=FE280000\0" \ 529 "ramdisk_addr=FE290000\0" \ 530 "u-boot=mpc8308rdb/u-boot.bin\0" \ 531 "kernel_addr_r=1000000\0" \ 532 "fdt_addr_r=C00000\0" \ 533 "hostname=mpc8308rdb\0" \ 534 "bootfile=mpc8308rdb/uImage\0" \ 535 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ 536 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 537 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 538 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 539 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 540 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 541 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 542 "tftp ${fdt_addr_r} ${fdtfile};" \ 543 "run nfsargs addip addtty addmtd addmisc;" \ 544 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 545 "bootcmd=run flash_self\0" \ 546 "load=tftp ${loadaddr} ${u-boot}\0" \ 547 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 548 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 549 " +${filesize};cp.b ${fileaddr} " \ 550 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 551 "upd=run load update\0" \ 552 553 #endif /* __CONFIG_H */ 554