1 /* 2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC830x 1 /* MPC830x family */ 17 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 18 19 #define CONFIG_SYS_TEXT_BASE 0xFE000000 20 21 #define CONFIG_MISC_INIT_R 22 23 #ifdef CONFIG_MMC 24 #define CONFIG_FSL_ESDHC 25 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 26 #define CONFIG_SYS_FSL_ESDHC_USE_PIO 27 #endif 28 29 /* 30 * On-board devices 31 * 32 * TSEC1 is SoC TSEC 33 * TSEC2 is VSC switch 34 */ 35 #define CONFIG_TSEC1 36 #define CONFIG_VSC7385_ENET 37 38 /* 39 * System Clock Setup 40 */ 41 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 42 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 43 44 /* 45 * Hardware Reset Configuration Word 46 * if CLKIN is 66.66MHz, then 47 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 48 * We choose the A type silicon as default, so the core is 400Mhz. 49 */ 50 #define CONFIG_SYS_HRCW_LOW (\ 51 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 52 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 53 HRCWL_SVCOD_DIV_2 |\ 54 HRCWL_CSB_TO_CLKIN_4X1 |\ 55 HRCWL_CORE_TO_CSB_3X1) 56 /* 57 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 58 * in 8308's HRCWH according to the manual, but original Freescale's 59 * code has them and I've expirienced some problems using the board 60 * with BDI3000 attached when I've tried to set these bits to zero 61 * (UART doesn't work after the 'reset run' command). 62 */ 63 #define CONFIG_SYS_HRCW_HIGH (\ 64 HRCWH_PCI_HOST |\ 65 HRCWH_PCI1_ARBITER_ENABLE |\ 66 HRCWH_CORE_ENABLE |\ 67 HRCWH_FROM_0X00000100 |\ 68 HRCWH_BOOTSEQ_DISABLE |\ 69 HRCWH_SW_WATCHDOG_DISABLE |\ 70 HRCWH_ROM_LOC_LOCAL_16BIT |\ 71 HRCWH_RL_EXT_LEGACY |\ 72 HRCWH_TSEC1M_IN_RGMII |\ 73 HRCWH_TSEC2M_IN_RGMII |\ 74 HRCWH_BIG_ENDIAN) 75 76 /* 77 * System IO Config 78 */ 79 #define CONFIG_SYS_SICRH (\ 80 SICRH_ESDHC_A_SD |\ 81 SICRH_ESDHC_B_SD |\ 82 SICRH_ESDHC_C_SD |\ 83 SICRH_GPIO_A_TSEC2 |\ 84 SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ 85 SICRH_IEEE1588_A_GPIO |\ 86 SICRH_USB |\ 87 SICRH_GTM_GPIO |\ 88 SICRH_IEEE1588_B_GPIO |\ 89 SICRH_ETSEC2_CRS |\ 90 SICRH_GPIOSEL_1 |\ 91 SICRH_TMROBI_V3P3 |\ 92 SICRH_TSOBI1_V2P5 |\ 93 SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ 94 #define CONFIG_SYS_SICRL (\ 95 SICRL_SPI_PF0 |\ 96 SICRL_UART_PF0 |\ 97 SICRL_IRQ_PF0 |\ 98 SICRL_I2C2_PF0 |\ 99 SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ 100 101 /* 102 * IMMR new address 103 */ 104 #define CONFIG_SYS_IMMR 0xE0000000 105 106 /* 107 * SERDES 108 */ 109 #define CONFIG_FSL_SERDES 110 #define CONFIG_FSL_SERDES1 0xe3000 111 112 /* 113 * Arbiter Setup 114 */ 115 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 116 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 117 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 118 119 /* 120 * DDR Setup 121 */ 122 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 123 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 124 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 125 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 126 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 127 | DDRCDR_PZ_LOZ \ 128 | DDRCDR_NZ_LOZ \ 129 | DDRCDR_ODT \ 130 | DDRCDR_Q_DRN) 131 /* 0x7b880001 */ 132 /* 133 * Manually set up DDR parameters 134 * consist of two chips HY5PS12621BFP-C4 from HYNIX 135 */ 136 137 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 138 139 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 140 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 141 | CSCONFIG_ODT_RD_NEVER \ 142 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 143 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 144 /* 0x80010102 */ 145 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 146 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 147 | (0 << TIMING_CFG0_WRT_SHIFT) \ 148 | (0 << TIMING_CFG0_RRT_SHIFT) \ 149 | (0 << TIMING_CFG0_WWT_SHIFT) \ 150 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 151 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 152 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 153 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 154 /* 0x00220802 */ 155 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 156 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 157 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 158 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 159 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 160 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 161 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 162 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 163 /* 0x27256222 */ 164 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 165 | (4 << TIMING_CFG2_CPO_SHIFT) \ 166 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 167 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 168 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 169 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 170 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 171 /* 0x121048c5 */ 172 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 173 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 174 /* 0x03600100 */ 175 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 176 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 177 | SDRAM_CFG_DBW_32) 178 /* 0x43080000 */ 179 180 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 181 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 182 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 183 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 184 #define CONFIG_SYS_DDR_MODE2 0x00000000 185 186 /* 187 * Memory test 188 */ 189 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 190 #define CONFIG_SYS_MEMTEST_END 0x07f00000 191 192 /* 193 * The reserved memory 194 */ 195 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 196 197 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 198 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 199 200 /* 201 * Initial RAM Base Address Setup 202 */ 203 #define CONFIG_SYS_INIT_RAM_LOCK 1 204 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 205 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 206 #define CONFIG_SYS_GBL_DATA_OFFSET \ 207 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 208 209 /* 210 * Local Bus Configuration & Clock Setup 211 */ 212 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 213 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 214 #define CONFIG_SYS_LBC_LBCR 0x00040000 215 216 /* 217 * FLASH on the Local Bus 218 */ 219 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 220 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 221 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 222 223 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 224 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 225 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 226 227 /* Window base at flash base */ 228 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 229 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 230 231 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 232 | BR_PS_16 /* 16 bit port */ \ 233 | BR_MS_GPCM /* MSEL = GPCM */ \ 234 | BR_V) /* valid */ 235 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 236 | OR_UPM_XAM \ 237 | OR_GPCM_CSNT \ 238 | OR_GPCM_ACS_DIV2 \ 239 | OR_GPCM_XACS \ 240 | OR_GPCM_SCY_15 \ 241 | OR_GPCM_TRLX_SET \ 242 | OR_GPCM_EHTR_SET) 243 244 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 245 /* 127 64KB sectors and 8 8KB top sectors per device */ 246 #define CONFIG_SYS_MAX_FLASH_SECT 135 247 248 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 249 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 250 251 /* 252 * NAND Flash on the Local Bus 253 */ 254 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 255 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ 256 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 257 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 258 | BR_PS_8 /* 8 bit Port */ \ 259 | BR_MS_FCM /* MSEL = FCM */ \ 260 | BR_V) /* valid */ 261 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 262 | OR_FCM_CSCT \ 263 | OR_FCM_CST \ 264 | OR_FCM_CHT \ 265 | OR_FCM_SCY_1 \ 266 | OR_FCM_TRLX \ 267 | OR_FCM_EHTR) 268 /* 0xFFFF8396 */ 269 270 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 271 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 272 273 #ifdef CONFIG_VSC7385_ENET 274 #define CONFIG_TSEC2 275 /* VSC7385 Base address on CS2 */ 276 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 277 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 278 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 279 | BR_PS_8 /* 8-bit port */ \ 280 | BR_MS_GPCM /* MSEL = GPCM */ \ 281 | BR_V) /* valid */ 282 /* 0xF0000801 */ 283 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 284 | OR_GPCM_CSNT \ 285 | OR_GPCM_XACS \ 286 | OR_GPCM_SCY_15 \ 287 | OR_GPCM_SETA \ 288 | OR_GPCM_TRLX_SET \ 289 | OR_GPCM_EHTR_SET) 290 /* 0xFFFE09FF */ 291 /* Access window base at VSC7385 base */ 292 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 293 /* Access window size 128K */ 294 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 295 /* The flash address and size of the VSC7385 firmware image */ 296 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 297 #define CONFIG_VSC7385_IMAGE_SIZE 8192 298 #endif 299 /* 300 * Serial Port 301 */ 302 #define CONFIG_CONS_INDEX 1 303 #define CONFIG_SYS_NS16550_SERIAL 304 #define CONFIG_SYS_NS16550_REG_SIZE 1 305 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 306 307 #define CONFIG_SYS_BAUDRATE_TABLE \ 308 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 309 310 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 311 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 312 313 /* I2C */ 314 #define CONFIG_SYS_I2C 315 #define CONFIG_SYS_I2C_FSL 316 #define CONFIG_SYS_FSL_I2C_SPEED 400000 317 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 318 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 319 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 320 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 321 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 322 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 323 324 /* 325 * SPI on header J8 326 * 327 * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) 328 * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. 329 */ 330 #ifdef CONFIG_MPC8XXX_SPI 331 #define CONFIG_USE_SPIFLASH 332 #endif 333 334 /* 335 * Board info - revision and where boot from 336 */ 337 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 338 339 /* 340 * Config on-board RTC 341 */ 342 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 343 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 344 345 /* 346 * General PCI 347 * Addresses are mapped 1-1. 348 */ 349 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 350 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 351 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 352 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 353 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 354 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 355 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 356 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 357 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 358 359 /* enable PCIE clock */ 360 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 361 362 #define CONFIG_PCI_INDIRECT_BRIDGE 363 #define CONFIG_PCIE 364 365 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 366 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 367 368 /* 369 * TSEC 370 */ 371 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 372 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 373 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 374 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 375 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 376 377 /* 378 * TSEC ethernet configuration 379 */ 380 #define CONFIG_MII 1 /* MII PHY management */ 381 #define CONFIG_TSEC1_NAME "eTSEC0" 382 #define CONFIG_TSEC2_NAME "eTSEC1" 383 #define TSEC1_PHY_ADDR 2 384 #define TSEC2_PHY_ADDR 1 385 #define TSEC1_PHYIDX 0 386 #define TSEC2_PHYIDX 0 387 #define TSEC1_FLAGS TSEC_GIGABIT 388 #define TSEC2_FLAGS TSEC_GIGABIT 389 390 /* Options are: eTSEC[0-1] */ 391 #define CONFIG_ETHPRIME "eTSEC0" 392 393 /* 394 * Environment 395 */ 396 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 397 CONFIG_SYS_MONITOR_LEN) 398 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 399 #define CONFIG_ENV_SIZE 0x2000 400 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 401 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 402 403 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 404 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 405 406 /* 407 * BOOTP options 408 */ 409 #define CONFIG_BOOTP_BOOTFILESIZE 410 #define CONFIG_BOOTP_BOOTPATH 411 #define CONFIG_BOOTP_GATEWAY 412 #define CONFIG_BOOTP_HOSTNAME 413 414 /* 415 * Command line configuration. 416 */ 417 418 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 419 420 /* 421 * Miscellaneous configurable options 422 */ 423 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 424 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 425 426 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 427 428 /* Boot Argument Buffer Size */ 429 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 430 431 /* 432 * For booting Linux, the board info and command line data 433 * have to be in the first 256 MB of memory, since this is 434 * the maximum mapped by the Linux kernel during initialization. 435 */ 436 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 437 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 438 439 /* 440 * Core HID Setup 441 */ 442 #define CONFIG_SYS_HID0_INIT 0x000000000 443 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 444 HID0_ENABLE_INSTRUCTION_CACHE | \ 445 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 446 #define CONFIG_SYS_HID2 HID2_HBE 447 448 /* 449 * MMU Setup 450 */ 451 452 /* DDR: cache cacheable */ 453 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 454 BATL_MEMCOHERENCE) 455 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 456 BATU_VS | BATU_VP) 457 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 458 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 459 460 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 461 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 462 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 463 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 464 BATU_VP) 465 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 466 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 467 468 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 469 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 470 BATL_MEMCOHERENCE) 471 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 472 BATU_VS | BATU_VP) 473 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 474 BATL_CACHEINHIBIT | \ 475 BATL_GUARDEDSTORAGE) 476 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 477 478 /* Stack in dcache: cacheable, no memory coherence */ 479 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 480 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 481 BATU_VS | BATU_VP) 482 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 483 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 484 485 /* 486 * Environment Configuration 487 */ 488 489 #define CONFIG_ENV_OVERWRITE 490 491 #if defined(CONFIG_TSEC_ENET) 492 #define CONFIG_HAS_ETH0 493 #define CONFIG_HAS_ETH1 494 #endif 495 496 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 497 498 499 #define CONFIG_EXTRA_ENV_SETTINGS \ 500 "netdev=eth0\0" \ 501 "consoledev=ttyS0\0" \ 502 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 503 "nfsroot=${serverip}:${rootpath}\0" \ 504 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 505 "addip=setenv bootargs ${bootargs} " \ 506 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 507 ":${hostname}:${netdev}:off panic=1\0" \ 508 "addtty=setenv bootargs ${bootargs}" \ 509 " console=${consoledev},${baudrate}\0" \ 510 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 511 "addmisc=setenv bootargs ${bootargs}\0" \ 512 "kernel_addr=FE080000\0" \ 513 "fdt_addr=FE280000\0" \ 514 "ramdisk_addr=FE290000\0" \ 515 "u-boot=mpc8308rdb/u-boot.bin\0" \ 516 "kernel_addr_r=1000000\0" \ 517 "fdt_addr_r=C00000\0" \ 518 "hostname=mpc8308rdb\0" \ 519 "bootfile=mpc8308rdb/uImage\0" \ 520 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ 521 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 522 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 523 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 524 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 525 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 526 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 527 "tftp ${fdt_addr_r} ${fdtfile};" \ 528 "run nfsargs addip addtty addmtd addmisc;" \ 529 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 530 "bootcmd=run flash_self\0" \ 531 "load=tftp ${loadaddr} ${u-boot}\0" \ 532 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 533 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 534 " +${filesize};cp.b ${fileaddr} " \ 535 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 536 "upd=run load update\0" \ 537 538 #endif /* __CONFIG_H */ 539