1 /* 2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4 * 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef __CONFIG_H 26 #define __CONFIG_H 27 28 /* 29 * High Level Configuration Options 30 */ 31 #define CONFIG_E300 1 /* E300 family */ 32 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 33 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 34 #define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ 35 36 #define CONFIG_MISC_INIT_R 37 38 /* 39 * On-board devices 40 * 41 * TSEC1 is SoC TSEC 42 * TSEC2 is VSC switch 43 */ 44 #define CONFIG_TSEC1 45 #define CONFIG_VSC7385_ENET 46 47 /* 48 * System Clock Setup 49 */ 50 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 51 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 52 53 /* 54 * Hardware Reset Configuration Word 55 * if CLKIN is 66.66MHz, then 56 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 57 * We choose the A type silicon as default, so the core is 400Mhz. 58 */ 59 #define CONFIG_SYS_HRCW_LOW (\ 60 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 61 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 62 HRCWL_SVCOD_DIV_2 |\ 63 HRCWL_CSB_TO_CLKIN_4X1 |\ 64 HRCWL_CORE_TO_CSB_3X1) 65 /* 66 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 67 * in 8308's HRCWH according to the manual, but original Freescale's 68 * code has them and I've expirienced some problems using the board 69 * with BDI3000 attached when I've tried to set these bits to zero 70 * (UART doesn't work after the 'reset run' command). 71 */ 72 #define CONFIG_SYS_HRCW_HIGH (\ 73 HRCWH_PCI_HOST |\ 74 HRCWH_PCI1_ARBITER_ENABLE |\ 75 HRCWH_CORE_ENABLE |\ 76 HRCWH_FROM_0X00000100 |\ 77 HRCWH_BOOTSEQ_DISABLE |\ 78 HRCWH_SW_WATCHDOG_DISABLE |\ 79 HRCWH_ROM_LOC_LOCAL_16BIT |\ 80 HRCWH_RL_EXT_LEGACY |\ 81 HRCWH_TSEC1M_IN_RGMII |\ 82 HRCWH_TSEC2M_IN_RGMII |\ 83 HRCWH_BIG_ENDIAN) 84 85 /* 86 * System IO Config 87 */ 88 #define CONFIG_SYS_SICRH 0x01b7d103 89 #define CONFIG_SYS_SICRL 0x00000040 /* 3.3V, no delay */ 90 91 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 92 93 /* 94 * IMMR new address 95 */ 96 #define CONFIG_SYS_IMMR 0xE0000000 97 98 /* 99 * SERDES 100 */ 101 #define CONFIG_FSL_SERDES 102 #define CONFIG_FSL_SERDES1 0xe3000 103 104 /* 105 * Arbiter Setup 106 */ 107 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 108 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 109 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 110 111 /* 112 * DDR Setup 113 */ 114 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 115 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 116 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 117 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 118 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 119 | DDRCDR_PZ_LOZ \ 120 | DDRCDR_NZ_LOZ \ 121 | DDRCDR_ODT \ 122 | DDRCDR_Q_DRN) 123 /* 0x7b880001 */ 124 /* 125 * Manually set up DDR parameters 126 * consist of two chips HY5PS12621BFP-C4 from HYNIX 127 */ 128 129 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 130 131 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 132 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 133 | 0x00010000 /* ODT_WR to CSn */ \ 134 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 135 /* 0x80010102 */ 136 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 137 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 138 | (0 << TIMING_CFG0_WRT_SHIFT) \ 139 | (0 << TIMING_CFG0_RRT_SHIFT) \ 140 | (0 << TIMING_CFG0_WWT_SHIFT) \ 141 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 142 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 143 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 144 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 145 /* 0x00220802 */ 146 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 147 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 148 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 149 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 150 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 151 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 152 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 153 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 154 /* 0x27256222 */ 155 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 156 | (4 << TIMING_CFG2_CPO_SHIFT) \ 157 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 158 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 159 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 160 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 161 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 162 /* 0x121048c5 */ 163 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 164 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 165 /* 0x03600100 */ 166 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 167 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 168 | SDRAM_CFG_32_BE) 169 /* 0x43080000 */ 170 171 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 172 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 173 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 174 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 175 #define CONFIG_SYS_DDR_MODE2 0x00000000 176 177 /* 178 * Memory test 179 */ 180 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 181 #define CONFIG_SYS_MEMTEST_END 0x07f00000 182 183 /* 184 * The reserved memory 185 */ 186 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 187 188 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 189 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 190 191 /* 192 * Initial RAM Base Address Setup 193 */ 194 #define CONFIG_SYS_INIT_RAM_LOCK 1 195 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 196 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ 197 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 198 #define CONFIG_SYS_GBL_DATA_OFFSET \ 199 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 200 201 /* 202 * Local Bus Configuration & Clock Setup 203 */ 204 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 205 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 206 #define CONFIG_SYS_LBC_LBCR 0x00040000 207 208 /* 209 * FLASH on the Local Bus 210 */ 211 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 212 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 213 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 214 215 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 216 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 217 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 218 219 /* Window base at flash base */ 220 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 221 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ 222 223 #define CONFIG_SYS_BR0_PRELIM (\ 224 CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\ 225 (2 << BR_PS_SHIFT) /* 16 bit port size */ |\ 226 BR_V) /* valid */ 227 #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ 228 | OR_UPM_XAM \ 229 | OR_GPCM_CSNT \ 230 | OR_GPCM_ACS_DIV2 \ 231 | OR_GPCM_XACS \ 232 | OR_GPCM_SCY_15 \ 233 | OR_GPCM_TRLX \ 234 | OR_GPCM_EHTR \ 235 | OR_GPCM_EAD) 236 237 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 238 /* 127 64KB sectors and 8 8KB top sectors per device */ 239 #define CONFIG_SYS_MAX_FLASH_SECT 135 240 241 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 242 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 243 244 /* 245 * NAND Flash on the Local Bus 246 */ 247 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 248 #define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ 249 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 250 | BR_PS_8 /* Port Size = 8 bit */ \ 251 | BR_MS_FCM /* MSEL = FCM */ \ 252 | BR_V ) /* valid */ 253 #define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ 254 | OR_FCM_CSCT \ 255 | OR_FCM_CST \ 256 | OR_FCM_CHT \ 257 | OR_FCM_SCY_1 \ 258 | OR_FCM_TRLX \ 259 | OR_FCM_EHTR ) 260 /* 0xFFFF8396 */ 261 262 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 263 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 264 265 #ifdef CONFIG_VSC7385_ENET 266 #define CONFIG_TSEC2 267 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 268 #define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ 269 #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ 270 /* Access window base at VSC7385 base */ 271 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 272 /* Access window size 128K */ 273 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 274 /* The flash address and size of the VSC7385 firmware image */ 275 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 276 #define CONFIG_VSC7385_IMAGE_SIZE 8192 277 #endif 278 /* 279 * Serial Port 280 */ 281 #define CONFIG_CONS_INDEX 1 282 #undef CONFIG_SERIAL_SOFTWARE_FIFO 283 #define CONFIG_SYS_NS16550 284 #define CONFIG_SYS_NS16550_SERIAL 285 #define CONFIG_SYS_NS16550_REG_SIZE 1 286 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 287 288 #define CONFIG_SYS_BAUDRATE_TABLE \ 289 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 290 291 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 292 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 293 294 /* Use the HUSH parser */ 295 #define CONFIG_SYS_HUSH_PARSER 296 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 297 298 /* Pass open firmware flat tree */ 299 #define CONFIG_OF_LIBFDT 1 300 #define CONFIG_OF_BOARD_SETUP 1 301 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 302 303 /* I2C */ 304 #define CONFIG_HARD_I2C /* I2C with hardware support */ 305 #define CONFIG_FSL_I2C 306 #define CONFIG_I2C_MULTI_BUS 307 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 308 #define CONFIG_SYS_I2C_SLAVE 0x7F 309 #define CONFIG_SYS_I2C_NOPROBES {{0x51}} /* Don't probe these addrs */ 310 #define CONFIG_SYS_I2C_OFFSET 0x3000 311 #define CONFIG_SYS_I2C2_OFFSET 0x3100 312 313 314 /* 315 * Board info - revision and where boot from 316 */ 317 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 318 319 /* 320 * Config on-board RTC 321 */ 322 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 323 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 324 325 /* 326 * General PCI 327 * Addresses are mapped 1-1. 328 */ 329 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 330 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 331 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 332 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 333 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 334 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 335 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 336 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 337 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 338 339 /* 340 * Fake PCIE2 definitions: there is no PCIE2 on this board but the code 341 * in arch/powerpc/cpu/mpc83xx/pcie.c doesn't compile without this 342 */ 343 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 344 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 345 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 346 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 347 #define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 348 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 349 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 350 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 351 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 352 353 #define CONFIG_PCI 354 #define CONFIG_PCIE 355 356 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 357 358 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 359 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 360 361 /* 362 * TSEC 363 */ 364 #define CONFIG_NET_MULTI 365 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 366 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 367 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 368 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 369 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 370 371 /* 372 * TSEC ethernet configuration 373 */ 374 #define CONFIG_MII 1 /* MII PHY management */ 375 #define CONFIG_TSEC1_NAME "eTSEC0" 376 #define CONFIG_TSEC2_NAME "eTSEC1" 377 #define TSEC1_PHY_ADDR 2 378 #define TSEC2_PHY_ADDR 1 379 #define TSEC1_PHYIDX 0 380 #define TSEC2_PHYIDX 0 381 #define TSEC1_FLAGS TSEC_GIGABIT 382 #define TSEC2_FLAGS TSEC_GIGABIT 383 384 /* Options are: eTSEC[0-1] */ 385 #define CONFIG_ETHPRIME "eTSEC0" 386 387 /* 388 * Environment 389 */ 390 #define CONFIG_ENV_IS_IN_FLASH 1 391 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 392 CONFIG_SYS_MONITOR_LEN) 393 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 394 #define CONFIG_ENV_SIZE 0x2000 395 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 396 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 397 398 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 399 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 400 401 /* 402 * BOOTP options 403 */ 404 #define CONFIG_BOOTP_BOOTFILESIZE 405 #define CONFIG_BOOTP_BOOTPATH 406 #define CONFIG_BOOTP_GATEWAY 407 #define CONFIG_BOOTP_HOSTNAME 408 409 /* 410 * Command line configuration. 411 */ 412 #include <config_cmd_default.h> 413 414 #define CONFIG_CMD_DATE 415 #define CONFIG_CMD_DHCP 416 #define CONFIG_CMD_I2C 417 #define CONFIG_CMD_MII 418 #define CONFIG_CMD_NET 419 #define CONFIG_CMD_PCI 420 #define CONFIG_CMD_PING 421 422 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 423 424 /* 425 * Miscellaneous configurable options 426 */ 427 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 428 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 429 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 430 431 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 432 433 /* Print Buffer Size */ 434 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 435 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 436 /* Boot Argument Buffer Size */ 437 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 438 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 439 440 /* 441 * For booting Linux, the board info and command line data 442 * have to be in the first 8 MB of memory, since this is 443 * the maximum mapped by the Linux kernel during initialization. 444 */ 445 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 446 447 /* 448 * Core HID Setup 449 */ 450 #define CONFIG_SYS_HID0_INIT 0x000000000 451 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 452 HID0_ENABLE_INSTRUCTION_CACHE | \ 453 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 454 #define CONFIG_SYS_HID2 HID2_HBE 455 456 /* 457 * MMU Setup 458 */ 459 460 /* DDR: cache cacheable */ 461 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ 462 BATL_MEMCOHERENCE) 463 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 464 BATU_VS | BATU_VP) 465 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 466 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 467 468 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 469 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ 470 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 471 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 472 BATU_VP) 473 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 474 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 475 476 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 477 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ 478 BATL_MEMCOHERENCE) 479 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 480 BATU_VS | BATU_VP) 481 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ 482 BATL_CACHEINHIBIT | \ 483 BATL_GUARDEDSTORAGE) 484 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 485 486 /* Stack in dcache: cacheable, no memory coherence */ 487 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) 488 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 489 BATU_VS | BATU_VP) 490 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 491 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 492 493 /* 494 * Internal Definitions 495 * 496 * Boot Flags 497 */ 498 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 499 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 500 501 /* 502 * Environment Configuration 503 */ 504 505 #define CONFIG_ENV_OVERWRITE 506 507 #if defined(CONFIG_TSEC_ENET) 508 #define CONFIG_HAS_ETH0 509 #define CONFIG_HAS_ETH1 510 #endif 511 512 #define CONFIG_BAUDRATE 115200 513 514 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 515 516 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 517 518 #define xstr(s) str(s) 519 #define str(s) #s 520 521 #define CONFIG_EXTRA_ENV_SETTINGS \ 522 "netdev=eth0\0" \ 523 "consoledev=ttyS0\0" \ 524 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 525 "nfsroot=${serverip}:${rootpath}\0" \ 526 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 527 "addip=setenv bootargs ${bootargs} " \ 528 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 529 ":${hostname}:${netdev}:off panic=1\0" \ 530 "addtty=setenv bootargs ${bootargs}" \ 531 " console=${consoledev},${baudrate}\0" \ 532 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 533 "addmisc=setenv bootargs ${bootargs}\0" \ 534 "kernel_addr=FE080000\0" \ 535 "fdt_addr=FE280000\0" \ 536 "ramdisk_addr=FE290000\0" \ 537 "u-boot=mpc8308rdb/u-boot.bin\0" \ 538 "kernel_addr_r=1000000\0" \ 539 "fdt_addr_r=C00000\0" \ 540 "hostname=mpc8308rdb\0" \ 541 "bootfile=mpc8308rdb/uImage\0" \ 542 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ 543 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 544 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 545 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 546 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 547 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 548 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 549 "tftp ${fdt_addr_r} ${fdtfile};" \ 550 "run nfsargs addip addtty addmtd addmisc;" \ 551 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 552 "bootcmd=run flash_self\0" \ 553 "load=tftp ${loadaddr} ${u-boot}\0" \ 554 "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \ 555 " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \ 556 " +${filesize};cp.b ${fileaddr} " \ 557 xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 558 "upd=run load update\0" \ 559 560 #endif /* __CONFIG_H */ 561