1*5fb17030SIlya Yanok /* 2*5fb17030SIlya Yanok * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 3*5fb17030SIlya Yanok * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 4*5fb17030SIlya Yanok * 5*5fb17030SIlya Yanok * 6*5fb17030SIlya Yanok * See file CREDITS for list of people who contributed to this 7*5fb17030SIlya Yanok * project. 8*5fb17030SIlya Yanok * 9*5fb17030SIlya Yanok * This program is free software; you can redistribute it and/or 10*5fb17030SIlya Yanok * modify it under the terms of the GNU General Public License as 11*5fb17030SIlya Yanok * published by the Free Software Foundation; either version 2 of 12*5fb17030SIlya Yanok * the License, or (at your option) any later version. 13*5fb17030SIlya Yanok * 14*5fb17030SIlya Yanok * This program is distributed in the hope that it will be useful, 15*5fb17030SIlya Yanok * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*5fb17030SIlya Yanok * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*5fb17030SIlya Yanok * GNU General Public License for more details. 18*5fb17030SIlya Yanok * 19*5fb17030SIlya Yanok * You should have received a copy of the GNU General Public License 20*5fb17030SIlya Yanok * along with this program; if not, write to the Free Software 21*5fb17030SIlya Yanok * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22*5fb17030SIlya Yanok * MA 02111-1307 USA 23*5fb17030SIlya Yanok */ 24*5fb17030SIlya Yanok 25*5fb17030SIlya Yanok #ifndef __CONFIG_H 26*5fb17030SIlya Yanok #define __CONFIG_H 27*5fb17030SIlya Yanok 28*5fb17030SIlya Yanok /* 29*5fb17030SIlya Yanok * High Level Configuration Options 30*5fb17030SIlya Yanok */ 31*5fb17030SIlya Yanok #define CONFIG_E300 1 /* E300 family */ 32*5fb17030SIlya Yanok #define CONFIG_MPC83xx 1 /* MPC83xx family */ 33*5fb17030SIlya Yanok #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 34*5fb17030SIlya Yanok #define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ 35*5fb17030SIlya Yanok 36*5fb17030SIlya Yanok #define CONFIG_MISC_INIT_R 37*5fb17030SIlya Yanok 38*5fb17030SIlya Yanok /* 39*5fb17030SIlya Yanok * On-board devices 40*5fb17030SIlya Yanok * 41*5fb17030SIlya Yanok * TSEC1 is SoC TSEC 42*5fb17030SIlya Yanok * TSEC2 is VSC switch 43*5fb17030SIlya Yanok */ 44*5fb17030SIlya Yanok #define CONFIG_TSEC1 45*5fb17030SIlya Yanok #define CONFIG_VSC7385_ENET 46*5fb17030SIlya Yanok 47*5fb17030SIlya Yanok /* 48*5fb17030SIlya Yanok * System Clock Setup 49*5fb17030SIlya Yanok */ 50*5fb17030SIlya Yanok #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 51*5fb17030SIlya Yanok #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 52*5fb17030SIlya Yanok 53*5fb17030SIlya Yanok /* 54*5fb17030SIlya Yanok * Hardware Reset Configuration Word 55*5fb17030SIlya Yanok * if CLKIN is 66.66MHz, then 56*5fb17030SIlya Yanok * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 57*5fb17030SIlya Yanok * We choose the A type silicon as default, so the core is 400Mhz. 58*5fb17030SIlya Yanok */ 59*5fb17030SIlya Yanok #define CONFIG_SYS_HRCW_LOW (\ 60*5fb17030SIlya Yanok HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 61*5fb17030SIlya Yanok HRCWL_DDR_TO_SCB_CLK_2X1 |\ 62*5fb17030SIlya Yanok HRCWL_SVCOD_DIV_2 |\ 63*5fb17030SIlya Yanok HRCWL_CSB_TO_CLKIN_4X1 |\ 64*5fb17030SIlya Yanok HRCWL_CORE_TO_CSB_3X1) 65*5fb17030SIlya Yanok /* 66*5fb17030SIlya Yanok * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 67*5fb17030SIlya Yanok * in 8308's HRCWH according to the manual, but original Freescale's 68*5fb17030SIlya Yanok * code has them and I've expirienced some problems using the board 69*5fb17030SIlya Yanok * with BDI3000 attached when I've tried to set these bits to zero 70*5fb17030SIlya Yanok * (UART doesn't work after the 'reset run' command). 71*5fb17030SIlya Yanok */ 72*5fb17030SIlya Yanok #define CONFIG_SYS_HRCW_HIGH (\ 73*5fb17030SIlya Yanok HRCWH_PCI_HOST |\ 74*5fb17030SIlya Yanok HRCWH_PCI1_ARBITER_ENABLE |\ 75*5fb17030SIlya Yanok HRCWH_CORE_ENABLE |\ 76*5fb17030SIlya Yanok HRCWH_FROM_0X00000100 |\ 77*5fb17030SIlya Yanok HRCWH_BOOTSEQ_DISABLE |\ 78*5fb17030SIlya Yanok HRCWH_SW_WATCHDOG_DISABLE |\ 79*5fb17030SIlya Yanok HRCWH_ROM_LOC_LOCAL_16BIT |\ 80*5fb17030SIlya Yanok HRCWH_RL_EXT_LEGACY |\ 81*5fb17030SIlya Yanok HRCWH_TSEC1M_IN_RGMII |\ 82*5fb17030SIlya Yanok HRCWH_TSEC2M_IN_RGMII |\ 83*5fb17030SIlya Yanok HRCWH_BIG_ENDIAN) 84*5fb17030SIlya Yanok 85*5fb17030SIlya Yanok /* 86*5fb17030SIlya Yanok * System IO Config 87*5fb17030SIlya Yanok */ 88*5fb17030SIlya Yanok #define CONFIG_SYS_SICRH 0x01b7d103 89*5fb17030SIlya Yanok #define CONFIG_SYS_SICRL 0x00000040 /* 3.3V, no delay */ 90*5fb17030SIlya Yanok 91*5fb17030SIlya Yanok #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 92*5fb17030SIlya Yanok 93*5fb17030SIlya Yanok /* 94*5fb17030SIlya Yanok * IMMR new address 95*5fb17030SIlya Yanok */ 96*5fb17030SIlya Yanok #define CONFIG_SYS_IMMR 0xE0000000 97*5fb17030SIlya Yanok 98*5fb17030SIlya Yanok /* 99*5fb17030SIlya Yanok * SERDES 100*5fb17030SIlya Yanok */ 101*5fb17030SIlya Yanok #define CONFIG_FSL_SERDES 102*5fb17030SIlya Yanok #define CONFIG_FSL_SERDES1 0xe3000 103*5fb17030SIlya Yanok 104*5fb17030SIlya Yanok /* 105*5fb17030SIlya Yanok * Arbiter Setup 106*5fb17030SIlya Yanok */ 107*5fb17030SIlya Yanok #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 108*5fb17030SIlya Yanok #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 109*5fb17030SIlya Yanok #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 110*5fb17030SIlya Yanok 111*5fb17030SIlya Yanok /* 112*5fb17030SIlya Yanok * DDR Setup 113*5fb17030SIlya Yanok */ 114*5fb17030SIlya Yanok #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 115*5fb17030SIlya Yanok #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 116*5fb17030SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 117*5fb17030SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 118*5fb17030SIlya Yanok #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 119*5fb17030SIlya Yanok | DDRCDR_PZ_LOZ \ 120*5fb17030SIlya Yanok | DDRCDR_NZ_LOZ \ 121*5fb17030SIlya Yanok | DDRCDR_ODT \ 122*5fb17030SIlya Yanok | DDRCDR_Q_DRN) 123*5fb17030SIlya Yanok /* 0x7b880001 */ 124*5fb17030SIlya Yanok /* 125*5fb17030SIlya Yanok * Manually set up DDR parameters 126*5fb17030SIlya Yanok * consist of two chips HY5PS12621BFP-C4 from HYNIX 127*5fb17030SIlya Yanok */ 128*5fb17030SIlya Yanok 129*5fb17030SIlya Yanok #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 130*5fb17030SIlya Yanok 131*5fb17030SIlya Yanok #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 132*5fb17030SIlya Yanok #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 133*5fb17030SIlya Yanok | 0x00010000 /* ODT_WR to CSn */ \ 134*5fb17030SIlya Yanok | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 135*5fb17030SIlya Yanok /* 0x80010102 */ 136*5fb17030SIlya Yanok #define CONFIG_SYS_DDR_TIMING_3 0x00000000 137*5fb17030SIlya Yanok #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 138*5fb17030SIlya Yanok | (0 << TIMING_CFG0_WRT_SHIFT) \ 139*5fb17030SIlya Yanok | (0 << TIMING_CFG0_RRT_SHIFT) \ 140*5fb17030SIlya Yanok | (0 << TIMING_CFG0_WWT_SHIFT) \ 141*5fb17030SIlya Yanok | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 142*5fb17030SIlya Yanok | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 143*5fb17030SIlya Yanok | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 144*5fb17030SIlya Yanok | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 145*5fb17030SIlya Yanok /* 0x00220802 */ 146*5fb17030SIlya Yanok #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 147*5fb17030SIlya Yanok | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 148*5fb17030SIlya Yanok | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 149*5fb17030SIlya Yanok | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 150*5fb17030SIlya Yanok | (6 << TIMING_CFG1_REFREC_SHIFT) \ 151*5fb17030SIlya Yanok | (2 << TIMING_CFG1_WRREC_SHIFT) \ 152*5fb17030SIlya Yanok | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 153*5fb17030SIlya Yanok | (2 << TIMING_CFG1_WRTORD_SHIFT)) 154*5fb17030SIlya Yanok /* 0x27256222 */ 155*5fb17030SIlya Yanok #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 156*5fb17030SIlya Yanok | (4 << TIMING_CFG2_CPO_SHIFT) \ 157*5fb17030SIlya Yanok | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 158*5fb17030SIlya Yanok | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 159*5fb17030SIlya Yanok | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 160*5fb17030SIlya Yanok | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 161*5fb17030SIlya Yanok | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 162*5fb17030SIlya Yanok /* 0x121048c5 */ 163*5fb17030SIlya Yanok #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 164*5fb17030SIlya Yanok | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 165*5fb17030SIlya Yanok /* 0x03600100 */ 166*5fb17030SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 167*5fb17030SIlya Yanok | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 168*5fb17030SIlya Yanok | SDRAM_CFG_32_BE) 169*5fb17030SIlya Yanok /* 0x43080000 */ 170*5fb17030SIlya Yanok 171*5fb17030SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 172*5fb17030SIlya Yanok #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 173*5fb17030SIlya Yanok | (0x0232 << SDRAM_MODE_SD_SHIFT)) 174*5fb17030SIlya Yanok /* ODT 150ohm CL=3, AL=1 on SDRAM */ 175*5fb17030SIlya Yanok #define CONFIG_SYS_DDR_MODE2 0x00000000 176*5fb17030SIlya Yanok 177*5fb17030SIlya Yanok /* 178*5fb17030SIlya Yanok * Memory test 179*5fb17030SIlya Yanok */ 180*5fb17030SIlya Yanok #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 181*5fb17030SIlya Yanok #define CONFIG_SYS_MEMTEST_END 0x07f00000 182*5fb17030SIlya Yanok 183*5fb17030SIlya Yanok /* 184*5fb17030SIlya Yanok * The reserved memory 185*5fb17030SIlya Yanok */ 186*5fb17030SIlya Yanok #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 187*5fb17030SIlya Yanok 188*5fb17030SIlya Yanok #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 189*5fb17030SIlya Yanok #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 190*5fb17030SIlya Yanok 191*5fb17030SIlya Yanok /* 192*5fb17030SIlya Yanok * Initial RAM Base Address Setup 193*5fb17030SIlya Yanok */ 194*5fb17030SIlya Yanok #define CONFIG_SYS_INIT_RAM_LOCK 1 195*5fb17030SIlya Yanok #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 196*5fb17030SIlya Yanok #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ 197*5fb17030SIlya Yanok #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 198*5fb17030SIlya Yanok #define CONFIG_SYS_GBL_DATA_OFFSET \ 199*5fb17030SIlya Yanok (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 200*5fb17030SIlya Yanok 201*5fb17030SIlya Yanok /* 202*5fb17030SIlya Yanok * Local Bus Configuration & Clock Setup 203*5fb17030SIlya Yanok */ 204*5fb17030SIlya Yanok #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 205*5fb17030SIlya Yanok #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 206*5fb17030SIlya Yanok #define CONFIG_SYS_LBC_LBCR 0x00040000 207*5fb17030SIlya Yanok 208*5fb17030SIlya Yanok /* 209*5fb17030SIlya Yanok * FLASH on the Local Bus 210*5fb17030SIlya Yanok */ 211*5fb17030SIlya Yanok #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 212*5fb17030SIlya Yanok #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 213*5fb17030SIlya Yanok #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 214*5fb17030SIlya Yanok 215*5fb17030SIlya Yanok #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 216*5fb17030SIlya Yanok #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 217*5fb17030SIlya Yanok #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 218*5fb17030SIlya Yanok 219*5fb17030SIlya Yanok /* Window base at flash base */ 220*5fb17030SIlya Yanok #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 221*5fb17030SIlya Yanok #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ 222*5fb17030SIlya Yanok 223*5fb17030SIlya Yanok #define CONFIG_SYS_BR0_PRELIM (\ 224*5fb17030SIlya Yanok CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\ 225*5fb17030SIlya Yanok (2 << BR_PS_SHIFT) /* 16 bit port size */ |\ 226*5fb17030SIlya Yanok BR_V) /* valid */ 227*5fb17030SIlya Yanok #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ 228*5fb17030SIlya Yanok | OR_UPM_XAM \ 229*5fb17030SIlya Yanok | OR_GPCM_CSNT \ 230*5fb17030SIlya Yanok | OR_GPCM_ACS_DIV2 \ 231*5fb17030SIlya Yanok | OR_GPCM_XACS \ 232*5fb17030SIlya Yanok | OR_GPCM_SCY_15 \ 233*5fb17030SIlya Yanok | OR_GPCM_TRLX \ 234*5fb17030SIlya Yanok | OR_GPCM_EHTR \ 235*5fb17030SIlya Yanok | OR_GPCM_EAD) 236*5fb17030SIlya Yanok 237*5fb17030SIlya Yanok #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 238*5fb17030SIlya Yanok /* 127 64KB sectors and 8 8KB top sectors per device */ 239*5fb17030SIlya Yanok #define CONFIG_SYS_MAX_FLASH_SECT 135 240*5fb17030SIlya Yanok 241*5fb17030SIlya Yanok #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 242*5fb17030SIlya Yanok #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 243*5fb17030SIlya Yanok 244*5fb17030SIlya Yanok /* 245*5fb17030SIlya Yanok * NAND Flash on the Local Bus 246*5fb17030SIlya Yanok */ 247*5fb17030SIlya Yanok #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 248*5fb17030SIlya Yanok #define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ 249*5fb17030SIlya Yanok | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 250*5fb17030SIlya Yanok | BR_PS_8 /* Port Size = 8 bit */ \ 251*5fb17030SIlya Yanok | BR_MS_FCM /* MSEL = FCM */ \ 252*5fb17030SIlya Yanok | BR_V ) /* valid */ 253*5fb17030SIlya Yanok #define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ 254*5fb17030SIlya Yanok | OR_FCM_CSCT \ 255*5fb17030SIlya Yanok | OR_FCM_CST \ 256*5fb17030SIlya Yanok | OR_FCM_CHT \ 257*5fb17030SIlya Yanok | OR_FCM_SCY_1 \ 258*5fb17030SIlya Yanok | OR_FCM_TRLX \ 259*5fb17030SIlya Yanok | OR_FCM_EHTR ) 260*5fb17030SIlya Yanok /* 0xFFFF8396 */ 261*5fb17030SIlya Yanok 262*5fb17030SIlya Yanok #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 263*5fb17030SIlya Yanok #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 264*5fb17030SIlya Yanok 265*5fb17030SIlya Yanok #ifdef CONFIG_VSC7385_ENET 266*5fb17030SIlya Yanok #define CONFIG_TSEC2 267*5fb17030SIlya Yanok #define CONFIG_SYS_VSC7385_BASE 0xF0000000 268*5fb17030SIlya Yanok #define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ 269*5fb17030SIlya Yanok #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ 270*5fb17030SIlya Yanok /* Access window base at VSC7385 base */ 271*5fb17030SIlya Yanok #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 272*5fb17030SIlya Yanok /* Access window size 128K */ 273*5fb17030SIlya Yanok #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 274*5fb17030SIlya Yanok /* The flash address and size of the VSC7385 firmware image */ 275*5fb17030SIlya Yanok #define CONFIG_VSC7385_IMAGE 0xFE7FE000 276*5fb17030SIlya Yanok #define CONFIG_VSC7385_IMAGE_SIZE 8192 277*5fb17030SIlya Yanok #endif 278*5fb17030SIlya Yanok /* 279*5fb17030SIlya Yanok * Serial Port 280*5fb17030SIlya Yanok */ 281*5fb17030SIlya Yanok #define CONFIG_CONS_INDEX 1 282*5fb17030SIlya Yanok #undef CONFIG_SERIAL_SOFTWARE_FIFO 283*5fb17030SIlya Yanok #define CONFIG_SYS_NS16550 284*5fb17030SIlya Yanok #define CONFIG_SYS_NS16550_SERIAL 285*5fb17030SIlya Yanok #define CONFIG_SYS_NS16550_REG_SIZE 1 286*5fb17030SIlya Yanok #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 287*5fb17030SIlya Yanok 288*5fb17030SIlya Yanok #define CONFIG_SYS_BAUDRATE_TABLE \ 289*5fb17030SIlya Yanok {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 290*5fb17030SIlya Yanok 291*5fb17030SIlya Yanok #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 292*5fb17030SIlya Yanok #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 293*5fb17030SIlya Yanok 294*5fb17030SIlya Yanok /* Use the HUSH parser */ 295*5fb17030SIlya Yanok #define CONFIG_SYS_HUSH_PARSER 296*5fb17030SIlya Yanok #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 297*5fb17030SIlya Yanok 298*5fb17030SIlya Yanok /* Pass open firmware flat tree */ 299*5fb17030SIlya Yanok #define CONFIG_OF_LIBFDT 1 300*5fb17030SIlya Yanok #define CONFIG_OF_BOARD_SETUP 1 301*5fb17030SIlya Yanok #define CONFIG_OF_STDOUT_VIA_ALIAS 1 302*5fb17030SIlya Yanok 303*5fb17030SIlya Yanok /* I2C */ 304*5fb17030SIlya Yanok #define CONFIG_HARD_I2C /* I2C with hardware support */ 305*5fb17030SIlya Yanok #define CONFIG_FSL_I2C 306*5fb17030SIlya Yanok #define CONFIG_I2C_MULTI_BUS 307*5fb17030SIlya Yanok #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 308*5fb17030SIlya Yanok #define CONFIG_SYS_I2C_SLAVE 0x7F 309*5fb17030SIlya Yanok #define CONFIG_SYS_I2C_NOPROBES {{0x51}} /* Don't probe these addrs */ 310*5fb17030SIlya Yanok #define CONFIG_SYS_I2C_OFFSET 0x3000 311*5fb17030SIlya Yanok #define CONFIG_SYS_I2C2_OFFSET 0x3100 312*5fb17030SIlya Yanok 313*5fb17030SIlya Yanok 314*5fb17030SIlya Yanok /* 315*5fb17030SIlya Yanok * Board info - revision and where boot from 316*5fb17030SIlya Yanok */ 317*5fb17030SIlya Yanok #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 318*5fb17030SIlya Yanok 319*5fb17030SIlya Yanok /* 320*5fb17030SIlya Yanok * Config on-board RTC 321*5fb17030SIlya Yanok */ 322*5fb17030SIlya Yanok #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 323*5fb17030SIlya Yanok #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 324*5fb17030SIlya Yanok 325*5fb17030SIlya Yanok /* 326*5fb17030SIlya Yanok * General PCI 327*5fb17030SIlya Yanok * Addresses are mapped 1-1. 328*5fb17030SIlya Yanok */ 329*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_BASE 0xA0000000 330*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 331*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 332*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 333*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 334*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 335*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 336*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 337*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 338*5fb17030SIlya Yanok 339*5fb17030SIlya Yanok /* 340*5fb17030SIlya Yanok * Fake PCIE2 definitions: there is no PCIE2 on this board but the code 341*5fb17030SIlya Yanok * in arch/powerpc/cpu/mpc83xx/pcie.c doesn't compile without this 342*5fb17030SIlya Yanok */ 343*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE2_BASE 0xC0000000 344*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 345*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 346*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 347*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 348*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 349*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 350*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 351*5fb17030SIlya Yanok #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 352*5fb17030SIlya Yanok 353*5fb17030SIlya Yanok #define CONFIG_PCI 354*5fb17030SIlya Yanok #define CONFIG_PCIE 355*5fb17030SIlya Yanok 356*5fb17030SIlya Yanok #define CONFIG_PCI_PNP /* do pci plug-and-play */ 357*5fb17030SIlya Yanok 358*5fb17030SIlya Yanok #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 359*5fb17030SIlya Yanok #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 360*5fb17030SIlya Yanok 361*5fb17030SIlya Yanok /* 362*5fb17030SIlya Yanok * TSEC 363*5fb17030SIlya Yanok */ 364*5fb17030SIlya Yanok #define CONFIG_NET_MULTI 365*5fb17030SIlya Yanok #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 366*5fb17030SIlya Yanok #define CONFIG_SYS_TSEC1_OFFSET 0x24000 367*5fb17030SIlya Yanok #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 368*5fb17030SIlya Yanok #define CONFIG_SYS_TSEC2_OFFSET 0x25000 369*5fb17030SIlya Yanok #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 370*5fb17030SIlya Yanok 371*5fb17030SIlya Yanok /* 372*5fb17030SIlya Yanok * TSEC ethernet configuration 373*5fb17030SIlya Yanok */ 374*5fb17030SIlya Yanok #define CONFIG_MII 1 /* MII PHY management */ 375*5fb17030SIlya Yanok #define CONFIG_TSEC1_NAME "eTSEC0" 376*5fb17030SIlya Yanok #define CONFIG_TSEC2_NAME "eTSEC1" 377*5fb17030SIlya Yanok #define TSEC1_PHY_ADDR 2 378*5fb17030SIlya Yanok #define TSEC2_PHY_ADDR 1 379*5fb17030SIlya Yanok #define TSEC1_PHYIDX 0 380*5fb17030SIlya Yanok #define TSEC2_PHYIDX 0 381*5fb17030SIlya Yanok #define TSEC1_FLAGS TSEC_GIGABIT 382*5fb17030SIlya Yanok #define TSEC2_FLAGS TSEC_GIGABIT 383*5fb17030SIlya Yanok 384*5fb17030SIlya Yanok /* Options are: eTSEC[0-1] */ 385*5fb17030SIlya Yanok #define CONFIG_ETHPRIME "eTSEC0" 386*5fb17030SIlya Yanok 387*5fb17030SIlya Yanok /* 388*5fb17030SIlya Yanok * Environment 389*5fb17030SIlya Yanok */ 390*5fb17030SIlya Yanok #define CONFIG_ENV_IS_IN_FLASH 1 391*5fb17030SIlya Yanok #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 392*5fb17030SIlya Yanok CONFIG_SYS_MONITOR_LEN) 393*5fb17030SIlya Yanok #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 394*5fb17030SIlya Yanok #define CONFIG_ENV_SIZE 0x2000 395*5fb17030SIlya Yanok #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 396*5fb17030SIlya Yanok #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 397*5fb17030SIlya Yanok 398*5fb17030SIlya Yanok #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 399*5fb17030SIlya Yanok #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 400*5fb17030SIlya Yanok 401*5fb17030SIlya Yanok /* 402*5fb17030SIlya Yanok * BOOTP options 403*5fb17030SIlya Yanok */ 404*5fb17030SIlya Yanok #define CONFIG_BOOTP_BOOTFILESIZE 405*5fb17030SIlya Yanok #define CONFIG_BOOTP_BOOTPATH 406*5fb17030SIlya Yanok #define CONFIG_BOOTP_GATEWAY 407*5fb17030SIlya Yanok #define CONFIG_BOOTP_HOSTNAME 408*5fb17030SIlya Yanok 409*5fb17030SIlya Yanok /* 410*5fb17030SIlya Yanok * Command line configuration. 411*5fb17030SIlya Yanok */ 412*5fb17030SIlya Yanok #include <config_cmd_default.h> 413*5fb17030SIlya Yanok 414*5fb17030SIlya Yanok #define CONFIG_CMD_DATE 415*5fb17030SIlya Yanok #define CONFIG_CMD_DHCP 416*5fb17030SIlya Yanok #define CONFIG_CMD_I2C 417*5fb17030SIlya Yanok #define CONFIG_CMD_MII 418*5fb17030SIlya Yanok #define CONFIG_CMD_NET 419*5fb17030SIlya Yanok #define CONFIG_CMD_PCI 420*5fb17030SIlya Yanok #define CONFIG_CMD_PING 421*5fb17030SIlya Yanok 422*5fb17030SIlya Yanok #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 423*5fb17030SIlya Yanok 424*5fb17030SIlya Yanok /* 425*5fb17030SIlya Yanok * Miscellaneous configurable options 426*5fb17030SIlya Yanok */ 427*5fb17030SIlya Yanok #define CONFIG_SYS_LONGHELP /* undef to save memory */ 428*5fb17030SIlya Yanok #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 429*5fb17030SIlya Yanok #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 430*5fb17030SIlya Yanok 431*5fb17030SIlya Yanok #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 432*5fb17030SIlya Yanok 433*5fb17030SIlya Yanok /* Print Buffer Size */ 434*5fb17030SIlya Yanok #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 435*5fb17030SIlya Yanok #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 436*5fb17030SIlya Yanok /* Boot Argument Buffer Size */ 437*5fb17030SIlya Yanok #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 438*5fb17030SIlya Yanok #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 439*5fb17030SIlya Yanok 440*5fb17030SIlya Yanok /* 441*5fb17030SIlya Yanok * For booting Linux, the board info and command line data 442*5fb17030SIlya Yanok * have to be in the first 8 MB of memory, since this is 443*5fb17030SIlya Yanok * the maximum mapped by the Linux kernel during initialization. 444*5fb17030SIlya Yanok */ 445*5fb17030SIlya Yanok #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 446*5fb17030SIlya Yanok 447*5fb17030SIlya Yanok /* 448*5fb17030SIlya Yanok * Core HID Setup 449*5fb17030SIlya Yanok */ 450*5fb17030SIlya Yanok #define CONFIG_SYS_HID0_INIT 0x000000000 451*5fb17030SIlya Yanok #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 452*5fb17030SIlya Yanok HID0_ENABLE_INSTRUCTION_CACHE | \ 453*5fb17030SIlya Yanok HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 454*5fb17030SIlya Yanok #define CONFIG_SYS_HID2 HID2_HBE 455*5fb17030SIlya Yanok 456*5fb17030SIlya Yanok /* 457*5fb17030SIlya Yanok * MMU Setup 458*5fb17030SIlya Yanok */ 459*5fb17030SIlya Yanok 460*5fb17030SIlya Yanok /* DDR: cache cacheable */ 461*5fb17030SIlya Yanok #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ 462*5fb17030SIlya Yanok BATL_MEMCOHERENCE) 463*5fb17030SIlya Yanok #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 464*5fb17030SIlya Yanok BATU_VS | BATU_VP) 465*5fb17030SIlya Yanok #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 466*5fb17030SIlya Yanok #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 467*5fb17030SIlya Yanok 468*5fb17030SIlya Yanok /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 469*5fb17030SIlya Yanok #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ 470*5fb17030SIlya Yanok BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 471*5fb17030SIlya Yanok #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 472*5fb17030SIlya Yanok BATU_VP) 473*5fb17030SIlya Yanok #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 474*5fb17030SIlya Yanok #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 475*5fb17030SIlya Yanok 476*5fb17030SIlya Yanok /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 477*5fb17030SIlya Yanok #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ 478*5fb17030SIlya Yanok BATL_MEMCOHERENCE) 479*5fb17030SIlya Yanok #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 480*5fb17030SIlya Yanok BATU_VS | BATU_VP) 481*5fb17030SIlya Yanok #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ 482*5fb17030SIlya Yanok BATL_CACHEINHIBIT | \ 483*5fb17030SIlya Yanok BATL_GUARDEDSTORAGE) 484*5fb17030SIlya Yanok #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 485*5fb17030SIlya Yanok 486*5fb17030SIlya Yanok /* Stack in dcache: cacheable, no memory coherence */ 487*5fb17030SIlya Yanok #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) 488*5fb17030SIlya Yanok #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 489*5fb17030SIlya Yanok BATU_VS | BATU_VP) 490*5fb17030SIlya Yanok #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 491*5fb17030SIlya Yanok #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 492*5fb17030SIlya Yanok 493*5fb17030SIlya Yanok /* 494*5fb17030SIlya Yanok * Internal Definitions 495*5fb17030SIlya Yanok * 496*5fb17030SIlya Yanok * Boot Flags 497*5fb17030SIlya Yanok */ 498*5fb17030SIlya Yanok #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 499*5fb17030SIlya Yanok #define BOOTFLAG_WARM 0x02 /* Software reboot */ 500*5fb17030SIlya Yanok 501*5fb17030SIlya Yanok /* 502*5fb17030SIlya Yanok * Environment Configuration 503*5fb17030SIlya Yanok */ 504*5fb17030SIlya Yanok 505*5fb17030SIlya Yanok #define CONFIG_ENV_OVERWRITE 506*5fb17030SIlya Yanok 507*5fb17030SIlya Yanok #if defined(CONFIG_TSEC_ENET) 508*5fb17030SIlya Yanok #define CONFIG_HAS_ETH0 509*5fb17030SIlya Yanok #define CONFIG_HAS_ETH1 510*5fb17030SIlya Yanok #endif 511*5fb17030SIlya Yanok 512*5fb17030SIlya Yanok #define CONFIG_BAUDRATE 115200 513*5fb17030SIlya Yanok 514*5fb17030SIlya Yanok #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 515*5fb17030SIlya Yanok 516*5fb17030SIlya Yanok #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 517*5fb17030SIlya Yanok 518*5fb17030SIlya Yanok #define xstr(s) str(s) 519*5fb17030SIlya Yanok #define str(s) #s 520*5fb17030SIlya Yanok 521*5fb17030SIlya Yanok #define CONFIG_EXTRA_ENV_SETTINGS \ 522*5fb17030SIlya Yanok "netdev=eth0\0" \ 523*5fb17030SIlya Yanok "consoledev=ttyS0\0" \ 524*5fb17030SIlya Yanok "nfsargs=setenv bootargs root=/dev/nfs rw " \ 525*5fb17030SIlya Yanok "nfsroot=${serverip}:${rootpath}\0" \ 526*5fb17030SIlya Yanok "ramargs=setenv bootargs root=/dev/ram rw\0" \ 527*5fb17030SIlya Yanok "addip=setenv bootargs ${bootargs} " \ 528*5fb17030SIlya Yanok "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 529*5fb17030SIlya Yanok ":${hostname}:${netdev}:off panic=1\0" \ 530*5fb17030SIlya Yanok "addtty=setenv bootargs ${bootargs}" \ 531*5fb17030SIlya Yanok " console=${consoledev},${baudrate}\0" \ 532*5fb17030SIlya Yanok "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 533*5fb17030SIlya Yanok "addmisc=setenv bootargs ${bootargs}\0" \ 534*5fb17030SIlya Yanok "kernel_addr=FE080000\0" \ 535*5fb17030SIlya Yanok "fdt_addr=FE280000\0" \ 536*5fb17030SIlya Yanok "ramdisk_addr=FE290000\0" \ 537*5fb17030SIlya Yanok "u-boot=mpc8308rdb/u-boot.bin\0" \ 538*5fb17030SIlya Yanok "kernel_addr_r=1000000\0" \ 539*5fb17030SIlya Yanok "fdt_addr_r=C00000\0" \ 540*5fb17030SIlya Yanok "hostname=mpc8308rdb\0" \ 541*5fb17030SIlya Yanok "bootfile=mpc8308rdb/uImage\0" \ 542*5fb17030SIlya Yanok "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ 543*5fb17030SIlya Yanok "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 544*5fb17030SIlya Yanok "flash_self=run ramargs addip addtty addmtd addmisc;" \ 545*5fb17030SIlya Yanok "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 546*5fb17030SIlya Yanok "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 547*5fb17030SIlya Yanok "bootm ${kernel_addr} - ${fdt_addr}\0" \ 548*5fb17030SIlya Yanok "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 549*5fb17030SIlya Yanok "tftp ${fdt_addr_r} ${fdtfile};" \ 550*5fb17030SIlya Yanok "run nfsargs addip addtty addmtd addmisc;" \ 551*5fb17030SIlya Yanok "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 552*5fb17030SIlya Yanok "bootcmd=run flash_self\0" \ 553*5fb17030SIlya Yanok "load=tftp ${loadaddr} ${u-boot}\0" \ 554*5fb17030SIlya Yanok "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \ 555*5fb17030SIlya Yanok " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \ 556*5fb17030SIlya Yanok " +${filesize};cp.b ${fileaddr} " \ 557*5fb17030SIlya Yanok xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 558*5fb17030SIlya Yanok "upd=run load update\0" \ 559*5fb17030SIlya Yanok 560*5fb17030SIlya Yanok #endif /* __CONFIG_H */ 561