15fb17030SIlya Yanok /* 25fb17030SIlya Yanok * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 35fb17030SIlya Yanok * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 45fb17030SIlya Yanok * 55fb17030SIlya Yanok * 65fb17030SIlya Yanok * See file CREDITS for list of people who contributed to this 75fb17030SIlya Yanok * project. 85fb17030SIlya Yanok * 95fb17030SIlya Yanok * This program is free software; you can redistribute it and/or 105fb17030SIlya Yanok * modify it under the terms of the GNU General Public License as 115fb17030SIlya Yanok * published by the Free Software Foundation; either version 2 of 125fb17030SIlya Yanok * the License, or (at your option) any later version. 135fb17030SIlya Yanok * 145fb17030SIlya Yanok * This program is distributed in the hope that it will be useful, 155fb17030SIlya Yanok * but WITHOUT ANY WARRANTY; without even the implied warranty of 165fb17030SIlya Yanok * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 175fb17030SIlya Yanok * GNU General Public License for more details. 185fb17030SIlya Yanok * 195fb17030SIlya Yanok * You should have received a copy of the GNU General Public License 205fb17030SIlya Yanok * along with this program; if not, write to the Free Software 215fb17030SIlya Yanok * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 225fb17030SIlya Yanok * MA 02111-1307 USA 235fb17030SIlya Yanok */ 245fb17030SIlya Yanok 255fb17030SIlya Yanok #ifndef __CONFIG_H 265fb17030SIlya Yanok #define __CONFIG_H 275fb17030SIlya Yanok 285fb17030SIlya Yanok /* 295fb17030SIlya Yanok * High Level Configuration Options 305fb17030SIlya Yanok */ 315fb17030SIlya Yanok #define CONFIG_E300 1 /* E300 family */ 325fb17030SIlya Yanok #define CONFIG_MPC83xx 1 /* MPC83xx family */ 335fb17030SIlya Yanok #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 345fb17030SIlya Yanok #define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ 355fb17030SIlya Yanok 362ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFE000000 372ae18241SWolfgang Denk 385fb17030SIlya Yanok #define CONFIG_MISC_INIT_R 395fb17030SIlya Yanok 405fb17030SIlya Yanok /* 415fb17030SIlya Yanok * On-board devices 425fb17030SIlya Yanok * 435fb17030SIlya Yanok * TSEC1 is SoC TSEC 445fb17030SIlya Yanok * TSEC2 is VSC switch 455fb17030SIlya Yanok */ 465fb17030SIlya Yanok #define CONFIG_TSEC1 475fb17030SIlya Yanok #define CONFIG_VSC7385_ENET 485fb17030SIlya Yanok 495fb17030SIlya Yanok /* 505fb17030SIlya Yanok * System Clock Setup 515fb17030SIlya Yanok */ 525fb17030SIlya Yanok #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 535fb17030SIlya Yanok #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 545fb17030SIlya Yanok 555fb17030SIlya Yanok /* 565fb17030SIlya Yanok * Hardware Reset Configuration Word 575fb17030SIlya Yanok * if CLKIN is 66.66MHz, then 585fb17030SIlya Yanok * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 595fb17030SIlya Yanok * We choose the A type silicon as default, so the core is 400Mhz. 605fb17030SIlya Yanok */ 615fb17030SIlya Yanok #define CONFIG_SYS_HRCW_LOW (\ 625fb17030SIlya Yanok HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 635fb17030SIlya Yanok HRCWL_DDR_TO_SCB_CLK_2X1 |\ 645fb17030SIlya Yanok HRCWL_SVCOD_DIV_2 |\ 655fb17030SIlya Yanok HRCWL_CSB_TO_CLKIN_4X1 |\ 665fb17030SIlya Yanok HRCWL_CORE_TO_CSB_3X1) 675fb17030SIlya Yanok /* 685fb17030SIlya Yanok * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 695fb17030SIlya Yanok * in 8308's HRCWH according to the manual, but original Freescale's 705fb17030SIlya Yanok * code has them and I've expirienced some problems using the board 715fb17030SIlya Yanok * with BDI3000 attached when I've tried to set these bits to zero 725fb17030SIlya Yanok * (UART doesn't work after the 'reset run' command). 735fb17030SIlya Yanok */ 745fb17030SIlya Yanok #define CONFIG_SYS_HRCW_HIGH (\ 755fb17030SIlya Yanok HRCWH_PCI_HOST |\ 765fb17030SIlya Yanok HRCWH_PCI1_ARBITER_ENABLE |\ 775fb17030SIlya Yanok HRCWH_CORE_ENABLE |\ 785fb17030SIlya Yanok HRCWH_FROM_0X00000100 |\ 795fb17030SIlya Yanok HRCWH_BOOTSEQ_DISABLE |\ 805fb17030SIlya Yanok HRCWH_SW_WATCHDOG_DISABLE |\ 815fb17030SIlya Yanok HRCWH_ROM_LOC_LOCAL_16BIT |\ 825fb17030SIlya Yanok HRCWH_RL_EXT_LEGACY |\ 835fb17030SIlya Yanok HRCWH_TSEC1M_IN_RGMII |\ 845fb17030SIlya Yanok HRCWH_TSEC2M_IN_RGMII |\ 855fb17030SIlya Yanok HRCWH_BIG_ENDIAN) 865fb17030SIlya Yanok 875fb17030SIlya Yanok /* 885fb17030SIlya Yanok * System IO Config 895fb17030SIlya Yanok */ 9065ea7589SIlya Yanok #define CONFIG_SYS_SICRH (\ 9165ea7589SIlya Yanok SICRH_ESDHC_A_SD |\ 9265ea7589SIlya Yanok SICRH_ESDHC_B_SD |\ 9365ea7589SIlya Yanok SICRH_ESDHC_C_SD |\ 9465ea7589SIlya Yanok SICRH_GPIO_A_TSEC2 |\ 9565ea7589SIlya Yanok SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ 9665ea7589SIlya Yanok SICRH_IEEE1588_A_GPIO |\ 9765ea7589SIlya Yanok SICRH_USB |\ 9865ea7589SIlya Yanok SICRH_GTM_GPIO |\ 9965ea7589SIlya Yanok SICRH_IEEE1588_B_GPIO |\ 10065ea7589SIlya Yanok SICRH_ETSEC2_CRS |\ 10165ea7589SIlya Yanok SICRH_GPIOSEL_1 |\ 10265ea7589SIlya Yanok SICRH_TMROBI_V3P3 |\ 10365ea7589SIlya Yanok SICRH_TSOBI1_V2P5 |\ 10465ea7589SIlya Yanok SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ 10565ea7589SIlya Yanok #define CONFIG_SYS_SICRL (\ 10665ea7589SIlya Yanok SICRL_SPI_PF0 |\ 10765ea7589SIlya Yanok SICRL_UART_PF0 |\ 10865ea7589SIlya Yanok SICRL_IRQ_PF0 |\ 10965ea7589SIlya Yanok SICRL_I2C2_PF0 |\ 11065ea7589SIlya Yanok SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ 1115fb17030SIlya Yanok 1125fb17030SIlya Yanok /* 1135fb17030SIlya Yanok * IMMR new address 1145fb17030SIlya Yanok */ 1155fb17030SIlya Yanok #define CONFIG_SYS_IMMR 0xE0000000 1165fb17030SIlya Yanok 1175fb17030SIlya Yanok /* 1185fb17030SIlya Yanok * SERDES 1195fb17030SIlya Yanok */ 1205fb17030SIlya Yanok #define CONFIG_FSL_SERDES 1215fb17030SIlya Yanok #define CONFIG_FSL_SERDES1 0xe3000 1225fb17030SIlya Yanok 1235fb17030SIlya Yanok /* 1245fb17030SIlya Yanok * Arbiter Setup 1255fb17030SIlya Yanok */ 1265fb17030SIlya Yanok #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 1275fb17030SIlya Yanok #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 1285fb17030SIlya Yanok #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 1295fb17030SIlya Yanok 1305fb17030SIlya Yanok /* 1315fb17030SIlya Yanok * DDR Setup 1325fb17030SIlya Yanok */ 1335fb17030SIlya Yanok #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 1345fb17030SIlya Yanok #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1355fb17030SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 1365fb17030SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 1375fb17030SIlya Yanok #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 1385fb17030SIlya Yanok | DDRCDR_PZ_LOZ \ 1395fb17030SIlya Yanok | DDRCDR_NZ_LOZ \ 1405fb17030SIlya Yanok | DDRCDR_ODT \ 1415fb17030SIlya Yanok | DDRCDR_Q_DRN) 1425fb17030SIlya Yanok /* 0x7b880001 */ 1435fb17030SIlya Yanok /* 1445fb17030SIlya Yanok * Manually set up DDR parameters 1455fb17030SIlya Yanok * consist of two chips HY5PS12621BFP-C4 from HYNIX 1465fb17030SIlya Yanok */ 1475fb17030SIlya Yanok 1485fb17030SIlya Yanok #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 1495fb17030SIlya Yanok 1505fb17030SIlya Yanok #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 1515fb17030SIlya Yanok #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 152*2fef4020SJoe Hershberger | CSCONFIG_ODT_RD_NEVER \ 153*2fef4020SJoe Hershberger | CSCONFIG_ODT_WR_ONLY_CURRENT \ 1545fb17030SIlya Yanok | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 1555fb17030SIlya Yanok /* 0x80010102 */ 1565fb17030SIlya Yanok #define CONFIG_SYS_DDR_TIMING_3 0x00000000 1575fb17030SIlya Yanok #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 1585fb17030SIlya Yanok | (0 << TIMING_CFG0_WRT_SHIFT) \ 1595fb17030SIlya Yanok | (0 << TIMING_CFG0_RRT_SHIFT) \ 1605fb17030SIlya Yanok | (0 << TIMING_CFG0_WWT_SHIFT) \ 1615fb17030SIlya Yanok | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 1625fb17030SIlya Yanok | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 1635fb17030SIlya Yanok | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 1645fb17030SIlya Yanok | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 1655fb17030SIlya Yanok /* 0x00220802 */ 1665fb17030SIlya Yanok #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 1675fb17030SIlya Yanok | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 1685fb17030SIlya Yanok | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 1695fb17030SIlya Yanok | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 1705fb17030SIlya Yanok | (6 << TIMING_CFG1_REFREC_SHIFT) \ 1715fb17030SIlya Yanok | (2 << TIMING_CFG1_WRREC_SHIFT) \ 1725fb17030SIlya Yanok | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 1735fb17030SIlya Yanok | (2 << TIMING_CFG1_WRTORD_SHIFT)) 1745fb17030SIlya Yanok /* 0x27256222 */ 1755fb17030SIlya Yanok #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 1765fb17030SIlya Yanok | (4 << TIMING_CFG2_CPO_SHIFT) \ 1775fb17030SIlya Yanok | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 1785fb17030SIlya Yanok | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 1795fb17030SIlya Yanok | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 1805fb17030SIlya Yanok | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 1815fb17030SIlya Yanok | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 1825fb17030SIlya Yanok /* 0x121048c5 */ 1835fb17030SIlya Yanok #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 1845fb17030SIlya Yanok | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 1855fb17030SIlya Yanok /* 0x03600100 */ 1865fb17030SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 1875fb17030SIlya Yanok | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 188*2fef4020SJoe Hershberger | SDRAM_CFG_DBW_32) 1895fb17030SIlya Yanok /* 0x43080000 */ 1905fb17030SIlya Yanok 1915fb17030SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 1925fb17030SIlya Yanok #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 1935fb17030SIlya Yanok | (0x0232 << SDRAM_MODE_SD_SHIFT)) 1945fb17030SIlya Yanok /* ODT 150ohm CL=3, AL=1 on SDRAM */ 1955fb17030SIlya Yanok #define CONFIG_SYS_DDR_MODE2 0x00000000 1965fb17030SIlya Yanok 1975fb17030SIlya Yanok /* 1985fb17030SIlya Yanok * Memory test 1995fb17030SIlya Yanok */ 2005fb17030SIlya Yanok #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 2015fb17030SIlya Yanok #define CONFIG_SYS_MEMTEST_END 0x07f00000 2025fb17030SIlya Yanok 2035fb17030SIlya Yanok /* 2045fb17030SIlya Yanok * The reserved memory 2055fb17030SIlya Yanok */ 20614d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 2075fb17030SIlya Yanok 2085fb17030SIlya Yanok #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 2095fb17030SIlya Yanok #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 2105fb17030SIlya Yanok 2115fb17030SIlya Yanok /* 2125fb17030SIlya Yanok * Initial RAM Base Address Setup 2135fb17030SIlya Yanok */ 2145fb17030SIlya Yanok #define CONFIG_SYS_INIT_RAM_LOCK 1 2155fb17030SIlya Yanok #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 216553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 2175fb17030SIlya Yanok #define CONFIG_SYS_GBL_DATA_OFFSET \ 21825ddd1fbSWolfgang Denk (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2195fb17030SIlya Yanok 2205fb17030SIlya Yanok /* 2215fb17030SIlya Yanok * Local Bus Configuration & Clock Setup 2225fb17030SIlya Yanok */ 2235fb17030SIlya Yanok #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 2245fb17030SIlya Yanok #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 2255fb17030SIlya Yanok #define CONFIG_SYS_LBC_LBCR 0x00040000 2265fb17030SIlya Yanok 2275fb17030SIlya Yanok /* 2285fb17030SIlya Yanok * FLASH on the Local Bus 2295fb17030SIlya Yanok */ 2305fb17030SIlya Yanok #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 2315fb17030SIlya Yanok #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 2325fb17030SIlya Yanok #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 2335fb17030SIlya Yanok 2345fb17030SIlya Yanok #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 2355fb17030SIlya Yanok #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 2365fb17030SIlya Yanok #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 2375fb17030SIlya Yanok 2385fb17030SIlya Yanok /* Window base at flash base */ 2395fb17030SIlya Yanok #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 24065ea7589SIlya Yanok #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 2415fb17030SIlya Yanok 2425fb17030SIlya Yanok #define CONFIG_SYS_BR0_PRELIM (\ 2435fb17030SIlya Yanok CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\ 2445fb17030SIlya Yanok (2 << BR_PS_SHIFT) /* 16 bit port size */ |\ 2455fb17030SIlya Yanok BR_V) /* valid */ 2465fb17030SIlya Yanok #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ 2475fb17030SIlya Yanok | OR_UPM_XAM \ 2485fb17030SIlya Yanok | OR_GPCM_CSNT \ 2495fb17030SIlya Yanok | OR_GPCM_ACS_DIV2 \ 2505fb17030SIlya Yanok | OR_GPCM_XACS \ 2515fb17030SIlya Yanok | OR_GPCM_SCY_15 \ 2525fb17030SIlya Yanok | OR_GPCM_TRLX \ 2535fb17030SIlya Yanok | OR_GPCM_EHTR \ 2545fb17030SIlya Yanok | OR_GPCM_EAD) 2555fb17030SIlya Yanok 2565fb17030SIlya Yanok #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 2575fb17030SIlya Yanok /* 127 64KB sectors and 8 8KB top sectors per device */ 2585fb17030SIlya Yanok #define CONFIG_SYS_MAX_FLASH_SECT 135 2595fb17030SIlya Yanok 2605fb17030SIlya Yanok #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2615fb17030SIlya Yanok #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 2625fb17030SIlya Yanok 2635fb17030SIlya Yanok /* 2645fb17030SIlya Yanok * NAND Flash on the Local Bus 2655fb17030SIlya Yanok */ 2665fb17030SIlya Yanok #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 2675fb17030SIlya Yanok #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 2685fb17030SIlya Yanok | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 26934f81968SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 2705fb17030SIlya Yanok | BR_MS_FCM /* MSEL = FCM */ \ 2715fb17030SIlya Yanok | BR_V) /* valid */ 2725fb17030SIlya Yanok #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 /* length 32K */ \ 2735fb17030SIlya Yanok | OR_FCM_CSCT \ 2745fb17030SIlya Yanok | OR_FCM_CST \ 2755fb17030SIlya Yanok | OR_FCM_CHT \ 2765fb17030SIlya Yanok | OR_FCM_SCY_1 \ 2775fb17030SIlya Yanok | OR_FCM_TRLX \ 2785fb17030SIlya Yanok | OR_FCM_EHTR) 2795fb17030SIlya Yanok /* 0xFFFF8396 */ 2805fb17030SIlya Yanok 2815fb17030SIlya Yanok #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 28265ea7589SIlya Yanok #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 2835fb17030SIlya Yanok 2845fb17030SIlya Yanok #ifdef CONFIG_VSC7385_ENET 2855fb17030SIlya Yanok #define CONFIG_TSEC2 2865fb17030SIlya Yanok #define CONFIG_SYS_VSC7385_BASE 0xF0000000 2875fb17030SIlya Yanok #define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ 2885fb17030SIlya Yanok #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ 2895fb17030SIlya Yanok /* Access window base at VSC7385 base */ 2905fb17030SIlya Yanok #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 2915fb17030SIlya Yanok /* Access window size 128K */ 29265ea7589SIlya Yanok #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 2935fb17030SIlya Yanok /* The flash address and size of the VSC7385 firmware image */ 2945fb17030SIlya Yanok #define CONFIG_VSC7385_IMAGE 0xFE7FE000 2955fb17030SIlya Yanok #define CONFIG_VSC7385_IMAGE_SIZE 8192 2965fb17030SIlya Yanok #endif 2975fb17030SIlya Yanok /* 2985fb17030SIlya Yanok * Serial Port 2995fb17030SIlya Yanok */ 3005fb17030SIlya Yanok #define CONFIG_CONS_INDEX 1 3015fb17030SIlya Yanok #define CONFIG_SYS_NS16550 3025fb17030SIlya Yanok #define CONFIG_SYS_NS16550_SERIAL 3035fb17030SIlya Yanok #define CONFIG_SYS_NS16550_REG_SIZE 1 3045fb17030SIlya Yanok #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 3055fb17030SIlya Yanok 3065fb17030SIlya Yanok #define CONFIG_SYS_BAUDRATE_TABLE \ 3075fb17030SIlya Yanok {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 3085fb17030SIlya Yanok 3095fb17030SIlya Yanok #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 3105fb17030SIlya Yanok #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 3115fb17030SIlya Yanok 3125fb17030SIlya Yanok /* Use the HUSH parser */ 3135fb17030SIlya Yanok #define CONFIG_SYS_HUSH_PARSER 3145fb17030SIlya Yanok #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 3155fb17030SIlya Yanok 3165fb17030SIlya Yanok /* Pass open firmware flat tree */ 3175fb17030SIlya Yanok #define CONFIG_OF_LIBFDT 1 3185fb17030SIlya Yanok #define CONFIG_OF_BOARD_SETUP 1 3195fb17030SIlya Yanok #define CONFIG_OF_STDOUT_VIA_ALIAS 1 3205fb17030SIlya Yanok 3215fb17030SIlya Yanok /* I2C */ 3225fb17030SIlya Yanok #define CONFIG_HARD_I2C /* I2C with hardware support */ 3235fb17030SIlya Yanok #define CONFIG_FSL_I2C 3245fb17030SIlya Yanok #define CONFIG_I2C_MULTI_BUS 3255fb17030SIlya Yanok #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 3265fb17030SIlya Yanok #define CONFIG_SYS_I2C_SLAVE 0x7F 32734f81968SJoe Hershberger #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } /* Don't probe these addrs */ 3285fb17030SIlya Yanok #define CONFIG_SYS_I2C_OFFSET 0x3000 3295fb17030SIlya Yanok #define CONFIG_SYS_I2C2_OFFSET 0x3100 3305fb17030SIlya Yanok 3315fb17030SIlya Yanok 3325fb17030SIlya Yanok /* 3335fb17030SIlya Yanok * Board info - revision and where boot from 3345fb17030SIlya Yanok */ 3355fb17030SIlya Yanok #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 3365fb17030SIlya Yanok 3375fb17030SIlya Yanok /* 3385fb17030SIlya Yanok * Config on-board RTC 3395fb17030SIlya Yanok */ 3405fb17030SIlya Yanok #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 3415fb17030SIlya Yanok #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 3425fb17030SIlya Yanok 3435fb17030SIlya Yanok /* 3445fb17030SIlya Yanok * General PCI 3455fb17030SIlya Yanok * Addresses are mapped 1-1. 3465fb17030SIlya Yanok */ 3475fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_BASE 0xA0000000 3485fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 3495fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 3505fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 3515fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 3525fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 3535fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 3545fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 3555fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 3565fb17030SIlya Yanok 35765ea7589SIlya Yanok /* enable PCIE clock */ 35865ea7589SIlya Yanok #define CONFIG_SYS_SCCR_PCIEXP1CM 1 3595fb17030SIlya Yanok 3605fb17030SIlya Yanok #define CONFIG_PCI 3615fb17030SIlya Yanok #define CONFIG_PCIE 3625fb17030SIlya Yanok 3635fb17030SIlya Yanok #define CONFIG_PCI_PNP /* do pci plug-and-play */ 3645fb17030SIlya Yanok 3655fb17030SIlya Yanok #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 3665fb17030SIlya Yanok #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 3675fb17030SIlya Yanok 3685fb17030SIlya Yanok /* 3695fb17030SIlya Yanok * TSEC 3705fb17030SIlya Yanok */ 3715fb17030SIlya Yanok #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 3725fb17030SIlya Yanok #define CONFIG_SYS_TSEC1_OFFSET 0x24000 3735fb17030SIlya Yanok #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 3745fb17030SIlya Yanok #define CONFIG_SYS_TSEC2_OFFSET 0x25000 3755fb17030SIlya Yanok #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 3765fb17030SIlya Yanok 3775fb17030SIlya Yanok /* 3785fb17030SIlya Yanok * TSEC ethernet configuration 3795fb17030SIlya Yanok */ 3805fb17030SIlya Yanok #define CONFIG_MII 1 /* MII PHY management */ 3815fb17030SIlya Yanok #define CONFIG_TSEC1_NAME "eTSEC0" 3825fb17030SIlya Yanok #define CONFIG_TSEC2_NAME "eTSEC1" 3835fb17030SIlya Yanok #define TSEC1_PHY_ADDR 2 3845fb17030SIlya Yanok #define TSEC2_PHY_ADDR 1 3855fb17030SIlya Yanok #define TSEC1_PHYIDX 0 3865fb17030SIlya Yanok #define TSEC2_PHYIDX 0 3875fb17030SIlya Yanok #define TSEC1_FLAGS TSEC_GIGABIT 3885fb17030SIlya Yanok #define TSEC2_FLAGS TSEC_GIGABIT 3895fb17030SIlya Yanok 3905fb17030SIlya Yanok /* Options are: eTSEC[0-1] */ 3915fb17030SIlya Yanok #define CONFIG_ETHPRIME "eTSEC0" 3925fb17030SIlya Yanok 3935fb17030SIlya Yanok /* 3945fb17030SIlya Yanok * Environment 3955fb17030SIlya Yanok */ 3965fb17030SIlya Yanok #define CONFIG_ENV_IS_IN_FLASH 1 3975fb17030SIlya Yanok #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 3985fb17030SIlya Yanok CONFIG_SYS_MONITOR_LEN) 3995fb17030SIlya Yanok #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 4005fb17030SIlya Yanok #define CONFIG_ENV_SIZE 0x2000 4015fb17030SIlya Yanok #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 4025fb17030SIlya Yanok #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 4035fb17030SIlya Yanok 4045fb17030SIlya Yanok #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 4055fb17030SIlya Yanok #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 4065fb17030SIlya Yanok 4075fb17030SIlya Yanok /* 4085fb17030SIlya Yanok * BOOTP options 4095fb17030SIlya Yanok */ 4105fb17030SIlya Yanok #define CONFIG_BOOTP_BOOTFILESIZE 4115fb17030SIlya Yanok #define CONFIG_BOOTP_BOOTPATH 4125fb17030SIlya Yanok #define CONFIG_BOOTP_GATEWAY 4135fb17030SIlya Yanok #define CONFIG_BOOTP_HOSTNAME 4145fb17030SIlya Yanok 4155fb17030SIlya Yanok /* 4165fb17030SIlya Yanok * Command line configuration. 4175fb17030SIlya Yanok */ 4185fb17030SIlya Yanok #include <config_cmd_default.h> 4195fb17030SIlya Yanok 4205fb17030SIlya Yanok #define CONFIG_CMD_DATE 4215fb17030SIlya Yanok #define CONFIG_CMD_DHCP 4225fb17030SIlya Yanok #define CONFIG_CMD_I2C 4235fb17030SIlya Yanok #define CONFIG_CMD_MII 4245fb17030SIlya Yanok #define CONFIG_CMD_NET 4255fb17030SIlya Yanok #define CONFIG_CMD_PCI 4265fb17030SIlya Yanok #define CONFIG_CMD_PING 4275fb17030SIlya Yanok 4285fb17030SIlya Yanok #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 4295fb17030SIlya Yanok 4305fb17030SIlya Yanok /* 4315fb17030SIlya Yanok * Miscellaneous configurable options 4325fb17030SIlya Yanok */ 4335fb17030SIlya Yanok #define CONFIG_SYS_LONGHELP /* undef to save memory */ 4345fb17030SIlya Yanok #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 4355fb17030SIlya Yanok #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 4365fb17030SIlya Yanok 4375fb17030SIlya Yanok #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 4385fb17030SIlya Yanok 4395fb17030SIlya Yanok /* Print Buffer Size */ 4405fb17030SIlya Yanok #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 4415fb17030SIlya Yanok #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 4425fb17030SIlya Yanok /* Boot Argument Buffer Size */ 4435fb17030SIlya Yanok #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 4445fb17030SIlya Yanok #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 4455fb17030SIlya Yanok 4465fb17030SIlya Yanok /* 4475fb17030SIlya Yanok * For booting Linux, the board info and command line data 4489f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 4495fb17030SIlya Yanok * the maximum mapped by the Linux kernel during initialization. 4505fb17030SIlya Yanok */ 4519f530d59SIra W. Snyder #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 4525fb17030SIlya Yanok 4535fb17030SIlya Yanok /* 4545fb17030SIlya Yanok * Core HID Setup 4555fb17030SIlya Yanok */ 4565fb17030SIlya Yanok #define CONFIG_SYS_HID0_INIT 0x000000000 4575fb17030SIlya Yanok #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 4585fb17030SIlya Yanok HID0_ENABLE_INSTRUCTION_CACHE | \ 4595fb17030SIlya Yanok HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 4605fb17030SIlya Yanok #define CONFIG_SYS_HID2 HID2_HBE 4615fb17030SIlya Yanok 4625fb17030SIlya Yanok /* 4635fb17030SIlya Yanok * MMU Setup 4645fb17030SIlya Yanok */ 4655fb17030SIlya Yanok 4665fb17030SIlya Yanok /* DDR: cache cacheable */ 46772cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 4685fb17030SIlya Yanok BATL_MEMCOHERENCE) 4695fb17030SIlya Yanok #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 4705fb17030SIlya Yanok BATU_VS | BATU_VP) 4715fb17030SIlya Yanok #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 4725fb17030SIlya Yanok #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 4735fb17030SIlya Yanok 4745fb17030SIlya Yanok /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 47572cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 4765fb17030SIlya Yanok BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 4775fb17030SIlya Yanok #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 4785fb17030SIlya Yanok BATU_VP) 4795fb17030SIlya Yanok #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 4805fb17030SIlya Yanok #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 4815fb17030SIlya Yanok 4825fb17030SIlya Yanok /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 48372cd4087SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 4845fb17030SIlya Yanok BATL_MEMCOHERENCE) 4855fb17030SIlya Yanok #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 4865fb17030SIlya Yanok BATU_VS | BATU_VP) 48772cd4087SJoe Hershberger #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 4885fb17030SIlya Yanok BATL_CACHEINHIBIT | \ 4895fb17030SIlya Yanok BATL_GUARDEDSTORAGE) 4905fb17030SIlya Yanok #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 4915fb17030SIlya Yanok 4925fb17030SIlya Yanok /* Stack in dcache: cacheable, no memory coherence */ 49372cd4087SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 4945fb17030SIlya Yanok #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 4955fb17030SIlya Yanok BATU_VS | BATU_VP) 4965fb17030SIlya Yanok #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 4975fb17030SIlya Yanok #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 4985fb17030SIlya Yanok 4995fb17030SIlya Yanok /* 5005fb17030SIlya Yanok * Environment Configuration 5015fb17030SIlya Yanok */ 5025fb17030SIlya Yanok 5035fb17030SIlya Yanok #define CONFIG_ENV_OVERWRITE 5045fb17030SIlya Yanok 5055fb17030SIlya Yanok #if defined(CONFIG_TSEC_ENET) 5065fb17030SIlya Yanok #define CONFIG_HAS_ETH0 5075fb17030SIlya Yanok #define CONFIG_HAS_ETH1 5085fb17030SIlya Yanok #endif 5095fb17030SIlya Yanok 5105fb17030SIlya Yanok #define CONFIG_BAUDRATE 115200 5115fb17030SIlya Yanok 5125fb17030SIlya Yanok #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 5135fb17030SIlya Yanok 5145fb17030SIlya Yanok #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 5155fb17030SIlya Yanok 5165fb17030SIlya Yanok #define xstr(s) str(s) 5175fb17030SIlya Yanok #define str(s) #s 5185fb17030SIlya Yanok 5195fb17030SIlya Yanok #define CONFIG_EXTRA_ENV_SETTINGS \ 5205fb17030SIlya Yanok "netdev=eth0\0" \ 5215fb17030SIlya Yanok "consoledev=ttyS0\0" \ 5225fb17030SIlya Yanok "nfsargs=setenv bootargs root=/dev/nfs rw " \ 5235fb17030SIlya Yanok "nfsroot=${serverip}:${rootpath}\0" \ 5245fb17030SIlya Yanok "ramargs=setenv bootargs root=/dev/ram rw\0" \ 5255fb17030SIlya Yanok "addip=setenv bootargs ${bootargs} " \ 5265fb17030SIlya Yanok "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 5275fb17030SIlya Yanok ":${hostname}:${netdev}:off panic=1\0" \ 5285fb17030SIlya Yanok "addtty=setenv bootargs ${bootargs}" \ 5295fb17030SIlya Yanok " console=${consoledev},${baudrate}\0" \ 5305fb17030SIlya Yanok "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 5315fb17030SIlya Yanok "addmisc=setenv bootargs ${bootargs}\0" \ 5325fb17030SIlya Yanok "kernel_addr=FE080000\0" \ 5335fb17030SIlya Yanok "fdt_addr=FE280000\0" \ 5345fb17030SIlya Yanok "ramdisk_addr=FE290000\0" \ 5355fb17030SIlya Yanok "u-boot=mpc8308rdb/u-boot.bin\0" \ 5365fb17030SIlya Yanok "kernel_addr_r=1000000\0" \ 5375fb17030SIlya Yanok "fdt_addr_r=C00000\0" \ 5385fb17030SIlya Yanok "hostname=mpc8308rdb\0" \ 5395fb17030SIlya Yanok "bootfile=mpc8308rdb/uImage\0" \ 5405fb17030SIlya Yanok "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ 5415fb17030SIlya Yanok "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 5425fb17030SIlya Yanok "flash_self=run ramargs addip addtty addmtd addmisc;" \ 5435fb17030SIlya Yanok "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 5445fb17030SIlya Yanok "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 5455fb17030SIlya Yanok "bootm ${kernel_addr} - ${fdt_addr}\0" \ 5465fb17030SIlya Yanok "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 5475fb17030SIlya Yanok "tftp ${fdt_addr_r} ${fdtfile};" \ 5485fb17030SIlya Yanok "run nfsargs addip addtty addmtd addmisc;" \ 5495fb17030SIlya Yanok "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 5505fb17030SIlya Yanok "bootcmd=run flash_self\0" \ 5515fb17030SIlya Yanok "load=tftp ${loadaddr} ${u-boot}\0" \ 5525fb17030SIlya Yanok "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \ 5535fb17030SIlya Yanok " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \ 5545fb17030SIlya Yanok " +${filesize};cp.b ${fileaddr} " \ 5555fb17030SIlya Yanok xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 5565fb17030SIlya Yanok "upd=run load update\0" \ 5575fb17030SIlya Yanok 5585fb17030SIlya Yanok #endif /* __CONFIG_H */ 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