1 /* 2 * Configuation settings for the Freescale MCF5485 FireEngine board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5485EVB_H 15 #define _M5485EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_HW_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 27 28 /* Command line configuration */ 29 #define CONFIG_CMD_PCI 30 31 #define CONFIG_SLTTMR 32 33 #define CONFIG_FSLDMAFEC 34 #ifdef CONFIG_FSLDMAFEC 35 # define CONFIG_MII 1 36 # define CONFIG_MII_INIT 1 37 # define CONFIG_HAS_ETH1 38 39 # define CONFIG_SYS_DMA_USE_INTSRAM 1 40 # define CONFIG_SYS_DISCOVER_PHY 41 # define CONFIG_SYS_RX_ETH_BUFFER 32 42 # define CONFIG_SYS_TX_ETH_BUFFER 48 43 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 44 45 # define CONFIG_SYS_FEC0_PINMUX 0 46 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 47 # define CONFIG_SYS_FEC1_PINMUX 0 48 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 49 50 # define MCFFEC_TOUT_LOOP 50000 51 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 52 # ifndef CONFIG_SYS_DISCOVER_PHY 53 # define FECDUPLEX FULL 54 # define FECSPEED _100BASET 55 # else 56 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 57 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 58 # endif 59 # endif /* CONFIG_SYS_DISCOVER_PHY */ 60 61 # define CONFIG_IPADDR 192.162.1.2 62 # define CONFIG_NETMASK 255.255.255.0 63 # define CONFIG_SERVERIP 192.162.1.1 64 # define CONFIG_GATEWAYIP 192.162.1.1 65 66 #endif 67 68 #ifdef CONFIG_CMD_USB 69 # define CONFIG_USB_OHCI_NEW 70 # ifndef CONFIG_CMD_PCI 71 # define CONFIG_CMD_PCI 72 # endif 73 /*# define CONFIG_PCI_OHCI*/ 74 # define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000 75 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 76 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 77 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 78 #endif 79 80 /* I2C */ 81 #define CONFIG_SYS_I2C 82 #define CONFIG_SYS_I2C_FSL 83 #define CONFIG_SYS_FSL_I2C_SPEED 80000 84 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 85 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 86 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 87 88 /* PCI */ 89 #ifdef CONFIG_CMD_PCI 90 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 91 92 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 93 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 94 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 95 96 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 97 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 98 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 99 100 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 101 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 102 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 103 #endif 104 105 #define CONFIG_UDP_CHECKSUM 106 107 #define CONFIG_HOSTNAME M548xEVB 108 #define CONFIG_EXTRA_ENV_SETTINGS \ 109 "netdev=eth0\0" \ 110 "loadaddr=10000\0" \ 111 "u-boot=u-boot.bin\0" \ 112 "load=tftp ${loadaddr) ${u-boot}\0" \ 113 "upd=run load; run prog\0" \ 114 "prog=prot off bank 1;" \ 115 "era ff800000 ff83ffff;" \ 116 "cp.b ${loadaddr} ff800000 ${filesize};"\ 117 "save\0" \ 118 "" 119 120 #define CONFIG_PRAM 512 /* 512 KB */ 121 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 122 123 #ifdef CONFIG_CMD_KGDB 124 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 125 #else 126 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 127 #endif 128 129 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 130 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 131 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 132 #define CONFIG_SYS_LOAD_ADDR 0x00010000 133 134 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 135 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 136 137 #define CONFIG_SYS_MBAR 0xF0000000 138 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 139 #define CONFIG_SYS_INTSRAMSZ 0x8000 140 141 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 142 143 /* 144 * Low Level Configuration Settings 145 * (address mappings, register initial values, etc.) 146 * You should know what you are doing if you make changes here. 147 */ 148 /*----------------------------------------------------------------------- 149 * Definitions for initial stack pointer and data area (in DPRAM) 150 */ 151 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 152 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 153 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 154 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 155 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 156 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 157 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 158 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 159 160 /*----------------------------------------------------------------------- 161 * Start addresses for the final memory configuration 162 * (Set up by the startup code) 163 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 164 */ 165 #define CONFIG_SYS_SDRAM_BASE 0x00000000 166 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 167 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 168 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 169 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 170 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 171 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 172 #ifdef CONFIG_SYS_DRAMSZ1 173 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 174 #else 175 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 176 #endif 177 178 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 179 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 180 181 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 182 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 183 184 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 185 186 /* Reserve 256 kB for malloc() */ 187 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 188 /* 189 * For booting Linux, the board info and command line data 190 * have to be in the first 8 MB of memory, since this is 191 * the maximum mapped by the Linux kernel during initialization ?? 192 */ 193 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 194 195 /*----------------------------------------------------------------------- 196 * FLASH organization 197 */ 198 #define CONFIG_SYS_FLASH_CFI 199 #ifdef CONFIG_SYS_FLASH_CFI 200 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 201 # define CONFIG_FLASH_CFI_DRIVER 1 202 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 203 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 204 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 205 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 206 #ifdef CONFIG_SYS_NOR1SZ 207 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 208 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 209 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 210 #else 211 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 212 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 213 #endif 214 #endif 215 216 /* Configuration for environment 217 * Environment is not embedded in u-boot. First time runing may have env 218 * crc error warning if there is no correct environment on the flash. 219 */ 220 #define CONFIG_ENV_OFFSET 0x40000 221 #define CONFIG_ENV_SECT_SIZE 0x10000 222 223 /*----------------------------------------------------------------------- 224 * Cache Configuration 225 */ 226 #define CONFIG_SYS_CACHELINE_SIZE 16 227 228 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 229 CONFIG_SYS_INIT_RAM_SIZE - 8) 230 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 231 CONFIG_SYS_INIT_RAM_SIZE - 4) 232 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 233 CF_CACR_IDCM) 234 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 235 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 236 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 237 CF_ACR_EN | CF_ACR_SM_ALL) 238 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 239 CF_CACR_IEC | CF_CACR_ICINVA) 240 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 241 CF_CACR_DEC | CF_CACR_DDCM_P | \ 242 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 243 244 /*----------------------------------------------------------------------- 245 * Chipselect bank definitions 246 */ 247 /* 248 * CS0 - NOR Flash 1, 2, 4, or 8MB 249 * CS1 - NOR Flash 250 * CS2 - Available 251 * CS3 - Available 252 * CS4 - Available 253 * CS5 - Available 254 */ 255 #define CONFIG_SYS_CS0_BASE 0xFF800000 256 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 257 #define CONFIG_SYS_CS0_CTRL 0x00101980 258 259 #ifdef CONFIG_SYS_NOR1SZ 260 #define CONFIG_SYS_CS1_BASE 0xE0000000 261 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 262 #define CONFIG_SYS_CS1_CTRL 0x00101D80 263 #endif 264 265 #endif /* _M5485EVB_H */ 266