1 /* 2 * Configuation settings for the Freescale MCF5485 FireEngine board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5485EVB_H 15 #define _M5485EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 #define CONFIG_BAUDRATE 115200 25 26 #undef CONFIG_HW_WATCHDOG 27 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 28 29 /* Command line configuration */ 30 #undef CONFIG_CMD_DATE 31 #define CONFIG_CMD_PCI 32 #define CONFIG_CMD_REGINFO 33 34 #define CONFIG_SLTTMR 35 36 #define CONFIG_FSLDMAFEC 37 #ifdef CONFIG_FSLDMAFEC 38 # define CONFIG_MII 1 39 # define CONFIG_MII_INIT 1 40 # define CONFIG_HAS_ETH1 41 42 # define CONFIG_SYS_DMA_USE_INTSRAM 1 43 # define CONFIG_SYS_DISCOVER_PHY 44 # define CONFIG_SYS_RX_ETH_BUFFER 32 45 # define CONFIG_SYS_TX_ETH_BUFFER 48 46 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 47 48 # define CONFIG_SYS_FEC0_PINMUX 0 49 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 50 # define CONFIG_SYS_FEC1_PINMUX 0 51 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 52 53 # define MCFFEC_TOUT_LOOP 50000 54 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 55 # ifndef CONFIG_SYS_DISCOVER_PHY 56 # define FECDUPLEX FULL 57 # define FECSPEED _100BASET 58 # else 59 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 60 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 61 # endif 62 # endif /* CONFIG_SYS_DISCOVER_PHY */ 63 64 # define CONFIG_IPADDR 192.162.1.2 65 # define CONFIG_NETMASK 255.255.255.0 66 # define CONFIG_SERVERIP 192.162.1.1 67 # define CONFIG_GATEWAYIP 192.162.1.1 68 69 #endif 70 71 #ifdef CONFIG_CMD_USB 72 # define CONFIG_DOS_PARTITION 73 # define CONFIG_USB_OHCI_NEW 74 # ifndef CONFIG_CMD_PCI 75 # define CONFIG_CMD_PCI 76 # endif 77 /*# define CONFIG_PCI_OHCI*/ 78 # define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000 79 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 80 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 81 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 82 #endif 83 84 /* I2C */ 85 #define CONFIG_SYS_I2C 86 #define CONFIG_SYS_I2C_FSL 87 #define CONFIG_SYS_FSL_I2C_SPEED 80000 88 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 89 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 90 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 91 92 /* PCI */ 93 #ifdef CONFIG_CMD_PCI 94 #define CONFIG_PCI 1 95 #define CONFIG_PCI_PNP 1 96 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 97 98 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 99 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 100 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 101 102 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 103 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 104 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 105 106 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 107 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 108 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 109 #endif 110 111 #define CONFIG_UDP_CHECKSUM 112 113 #define CONFIG_HOSTNAME M548xEVB 114 #define CONFIG_EXTRA_ENV_SETTINGS \ 115 "netdev=eth0\0" \ 116 "loadaddr=10000\0" \ 117 "u-boot=u-boot.bin\0" \ 118 "load=tftp ${loadaddr) ${u-boot}\0" \ 119 "upd=run load; run prog\0" \ 120 "prog=prot off bank 1;" \ 121 "era ff800000 ff83ffff;" \ 122 "cp.b ${loadaddr} ff800000 ${filesize};"\ 123 "save\0" \ 124 "" 125 126 #define CONFIG_PRAM 512 /* 512 KB */ 127 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 128 129 #ifdef CONFIG_CMD_KGDB 130 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 131 #else 132 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 133 #endif 134 135 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 136 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 137 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 138 #define CONFIG_SYS_LOAD_ADDR 0x00010000 139 140 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 141 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 142 143 #define CONFIG_SYS_MBAR 0xF0000000 144 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 145 #define CONFIG_SYS_INTSRAMSZ 0x8000 146 147 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 148 149 /* 150 * Low Level Configuration Settings 151 * (address mappings, register initial values, etc.) 152 * You should know what you are doing if you make changes here. 153 */ 154 /*----------------------------------------------------------------------- 155 * Definitions for initial stack pointer and data area (in DPRAM) 156 */ 157 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 158 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 159 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 160 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 161 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 162 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 163 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 164 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 165 166 /*----------------------------------------------------------------------- 167 * Start addresses for the final memory configuration 168 * (Set up by the startup code) 169 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 170 */ 171 #define CONFIG_SYS_SDRAM_BASE 0x00000000 172 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 173 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 174 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 175 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 176 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 177 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 178 #ifdef CONFIG_SYS_DRAMSZ1 179 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 180 #else 181 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 182 #endif 183 184 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 185 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 186 187 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 188 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 189 190 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 191 192 /* Reserve 256 kB for malloc() */ 193 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 194 /* 195 * For booting Linux, the board info and command line data 196 * have to be in the first 8 MB of memory, since this is 197 * the maximum mapped by the Linux kernel during initialization ?? 198 */ 199 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 200 201 /*----------------------------------------------------------------------- 202 * FLASH organization 203 */ 204 #define CONFIG_SYS_FLASH_CFI 205 #ifdef CONFIG_SYS_FLASH_CFI 206 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 207 # define CONFIG_FLASH_CFI_DRIVER 1 208 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 209 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 210 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 211 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 212 #ifdef CONFIG_SYS_NOR1SZ 213 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 214 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 215 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 216 #else 217 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 218 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 219 #endif 220 #endif 221 222 /* Configuration for environment 223 * Environment is not embedded in u-boot. First time runing may have env 224 * crc error warning if there is no correct environment on the flash. 225 */ 226 #define CONFIG_ENV_OFFSET 0x40000 227 #define CONFIG_ENV_SECT_SIZE 0x10000 228 #define CONFIG_ENV_IS_IN_FLASH 1 229 230 /*----------------------------------------------------------------------- 231 * Cache Configuration 232 */ 233 #define CONFIG_SYS_CACHELINE_SIZE 16 234 235 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 236 CONFIG_SYS_INIT_RAM_SIZE - 8) 237 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 238 CONFIG_SYS_INIT_RAM_SIZE - 4) 239 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 240 CF_CACR_IDCM) 241 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 242 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 243 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 244 CF_ACR_EN | CF_ACR_SM_ALL) 245 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 246 CF_CACR_IEC | CF_CACR_ICINVA) 247 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 248 CF_CACR_DEC | CF_CACR_DDCM_P | \ 249 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 250 251 /*----------------------------------------------------------------------- 252 * Chipselect bank definitions 253 */ 254 /* 255 * CS0 - NOR Flash 1, 2, 4, or 8MB 256 * CS1 - NOR Flash 257 * CS2 - Available 258 * CS3 - Available 259 * CS4 - Available 260 * CS5 - Available 261 */ 262 #define CONFIG_SYS_CS0_BASE 0xFF800000 263 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 264 #define CONFIG_SYS_CS0_CTRL 0x00101980 265 266 #ifdef CONFIG_SYS_NOR1SZ 267 #define CONFIG_SYS_CS1_BASE 0xE0000000 268 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 269 #define CONFIG_SYS_CS1_CTRL 0x00101D80 270 #endif 271 272 #endif /* _M5485EVB_H */ 273