1 /* 2 * Configuation settings for the Freescale MCF5485 FireEngine board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5485EVB_H 15 #define _M5485EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_DISPLAY_BOARDINFO 23 24 #define CONFIG_MCFUART 25 #define CONFIG_SYS_UART_PORT (0) 26 #define CONFIG_BAUDRATE 115200 27 28 #undef CONFIG_HW_WATCHDOG 29 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 30 31 /* Command line configuration */ 32 #undef CONFIG_CMD_DATE 33 #define CONFIG_CMD_PCI 34 #define CONFIG_CMD_REGINFO 35 36 #define CONFIG_SLTTMR 37 38 #define CONFIG_FSLDMAFEC 39 #ifdef CONFIG_FSLDMAFEC 40 # define CONFIG_MII 1 41 # define CONFIG_MII_INIT 1 42 # define CONFIG_HAS_ETH1 43 44 # define CONFIG_SYS_DMA_USE_INTSRAM 1 45 # define CONFIG_SYS_DISCOVER_PHY 46 # define CONFIG_SYS_RX_ETH_BUFFER 32 47 # define CONFIG_SYS_TX_ETH_BUFFER 48 48 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 49 50 # define CONFIG_SYS_FEC0_PINMUX 0 51 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 52 # define CONFIG_SYS_FEC1_PINMUX 0 53 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 54 55 # define MCFFEC_TOUT_LOOP 50000 56 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 57 # ifndef CONFIG_SYS_DISCOVER_PHY 58 # define FECDUPLEX FULL 59 # define FECSPEED _100BASET 60 # else 61 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 62 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 63 # endif 64 # endif /* CONFIG_SYS_DISCOVER_PHY */ 65 66 # define CONFIG_IPADDR 192.162.1.2 67 # define CONFIG_NETMASK 255.255.255.0 68 # define CONFIG_SERVERIP 192.162.1.1 69 # define CONFIG_GATEWAYIP 192.162.1.1 70 71 #endif 72 73 #ifdef CONFIG_CMD_USB 74 # define CONFIG_USB_STORAGE 75 # define CONFIG_DOS_PARTITION 76 # define CONFIG_USB_OHCI_NEW 77 # ifndef CONFIG_CMD_PCI 78 # define CONFIG_CMD_PCI 79 # endif 80 /*# define CONFIG_PCI_OHCI*/ 81 # define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000 82 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 83 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 84 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 85 #endif 86 87 /* I2C */ 88 #define CONFIG_SYS_I2C 89 #define CONFIG_SYS_I2C_FSL 90 #define CONFIG_SYS_FSL_I2C_SPEED 80000 91 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 92 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 93 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 94 95 /* PCI */ 96 #ifdef CONFIG_CMD_PCI 97 #define CONFIG_PCI 1 98 #define CONFIG_PCI_PNP 1 99 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 100 101 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 102 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 103 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 104 105 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 106 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 107 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 108 109 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 110 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 111 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 112 #endif 113 114 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 115 #define CONFIG_UDP_CHECKSUM 116 117 #define CONFIG_HOSTNAME M548xEVB 118 #define CONFIG_EXTRA_ENV_SETTINGS \ 119 "netdev=eth0\0" \ 120 "loadaddr=10000\0" \ 121 "u-boot=u-boot.bin\0" \ 122 "load=tftp ${loadaddr) ${u-boot}\0" \ 123 "upd=run load; run prog\0" \ 124 "prog=prot off bank 1;" \ 125 "era ff800000 ff83ffff;" \ 126 "cp.b ${loadaddr} ff800000 ${filesize};"\ 127 "save\0" \ 128 "" 129 130 #define CONFIG_PRAM 512 /* 512 KB */ 131 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 132 133 #ifdef CONFIG_CMD_KGDB 134 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 135 #else 136 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 137 #endif 138 139 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 140 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 141 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 142 #define CONFIG_SYS_LOAD_ADDR 0x00010000 143 144 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 145 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 146 147 #define CONFIG_SYS_MBAR 0xF0000000 148 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 149 #define CONFIG_SYS_INTSRAMSZ 0x8000 150 151 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 152 153 /* 154 * Low Level Configuration Settings 155 * (address mappings, register initial values, etc.) 156 * You should know what you are doing if you make changes here. 157 */ 158 /*----------------------------------------------------------------------- 159 * Definitions for initial stack pointer and data area (in DPRAM) 160 */ 161 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 162 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 163 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 164 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 165 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 166 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 167 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 168 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 169 170 /*----------------------------------------------------------------------- 171 * Start addresses for the final memory configuration 172 * (Set up by the startup code) 173 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 174 */ 175 #define CONFIG_SYS_SDRAM_BASE 0x00000000 176 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 177 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 178 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 179 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 180 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 181 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 182 #ifdef CONFIG_SYS_DRAMSZ1 183 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 184 #else 185 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 186 #endif 187 188 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 189 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 190 191 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 192 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 193 194 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 195 196 /* Reserve 256 kB for malloc() */ 197 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 198 /* 199 * For booting Linux, the board info and command line data 200 * have to be in the first 8 MB of memory, since this is 201 * the maximum mapped by the Linux kernel during initialization ?? 202 */ 203 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 204 205 /*----------------------------------------------------------------------- 206 * FLASH organization 207 */ 208 #define CONFIG_SYS_FLASH_CFI 209 #ifdef CONFIG_SYS_FLASH_CFI 210 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 211 # define CONFIG_FLASH_CFI_DRIVER 1 212 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 213 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 214 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 215 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 216 #ifdef CONFIG_SYS_NOR1SZ 217 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 218 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 219 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 220 #else 221 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 222 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 223 #endif 224 #endif 225 226 /* Configuration for environment 227 * Environment is not embedded in u-boot. First time runing may have env 228 * crc error warning if there is no correct environment on the flash. 229 */ 230 #define CONFIG_ENV_OFFSET 0x40000 231 #define CONFIG_ENV_SECT_SIZE 0x10000 232 #define CONFIG_ENV_IS_IN_FLASH 1 233 234 /*----------------------------------------------------------------------- 235 * Cache Configuration 236 */ 237 #define CONFIG_SYS_CACHELINE_SIZE 16 238 239 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 240 CONFIG_SYS_INIT_RAM_SIZE - 8) 241 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 242 CONFIG_SYS_INIT_RAM_SIZE - 4) 243 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 244 CF_CACR_IDCM) 245 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 246 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 247 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 248 CF_ACR_EN | CF_ACR_SM_ALL) 249 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 250 CF_CACR_IEC | CF_CACR_ICINVA) 251 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 252 CF_CACR_DEC | CF_CACR_DDCM_P | \ 253 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 254 255 /*----------------------------------------------------------------------- 256 * Chipselect bank definitions 257 */ 258 /* 259 * CS0 - NOR Flash 1, 2, 4, or 8MB 260 * CS1 - NOR Flash 261 * CS2 - Available 262 * CS3 - Available 263 * CS4 - Available 264 * CS5 - Available 265 */ 266 #define CONFIG_SYS_CS0_BASE 0xFF800000 267 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 268 #define CONFIG_SYS_CS0_CTRL 0x00101980 269 270 #ifdef CONFIG_SYS_NOR1SZ 271 #define CONFIG_SYS_CS1_BASE 0xE0000000 272 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 273 #define CONFIG_SYS_CS1_CTRL 0x00101D80 274 #endif 275 276 #endif /* _M5485EVB_H */ 277