1 /* 2 * Configuation settings for the Freescale MCF5485 FireEngine board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5485EVB_H 15 #define _M5485EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_HW_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 27 28 /* Command line configuration */ 29 #define CONFIG_CMD_PCI 30 #define CONFIG_CMD_REGINFO 31 32 #define CONFIG_SLTTMR 33 34 #define CONFIG_FSLDMAFEC 35 #ifdef CONFIG_FSLDMAFEC 36 # define CONFIG_MII 1 37 # define CONFIG_MII_INIT 1 38 # define CONFIG_HAS_ETH1 39 40 # define CONFIG_SYS_DMA_USE_INTSRAM 1 41 # define CONFIG_SYS_DISCOVER_PHY 42 # define CONFIG_SYS_RX_ETH_BUFFER 32 43 # define CONFIG_SYS_TX_ETH_BUFFER 48 44 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 45 46 # define CONFIG_SYS_FEC0_PINMUX 0 47 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 48 # define CONFIG_SYS_FEC1_PINMUX 0 49 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 50 51 # define MCFFEC_TOUT_LOOP 50000 52 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 53 # ifndef CONFIG_SYS_DISCOVER_PHY 54 # define FECDUPLEX FULL 55 # define FECSPEED _100BASET 56 # else 57 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 58 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 59 # endif 60 # endif /* CONFIG_SYS_DISCOVER_PHY */ 61 62 # define CONFIG_IPADDR 192.162.1.2 63 # define CONFIG_NETMASK 255.255.255.0 64 # define CONFIG_SERVERIP 192.162.1.1 65 # define CONFIG_GATEWAYIP 192.162.1.1 66 67 #endif 68 69 #ifdef CONFIG_CMD_USB 70 # define CONFIG_USB_OHCI_NEW 71 # ifndef CONFIG_CMD_PCI 72 # define CONFIG_CMD_PCI 73 # endif 74 /*# define CONFIG_PCI_OHCI*/ 75 # define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000 76 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 77 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 78 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 79 #endif 80 81 /* I2C */ 82 #define CONFIG_SYS_I2C 83 #define CONFIG_SYS_I2C_FSL 84 #define CONFIG_SYS_FSL_I2C_SPEED 80000 85 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 86 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 87 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 88 89 /* PCI */ 90 #ifdef CONFIG_CMD_PCI 91 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 92 93 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 94 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 95 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 96 97 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 98 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 99 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 100 101 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 102 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 103 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 104 #endif 105 106 #define CONFIG_UDP_CHECKSUM 107 108 #define CONFIG_HOSTNAME M548xEVB 109 #define CONFIG_EXTRA_ENV_SETTINGS \ 110 "netdev=eth0\0" \ 111 "loadaddr=10000\0" \ 112 "u-boot=u-boot.bin\0" \ 113 "load=tftp ${loadaddr) ${u-boot}\0" \ 114 "upd=run load; run prog\0" \ 115 "prog=prot off bank 1;" \ 116 "era ff800000 ff83ffff;" \ 117 "cp.b ${loadaddr} ff800000 ${filesize};"\ 118 "save\0" \ 119 "" 120 121 #define CONFIG_PRAM 512 /* 512 KB */ 122 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 123 124 #ifdef CONFIG_CMD_KGDB 125 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 126 #else 127 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 128 #endif 129 130 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 131 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 132 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 133 #define CONFIG_SYS_LOAD_ADDR 0x00010000 134 135 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 136 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 137 138 #define CONFIG_SYS_MBAR 0xF0000000 139 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 140 #define CONFIG_SYS_INTSRAMSZ 0x8000 141 142 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 143 144 /* 145 * Low Level Configuration Settings 146 * (address mappings, register initial values, etc.) 147 * You should know what you are doing if you make changes here. 148 */ 149 /*----------------------------------------------------------------------- 150 * Definitions for initial stack pointer and data area (in DPRAM) 151 */ 152 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 153 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 154 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 155 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 156 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 157 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 158 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 159 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 160 161 /*----------------------------------------------------------------------- 162 * Start addresses for the final memory configuration 163 * (Set up by the startup code) 164 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 165 */ 166 #define CONFIG_SYS_SDRAM_BASE 0x00000000 167 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 168 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 169 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 170 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 171 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 172 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 173 #ifdef CONFIG_SYS_DRAMSZ1 174 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 175 #else 176 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 177 #endif 178 179 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 180 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 181 182 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 183 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 184 185 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 186 187 /* Reserve 256 kB for malloc() */ 188 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 189 /* 190 * For booting Linux, the board info and command line data 191 * have to be in the first 8 MB of memory, since this is 192 * the maximum mapped by the Linux kernel during initialization ?? 193 */ 194 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 195 196 /*----------------------------------------------------------------------- 197 * FLASH organization 198 */ 199 #define CONFIG_SYS_FLASH_CFI 200 #ifdef CONFIG_SYS_FLASH_CFI 201 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 202 # define CONFIG_FLASH_CFI_DRIVER 1 203 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 204 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 205 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 206 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 207 #ifdef CONFIG_SYS_NOR1SZ 208 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 209 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 210 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 211 #else 212 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 213 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 214 #endif 215 #endif 216 217 /* Configuration for environment 218 * Environment is not embedded in u-boot. First time runing may have env 219 * crc error warning if there is no correct environment on the flash. 220 */ 221 #define CONFIG_ENV_OFFSET 0x40000 222 #define CONFIG_ENV_SECT_SIZE 0x10000 223 #define CONFIG_ENV_IS_IN_FLASH 1 224 225 /*----------------------------------------------------------------------- 226 * Cache Configuration 227 */ 228 #define CONFIG_SYS_CACHELINE_SIZE 16 229 230 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 231 CONFIG_SYS_INIT_RAM_SIZE - 8) 232 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 233 CONFIG_SYS_INIT_RAM_SIZE - 4) 234 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 235 CF_CACR_IDCM) 236 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 237 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 238 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 239 CF_ACR_EN | CF_ACR_SM_ALL) 240 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 241 CF_CACR_IEC | CF_CACR_ICINVA) 242 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 243 CF_CACR_DEC | CF_CACR_DDCM_P | \ 244 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 245 246 /*----------------------------------------------------------------------- 247 * Chipselect bank definitions 248 */ 249 /* 250 * CS0 - NOR Flash 1, 2, 4, or 8MB 251 * CS1 - NOR Flash 252 * CS2 - Available 253 * CS3 - Available 254 * CS4 - Available 255 * CS5 - Available 256 */ 257 #define CONFIG_SYS_CS0_BASE 0xFF800000 258 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 259 #define CONFIG_SYS_CS0_CTRL 0x00101980 260 261 #ifdef CONFIG_SYS_NOR1SZ 262 #define CONFIG_SYS_CS1_BASE 0xE0000000 263 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 264 #define CONFIG_SYS_CS1_CTRL 0x00101D80 265 #endif 266 267 #endif /* _M5485EVB_H */ 268