1 /* 2 * Configuation settings for the Freescale MCF5485 FireEngine board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5485EVB_H 15 #define _M5485EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 #define CONFIG_BAUDRATE 115200 25 26 #undef CONFIG_HW_WATCHDOG 27 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 28 29 /* Command line configuration */ 30 #undef CONFIG_CMD_DATE 31 #define CONFIG_CMD_PCI 32 #define CONFIG_CMD_REGINFO 33 34 #define CONFIG_SLTTMR 35 36 #define CONFIG_FSLDMAFEC 37 #ifdef CONFIG_FSLDMAFEC 38 # define CONFIG_MII 1 39 # define CONFIG_MII_INIT 1 40 # define CONFIG_HAS_ETH1 41 42 # define CONFIG_SYS_DMA_USE_INTSRAM 1 43 # define CONFIG_SYS_DISCOVER_PHY 44 # define CONFIG_SYS_RX_ETH_BUFFER 32 45 # define CONFIG_SYS_TX_ETH_BUFFER 48 46 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 47 48 # define CONFIG_SYS_FEC0_PINMUX 0 49 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 50 # define CONFIG_SYS_FEC1_PINMUX 0 51 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 52 53 # define MCFFEC_TOUT_LOOP 50000 54 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 55 # ifndef CONFIG_SYS_DISCOVER_PHY 56 # define FECDUPLEX FULL 57 # define FECSPEED _100BASET 58 # else 59 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 60 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 61 # endif 62 # endif /* CONFIG_SYS_DISCOVER_PHY */ 63 64 # define CONFIG_IPADDR 192.162.1.2 65 # define CONFIG_NETMASK 255.255.255.0 66 # define CONFIG_SERVERIP 192.162.1.1 67 # define CONFIG_GATEWAYIP 192.162.1.1 68 69 #endif 70 71 #ifdef CONFIG_CMD_USB 72 # define CONFIG_USB_OHCI_NEW 73 # ifndef CONFIG_CMD_PCI 74 # define CONFIG_CMD_PCI 75 # endif 76 /*# define CONFIG_PCI_OHCI*/ 77 # define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000 78 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 79 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 80 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 81 #endif 82 83 /* I2C */ 84 #define CONFIG_SYS_I2C 85 #define CONFIG_SYS_I2C_FSL 86 #define CONFIG_SYS_FSL_I2C_SPEED 80000 87 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 88 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 89 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 90 91 /* PCI */ 92 #ifdef CONFIG_CMD_PCI 93 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 94 95 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 96 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 97 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 98 99 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 100 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 101 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 102 103 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 104 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 105 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 106 #endif 107 108 #define CONFIG_UDP_CHECKSUM 109 110 #define CONFIG_HOSTNAME M548xEVB 111 #define CONFIG_EXTRA_ENV_SETTINGS \ 112 "netdev=eth0\0" \ 113 "loadaddr=10000\0" \ 114 "u-boot=u-boot.bin\0" \ 115 "load=tftp ${loadaddr) ${u-boot}\0" \ 116 "upd=run load; run prog\0" \ 117 "prog=prot off bank 1;" \ 118 "era ff800000 ff83ffff;" \ 119 "cp.b ${loadaddr} ff800000 ${filesize};"\ 120 "save\0" \ 121 "" 122 123 #define CONFIG_PRAM 512 /* 512 KB */ 124 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 125 126 #ifdef CONFIG_CMD_KGDB 127 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 128 #else 129 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 130 #endif 131 132 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 133 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 134 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 135 #define CONFIG_SYS_LOAD_ADDR 0x00010000 136 137 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 138 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 139 140 #define CONFIG_SYS_MBAR 0xF0000000 141 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 142 #define CONFIG_SYS_INTSRAMSZ 0x8000 143 144 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 145 146 /* 147 * Low Level Configuration Settings 148 * (address mappings, register initial values, etc.) 149 * You should know what you are doing if you make changes here. 150 */ 151 /*----------------------------------------------------------------------- 152 * Definitions for initial stack pointer and data area (in DPRAM) 153 */ 154 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 155 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 156 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 157 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 158 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 159 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 160 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 161 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 162 163 /*----------------------------------------------------------------------- 164 * Start addresses for the final memory configuration 165 * (Set up by the startup code) 166 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 167 */ 168 #define CONFIG_SYS_SDRAM_BASE 0x00000000 169 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 170 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 171 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 172 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 173 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 174 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 175 #ifdef CONFIG_SYS_DRAMSZ1 176 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 177 #else 178 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 179 #endif 180 181 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 182 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 183 184 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 185 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 186 187 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 188 189 /* Reserve 256 kB for malloc() */ 190 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 191 /* 192 * For booting Linux, the board info and command line data 193 * have to be in the first 8 MB of memory, since this is 194 * the maximum mapped by the Linux kernel during initialization ?? 195 */ 196 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 197 198 /*----------------------------------------------------------------------- 199 * FLASH organization 200 */ 201 #define CONFIG_SYS_FLASH_CFI 202 #ifdef CONFIG_SYS_FLASH_CFI 203 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 204 # define CONFIG_FLASH_CFI_DRIVER 1 205 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 206 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 207 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 208 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 209 #ifdef CONFIG_SYS_NOR1SZ 210 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 211 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 212 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 213 #else 214 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 215 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 216 #endif 217 #endif 218 219 /* Configuration for environment 220 * Environment is not embedded in u-boot. First time runing may have env 221 * crc error warning if there is no correct environment on the flash. 222 */ 223 #define CONFIG_ENV_OFFSET 0x40000 224 #define CONFIG_ENV_SECT_SIZE 0x10000 225 #define CONFIG_ENV_IS_IN_FLASH 1 226 227 /*----------------------------------------------------------------------- 228 * Cache Configuration 229 */ 230 #define CONFIG_SYS_CACHELINE_SIZE 16 231 232 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 233 CONFIG_SYS_INIT_RAM_SIZE - 8) 234 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 235 CONFIG_SYS_INIT_RAM_SIZE - 4) 236 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 237 CF_CACR_IDCM) 238 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 239 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 240 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 241 CF_ACR_EN | CF_ACR_SM_ALL) 242 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 243 CF_CACR_IEC | CF_CACR_ICINVA) 244 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 245 CF_CACR_DEC | CF_CACR_DDCM_P | \ 246 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 247 248 /*----------------------------------------------------------------------- 249 * Chipselect bank definitions 250 */ 251 /* 252 * CS0 - NOR Flash 1, 2, 4, or 8MB 253 * CS1 - NOR Flash 254 * CS2 - Available 255 * CS3 - Available 256 * CS4 - Available 257 * CS5 - Available 258 */ 259 #define CONFIG_SYS_CS0_BASE 0xFF800000 260 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 261 #define CONFIG_SYS_CS0_CTRL 0x00101980 262 263 #ifdef CONFIG_SYS_NOR1SZ 264 #define CONFIG_SYS_CS1_BASE 0xE0000000 265 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 266 #define CONFIG_SYS_CS1_CTRL 0x00101D80 267 #endif 268 269 #endif /* _M5485EVB_H */ 270