1 /* 2 * Configuation settings for the Freescale MCF5485 FireEngine board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5485EVB_H 15 #define _M5485EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_DISPLAY_BOARDINFO 23 24 #define CONFIG_MCFUART 25 #define CONFIG_SYS_UART_PORT (0) 26 #define CONFIG_BAUDRATE 115200 27 28 #undef CONFIG_HW_WATCHDOG 29 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 30 31 /* Command line configuration */ 32 #define CONFIG_CMD_CACHE 33 #undef CONFIG_CMD_DATE 34 #define CONFIG_CMD_ELF 35 #define CONFIG_CMD_I2C 36 #define CONFIG_CMD_MII 37 #define CONFIG_CMD_PCI 38 #define CONFIG_CMD_PING 39 #define CONFIG_CMD_REGINFO 40 #define CONFIG_CMD_USB 41 42 #define CONFIG_SLTTMR 43 44 #define CONFIG_FSLDMAFEC 45 #ifdef CONFIG_FSLDMAFEC 46 # define CONFIG_MII 1 47 # define CONFIG_MII_INIT 1 48 # define CONFIG_HAS_ETH1 49 50 # define CONFIG_SYS_DMA_USE_INTSRAM 1 51 # define CONFIG_SYS_DISCOVER_PHY 52 # define CONFIG_SYS_RX_ETH_BUFFER 32 53 # define CONFIG_SYS_TX_ETH_BUFFER 48 54 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 55 56 # define CONFIG_SYS_FEC0_PINMUX 0 57 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 58 # define CONFIG_SYS_FEC1_PINMUX 0 59 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 60 61 # define MCFFEC_TOUT_LOOP 50000 62 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 63 # ifndef CONFIG_SYS_DISCOVER_PHY 64 # define FECDUPLEX FULL 65 # define FECSPEED _100BASET 66 # else 67 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 68 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 69 # endif 70 # endif /* CONFIG_SYS_DISCOVER_PHY */ 71 72 # define CONFIG_IPADDR 192.162.1.2 73 # define CONFIG_NETMASK 255.255.255.0 74 # define CONFIG_SERVERIP 192.162.1.1 75 # define CONFIG_GATEWAYIP 192.162.1.1 76 77 #endif 78 79 #ifdef CONFIG_CMD_USB 80 # define CONFIG_USB_STORAGE 81 # define CONFIG_DOS_PARTITION 82 # define CONFIG_USB_OHCI_NEW 83 # ifndef CONFIG_CMD_PCI 84 # define CONFIG_CMD_PCI 85 # endif 86 /*# define CONFIG_PCI_OHCI*/ 87 # define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000 88 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 89 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 90 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 91 #endif 92 93 /* I2C */ 94 #define CONFIG_SYS_I2C 95 #define CONFIG_SYS_I2C_FSL 96 #define CONFIG_SYS_FSL_I2C_SPEED 80000 97 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 98 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 99 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 100 101 /* PCI */ 102 #ifdef CONFIG_CMD_PCI 103 #define CONFIG_PCI 1 104 #define CONFIG_PCI_PNP 1 105 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 106 107 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 108 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 109 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 110 111 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 112 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 113 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 114 115 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 116 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 117 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 118 #endif 119 120 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 121 #define CONFIG_UDP_CHECKSUM 122 123 #define CONFIG_HOSTNAME M548xEVB 124 #define CONFIG_EXTRA_ENV_SETTINGS \ 125 "netdev=eth0\0" \ 126 "loadaddr=10000\0" \ 127 "u-boot=u-boot.bin\0" \ 128 "load=tftp ${loadaddr) ${u-boot}\0" \ 129 "upd=run load; run prog\0" \ 130 "prog=prot off bank 1;" \ 131 "era ff800000 ff83ffff;" \ 132 "cp.b ${loadaddr} ff800000 ${filesize};"\ 133 "save\0" \ 134 "" 135 136 #define CONFIG_PRAM 512 /* 512 KB */ 137 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 138 139 #ifdef CONFIG_CMD_KGDB 140 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 141 #else 142 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 143 #endif 144 145 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 146 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 147 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 148 #define CONFIG_SYS_LOAD_ADDR 0x00010000 149 150 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 151 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 152 153 #define CONFIG_SYS_MBAR 0xF0000000 154 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 155 #define CONFIG_SYS_INTSRAMSZ 0x8000 156 157 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 158 159 /* 160 * Low Level Configuration Settings 161 * (address mappings, register initial values, etc.) 162 * You should know what you are doing if you make changes here. 163 */ 164 /*----------------------------------------------------------------------- 165 * Definitions for initial stack pointer and data area (in DPRAM) 166 */ 167 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 168 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 169 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 170 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 171 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 172 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 173 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 174 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 175 176 /*----------------------------------------------------------------------- 177 * Start addresses for the final memory configuration 178 * (Set up by the startup code) 179 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 180 */ 181 #define CONFIG_SYS_SDRAM_BASE 0x00000000 182 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 183 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 184 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 185 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 186 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 187 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 188 #ifdef CONFIG_SYS_DRAMSZ1 189 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 190 #else 191 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 192 #endif 193 194 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 195 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 196 197 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 198 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 199 200 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 201 202 /* Reserve 256 kB for malloc() */ 203 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 204 /* 205 * For booting Linux, the board info and command line data 206 * have to be in the first 8 MB of memory, since this is 207 * the maximum mapped by the Linux kernel during initialization ?? 208 */ 209 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 210 211 /*----------------------------------------------------------------------- 212 * FLASH organization 213 */ 214 #define CONFIG_SYS_FLASH_CFI 215 #ifdef CONFIG_SYS_FLASH_CFI 216 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 217 # define CONFIG_FLASH_CFI_DRIVER 1 218 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 219 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 220 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 221 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 222 #ifdef CONFIG_SYS_NOR1SZ 223 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 224 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 225 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 226 #else 227 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 228 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 229 #endif 230 #endif 231 232 /* Configuration for environment 233 * Environment is not embedded in u-boot. First time runing may have env 234 * crc error warning if there is no correct environment on the flash. 235 */ 236 #define CONFIG_ENV_OFFSET 0x40000 237 #define CONFIG_ENV_SECT_SIZE 0x10000 238 #define CONFIG_ENV_IS_IN_FLASH 1 239 240 /*----------------------------------------------------------------------- 241 * Cache Configuration 242 */ 243 #define CONFIG_SYS_CACHELINE_SIZE 16 244 245 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 246 CONFIG_SYS_INIT_RAM_SIZE - 8) 247 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 248 CONFIG_SYS_INIT_RAM_SIZE - 4) 249 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 250 CF_CACR_IDCM) 251 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 252 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 253 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 254 CF_ACR_EN | CF_ACR_SM_ALL) 255 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 256 CF_CACR_IEC | CF_CACR_ICINVA) 257 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 258 CF_CACR_DEC | CF_CACR_DDCM_P | \ 259 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 260 261 /*----------------------------------------------------------------------- 262 * Chipselect bank definitions 263 */ 264 /* 265 * CS0 - NOR Flash 1, 2, 4, or 8MB 266 * CS1 - NOR Flash 267 * CS2 - Available 268 * CS3 - Available 269 * CS4 - Available 270 * CS5 - Available 271 */ 272 #define CONFIG_SYS_CS0_BASE 0xFF800000 273 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 274 #define CONFIG_SYS_CS0_CTRL 0x00101980 275 276 #ifdef CONFIG_SYS_NOR1SZ 277 #define CONFIG_SYS_CS1_BASE 0xE0000000 278 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 279 #define CONFIG_SYS_CS1_CTRL 0x00101D80 280 #endif 281 282 #endif /* _M5485EVB_H */ 283