1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Freescale MCF5485 FireEngine board. 4 * 5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M5485EVB_H 14 #define _M5485EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21 #define CONFIG_MCFUART 22 #define CONFIG_SYS_UART_PORT (0) 23 24 #undef CONFIG_HW_WATCHDOG 25 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 26 27 #define CONFIG_SLTTMR 28 29 #define CONFIG_FSLDMAFEC 30 #ifdef CONFIG_FSLDMAFEC 31 # define CONFIG_MII 1 32 # define CONFIG_MII_INIT 1 33 # define CONFIG_HAS_ETH1 34 35 # define CONFIG_SYS_DMA_USE_INTSRAM 1 36 # define CONFIG_SYS_DISCOVER_PHY 37 # define CONFIG_SYS_RX_ETH_BUFFER 32 38 # define CONFIG_SYS_TX_ETH_BUFFER 48 39 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 40 41 # define CONFIG_SYS_FEC0_PINMUX 0 42 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 43 # define CONFIG_SYS_FEC1_PINMUX 0 44 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 45 46 # define MCFFEC_TOUT_LOOP 50000 47 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 48 # ifndef CONFIG_SYS_DISCOVER_PHY 49 # define FECDUPLEX FULL 50 # define FECSPEED _100BASET 51 # else 52 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 53 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 54 # endif 55 # endif /* CONFIG_SYS_DISCOVER_PHY */ 56 57 # define CONFIG_IPADDR 192.162.1.2 58 # define CONFIG_NETMASK 255.255.255.0 59 # define CONFIG_SERVERIP 192.162.1.1 60 # define CONFIG_GATEWAYIP 192.162.1.1 61 62 #endif 63 64 #ifdef CONFIG_CMD_USB 65 # define CONFIG_USB_OHCI_NEW 66 /*# define CONFIG_PCI_OHCI*/ 67 # define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000 68 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 69 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 70 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 71 #endif 72 73 /* I2C */ 74 #define CONFIG_SYS_I2C 75 #define CONFIG_SYS_I2C_FSL 76 #define CONFIG_SYS_FSL_I2C_SPEED 80000 77 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 78 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 79 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 80 81 /* PCI */ 82 #ifdef CONFIG_CMD_PCI 83 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 84 85 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 86 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 87 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 88 89 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 90 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 91 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 92 93 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 94 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 95 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 96 #endif 97 98 #define CONFIG_UDP_CHECKSUM 99 100 #define CONFIG_HOSTNAME "M548xEVB" 101 #define CONFIG_EXTRA_ENV_SETTINGS \ 102 "netdev=eth0\0" \ 103 "loadaddr=10000\0" \ 104 "u-boot=u-boot.bin\0" \ 105 "load=tftp ${loadaddr) ${u-boot}\0" \ 106 "upd=run load; run prog\0" \ 107 "prog=prot off bank 1;" \ 108 "era ff800000 ff83ffff;" \ 109 "cp.b ${loadaddr} ff800000 ${filesize};"\ 110 "save\0" \ 111 "" 112 113 #define CONFIG_PRAM 512 /* 512 KB */ 114 115 #define CONFIG_SYS_LOAD_ADDR 0x00010000 116 117 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 118 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 119 120 #define CONFIG_SYS_MBAR 0xF0000000 121 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 122 #define CONFIG_SYS_INTSRAMSZ 0x8000 123 124 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 125 126 /* 127 * Low Level Configuration Settings 128 * (address mappings, register initial values, etc.) 129 * You should know what you are doing if you make changes here. 130 */ 131 /*----------------------------------------------------------------------- 132 * Definitions for initial stack pointer and data area (in DPRAM) 133 */ 134 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 135 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 136 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 137 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 138 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 139 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 140 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 141 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 142 143 /*----------------------------------------------------------------------- 144 * Start addresses for the final memory configuration 145 * (Set up by the startup code) 146 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 147 */ 148 #define CONFIG_SYS_SDRAM_BASE 0x00000000 149 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 150 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 151 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 152 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 153 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 154 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 155 #ifdef CONFIG_SYS_DRAMSZ1 156 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 157 #else 158 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 159 #endif 160 161 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 162 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 163 164 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 165 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 166 167 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 168 169 /* Reserve 256 kB for malloc() */ 170 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 171 /* 172 * For booting Linux, the board info and command line data 173 * have to be in the first 8 MB of memory, since this is 174 * the maximum mapped by the Linux kernel during initialization ?? 175 */ 176 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 177 178 /*----------------------------------------------------------------------- 179 * FLASH organization 180 */ 181 #define CONFIG_SYS_FLASH_CFI 182 #ifdef CONFIG_SYS_FLASH_CFI 183 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 184 # define CONFIG_FLASH_CFI_DRIVER 1 185 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 186 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 187 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 188 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 189 #ifdef CONFIG_SYS_NOR1SZ 190 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 191 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 192 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 193 #else 194 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 195 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 196 #endif 197 #endif 198 199 /* Configuration for environment 200 * Environment is not embedded in u-boot. First time runing may have env 201 * crc error warning if there is no correct environment on the flash. 202 */ 203 #define CONFIG_ENV_OFFSET 0x40000 204 #define CONFIG_ENV_SECT_SIZE 0x10000 205 206 /*----------------------------------------------------------------------- 207 * Cache Configuration 208 */ 209 #define CONFIG_SYS_CACHELINE_SIZE 16 210 211 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 212 CONFIG_SYS_INIT_RAM_SIZE - 8) 213 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 214 CONFIG_SYS_INIT_RAM_SIZE - 4) 215 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 216 CF_CACR_IDCM) 217 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 218 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 219 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 220 CF_ACR_EN | CF_ACR_SM_ALL) 221 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 222 CF_CACR_IEC | CF_CACR_ICINVA) 223 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 224 CF_CACR_DEC | CF_CACR_DDCM_P | \ 225 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 226 227 /*----------------------------------------------------------------------- 228 * Chipselect bank definitions 229 */ 230 /* 231 * CS0 - NOR Flash 1, 2, 4, or 8MB 232 * CS1 - NOR Flash 233 * CS2 - Available 234 * CS3 - Available 235 * CS4 - Available 236 * CS5 - Available 237 */ 238 #define CONFIG_SYS_CS0_BASE 0xFF800000 239 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 240 #define CONFIG_SYS_CS0_CTRL 0x00101980 241 242 #ifdef CONFIG_SYS_NOR1SZ 243 #define CONFIG_SYS_CS1_BASE 0xE0000000 244 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 245 #define CONFIG_SYS_CS1_CTRL 0x00101D80 246 #endif 247 248 #endif /* _M5485EVB_H */ 249