1 /* 2 * Configuation settings for the Freescale MCF5485 FireEngine board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5485EVB_H 15 #define _M5485EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_HW_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 27 28 #define CONFIG_SLTTMR 29 30 #define CONFIG_FSLDMAFEC 31 #ifdef CONFIG_FSLDMAFEC 32 # define CONFIG_MII 1 33 # define CONFIG_MII_INIT 1 34 # define CONFIG_HAS_ETH1 35 36 # define CONFIG_SYS_DMA_USE_INTSRAM 1 37 # define CONFIG_SYS_DISCOVER_PHY 38 # define CONFIG_SYS_RX_ETH_BUFFER 32 39 # define CONFIG_SYS_TX_ETH_BUFFER 48 40 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 41 42 # define CONFIG_SYS_FEC0_PINMUX 0 43 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 44 # define CONFIG_SYS_FEC1_PINMUX 0 45 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 46 47 # define MCFFEC_TOUT_LOOP 50000 48 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 49 # ifndef CONFIG_SYS_DISCOVER_PHY 50 # define FECDUPLEX FULL 51 # define FECSPEED _100BASET 52 # else 53 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 54 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 55 # endif 56 # endif /* CONFIG_SYS_DISCOVER_PHY */ 57 58 # define CONFIG_IPADDR 192.162.1.2 59 # define CONFIG_NETMASK 255.255.255.0 60 # define CONFIG_SERVERIP 192.162.1.1 61 # define CONFIG_GATEWAYIP 192.162.1.1 62 63 #endif 64 65 #ifdef CONFIG_CMD_USB 66 # define CONFIG_USB_OHCI_NEW 67 /*# define CONFIG_PCI_OHCI*/ 68 # define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000 69 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 70 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 71 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 72 #endif 73 74 /* I2C */ 75 #define CONFIG_SYS_I2C 76 #define CONFIG_SYS_I2C_FSL 77 #define CONFIG_SYS_FSL_I2C_SPEED 80000 78 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 79 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 80 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 81 82 /* PCI */ 83 #ifdef CONFIG_CMD_PCI 84 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 85 86 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 87 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 88 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 89 90 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 91 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 92 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 93 94 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 95 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 96 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 97 #endif 98 99 #define CONFIG_UDP_CHECKSUM 100 101 #define CONFIG_HOSTNAME M548xEVB 102 #define CONFIG_EXTRA_ENV_SETTINGS \ 103 "netdev=eth0\0" \ 104 "loadaddr=10000\0" \ 105 "u-boot=u-boot.bin\0" \ 106 "load=tftp ${loadaddr) ${u-boot}\0" \ 107 "upd=run load; run prog\0" \ 108 "prog=prot off bank 1;" \ 109 "era ff800000 ff83ffff;" \ 110 "cp.b ${loadaddr} ff800000 ${filesize};"\ 111 "save\0" \ 112 "" 113 114 #define CONFIG_PRAM 512 /* 512 KB */ 115 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 116 117 #ifdef CONFIG_CMD_KGDB 118 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 119 #else 120 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 121 #endif 122 123 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 124 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 125 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 126 #define CONFIG_SYS_LOAD_ADDR 0x00010000 127 128 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 129 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 130 131 #define CONFIG_SYS_MBAR 0xF0000000 132 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 133 #define CONFIG_SYS_INTSRAMSZ 0x8000 134 135 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 136 137 /* 138 * Low Level Configuration Settings 139 * (address mappings, register initial values, etc.) 140 * You should know what you are doing if you make changes here. 141 */ 142 /*----------------------------------------------------------------------- 143 * Definitions for initial stack pointer and data area (in DPRAM) 144 */ 145 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 146 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 147 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 148 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 149 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 150 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 151 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 152 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 153 154 /*----------------------------------------------------------------------- 155 * Start addresses for the final memory configuration 156 * (Set up by the startup code) 157 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 158 */ 159 #define CONFIG_SYS_SDRAM_BASE 0x00000000 160 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 161 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 162 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 163 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 164 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 165 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 166 #ifdef CONFIG_SYS_DRAMSZ1 167 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 168 #else 169 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 170 #endif 171 172 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 173 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 174 175 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 176 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 177 178 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 179 180 /* Reserve 256 kB for malloc() */ 181 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 182 /* 183 * For booting Linux, the board info and command line data 184 * have to be in the first 8 MB of memory, since this is 185 * the maximum mapped by the Linux kernel during initialization ?? 186 */ 187 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 188 189 /*----------------------------------------------------------------------- 190 * FLASH organization 191 */ 192 #define CONFIG_SYS_FLASH_CFI 193 #ifdef CONFIG_SYS_FLASH_CFI 194 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 195 # define CONFIG_FLASH_CFI_DRIVER 1 196 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 197 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 198 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 199 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 200 #ifdef CONFIG_SYS_NOR1SZ 201 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 202 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 203 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 204 #else 205 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 206 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 207 #endif 208 #endif 209 210 /* Configuration for environment 211 * Environment is not embedded in u-boot. First time runing may have env 212 * crc error warning if there is no correct environment on the flash. 213 */ 214 #define CONFIG_ENV_OFFSET 0x40000 215 #define CONFIG_ENV_SECT_SIZE 0x10000 216 217 /*----------------------------------------------------------------------- 218 * Cache Configuration 219 */ 220 #define CONFIG_SYS_CACHELINE_SIZE 16 221 222 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 223 CONFIG_SYS_INIT_RAM_SIZE - 8) 224 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 225 CONFIG_SYS_INIT_RAM_SIZE - 4) 226 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 227 CF_CACR_IDCM) 228 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 229 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 230 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 231 CF_ACR_EN | CF_ACR_SM_ALL) 232 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 233 CF_CACR_IEC | CF_CACR_ICINVA) 234 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 235 CF_CACR_DEC | CF_CACR_DDCM_P | \ 236 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 237 238 /*----------------------------------------------------------------------- 239 * Chipselect bank definitions 240 */ 241 /* 242 * CS0 - NOR Flash 1, 2, 4, or 8MB 243 * CS1 - NOR Flash 244 * CS2 - Available 245 * CS3 - Available 246 * CS4 - Available 247 * CS5 - Available 248 */ 249 #define CONFIG_SYS_CS0_BASE 0xFF800000 250 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 251 #define CONFIG_SYS_CS0_CTRL 0x00101980 252 253 #ifdef CONFIG_SYS_NOR1SZ 254 #define CONFIG_SYS_CS1_BASE 0xE0000000 255 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 256 #define CONFIG_SYS_CS1_CTRL 0x00101D80 257 #endif 258 259 #endif /* _M5485EVB_H */ 260