1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Freescale MCF5485 FireEngine board. 4 * 5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M5485EVB_H 14 #define _M5485EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21 #define CONFIG_MCFUART 22 #define CONFIG_SYS_UART_PORT (0) 23 24 #undef CONFIG_HW_WATCHDOG 25 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 26 27 #define CONFIG_SLTTMR 28 29 #define CONFIG_FSLDMAFEC 30 #ifdef CONFIG_FSLDMAFEC 31 # define CONFIG_MII_INIT 1 32 # define CONFIG_HAS_ETH1 33 34 # define CONFIG_SYS_DMA_USE_INTSRAM 1 35 # define CONFIG_SYS_DISCOVER_PHY 36 # define CONFIG_SYS_RX_ETH_BUFFER 32 37 # define CONFIG_SYS_TX_ETH_BUFFER 48 38 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 39 40 # define CONFIG_SYS_FEC0_PINMUX 0 41 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 42 # define CONFIG_SYS_FEC1_PINMUX 0 43 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 44 45 # define MCFFEC_TOUT_LOOP 50000 46 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 47 # ifndef CONFIG_SYS_DISCOVER_PHY 48 # define FECDUPLEX FULL 49 # define FECSPEED _100BASET 50 # else 51 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 52 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 53 # endif 54 # endif /* CONFIG_SYS_DISCOVER_PHY */ 55 56 # define CONFIG_IPADDR 192.162.1.2 57 # define CONFIG_NETMASK 255.255.255.0 58 # define CONFIG_SERVERIP 192.162.1.1 59 # define CONFIG_GATEWAYIP 192.162.1.1 60 61 #endif 62 63 #ifdef CONFIG_CMD_USB 64 # define CONFIG_USB_OHCI_NEW 65 /*# define CONFIG_PCI_OHCI*/ 66 # define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000 67 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 68 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 69 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 70 #endif 71 72 /* I2C */ 73 #define CONFIG_SYS_I2C 74 #define CONFIG_SYS_I2C_FSL 75 #define CONFIG_SYS_FSL_I2C_SPEED 80000 76 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 77 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 78 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 79 80 /* PCI */ 81 #ifdef CONFIG_CMD_PCI 82 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 83 84 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 85 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 86 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 87 88 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 89 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 90 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 91 92 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 93 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 94 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 95 #endif 96 97 #define CONFIG_UDP_CHECKSUM 98 99 #define CONFIG_HOSTNAME "M548xEVB" 100 #define CONFIG_EXTRA_ENV_SETTINGS \ 101 "netdev=eth0\0" \ 102 "loadaddr=10000\0" \ 103 "u-boot=u-boot.bin\0" \ 104 "load=tftp ${loadaddr) ${u-boot}\0" \ 105 "upd=run load; run prog\0" \ 106 "prog=prot off bank 1;" \ 107 "era ff800000 ff83ffff;" \ 108 "cp.b ${loadaddr} ff800000 ${filesize};"\ 109 "save\0" \ 110 "" 111 112 #define CONFIG_PRAM 512 /* 512 KB */ 113 114 #define CONFIG_SYS_LOAD_ADDR 0x00010000 115 116 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 117 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 118 119 #define CONFIG_SYS_MBAR 0xF0000000 120 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 121 #define CONFIG_SYS_INTSRAMSZ 0x8000 122 123 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 124 125 /* 126 * Low Level Configuration Settings 127 * (address mappings, register initial values, etc.) 128 * You should know what you are doing if you make changes here. 129 */ 130 /*----------------------------------------------------------------------- 131 * Definitions for initial stack pointer and data area (in DPRAM) 132 */ 133 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 134 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 135 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 136 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 137 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 138 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 139 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 140 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 141 142 /*----------------------------------------------------------------------- 143 * Start addresses for the final memory configuration 144 * (Set up by the startup code) 145 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 146 */ 147 #define CONFIG_SYS_SDRAM_BASE 0x00000000 148 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 149 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 150 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 151 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 152 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 153 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 154 #ifdef CONFIG_SYS_DRAMSZ1 155 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 156 #else 157 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 158 #endif 159 160 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 161 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 162 163 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 164 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 165 166 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 167 168 /* Reserve 256 kB for malloc() */ 169 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 170 /* 171 * For booting Linux, the board info and command line data 172 * have to be in the first 8 MB of memory, since this is 173 * the maximum mapped by the Linux kernel during initialization ?? 174 */ 175 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 176 177 /*----------------------------------------------------------------------- 178 * FLASH organization 179 */ 180 #ifdef CONFIG_SYS_FLASH_CFI 181 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 182 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 183 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 184 #ifdef CONFIG_SYS_NOR1SZ 185 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 186 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 187 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 188 #else 189 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 190 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 191 #endif 192 #endif 193 194 /* Configuration for environment 195 * Environment is not embedded in u-boot. First time runing may have env 196 * crc error warning if there is no correct environment on the flash. 197 */ 198 #define CONFIG_ENV_OFFSET 0x40000 199 #define CONFIG_ENV_SECT_SIZE 0x10000 200 201 /*----------------------------------------------------------------------- 202 * Cache Configuration 203 */ 204 #define CONFIG_SYS_CACHELINE_SIZE 16 205 206 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 207 CONFIG_SYS_INIT_RAM_SIZE - 8) 208 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 209 CONFIG_SYS_INIT_RAM_SIZE - 4) 210 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 211 CF_CACR_IDCM) 212 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 213 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 214 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 215 CF_ACR_EN | CF_ACR_SM_ALL) 216 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 217 CF_CACR_IEC | CF_CACR_ICINVA) 218 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 219 CF_CACR_DEC | CF_CACR_DDCM_P | \ 220 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 221 222 /*----------------------------------------------------------------------- 223 * Chipselect bank definitions 224 */ 225 /* 226 * CS0 - NOR Flash 1, 2, 4, or 8MB 227 * CS1 - NOR Flash 228 * CS2 - Available 229 * CS3 - Available 230 * CS4 - Available 231 * CS5 - Available 232 */ 233 #define CONFIG_SYS_CS0_BASE 0xFF800000 234 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 235 #define CONFIG_SYS_CS0_CTRL 0x00101980 236 237 #ifdef CONFIG_SYS_NOR1SZ 238 #define CONFIG_SYS_CS1_BASE 0xE0000000 239 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 240 #define CONFIG_SYS_CS1_CTRL 0x00101D80 241 #endif 242 243 #endif /* _M5485EVB_H */ 244