1 /* 2 * Configuation settings for the Freescale MCF5475 board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5475EVB_H 15 #define _M5475EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_MCF547x_8x /* define processor family */ 22 #define CONFIG_M547x /* define processor type */ 23 #define CONFIG_M5475 /* define processor type */ 24 25 #define CONFIG_MCFUART 26 #define CONFIG_SYS_UART_PORT (0) 27 #define CONFIG_BAUDRATE 115200 28 29 #define CONFIG_HW_WATCHDOG 30 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 31 32 /* Command line configuration */ 33 #include <config_cmd_default.h> 34 35 #define CONFIG_CMD_CACHE 36 #undef CONFIG_CMD_DATE 37 #define CONFIG_CMD_ELF 38 #define CONFIG_CMD_FLASH 39 #define CONFIG_CMD_I2C 40 #define CONFIG_CMD_MEMORY 41 #define CONFIG_CMD_MISC 42 #define CONFIG_CMD_MII 43 #define CONFIG_CMD_NET 44 #define CONFIG_CMD_PCI 45 #define CONFIG_CMD_PING 46 #define CONFIG_CMD_REGINFO 47 #define CONFIG_CMD_USB 48 49 #define CONFIG_SLTTMR 50 51 #define CONFIG_FSLDMAFEC 52 #ifdef CONFIG_FSLDMAFEC 53 # define CONFIG_MII 1 54 # define CONFIG_MII_INIT 1 55 # define CONFIG_HAS_ETH1 56 57 # define CONFIG_SYS_DMA_USE_INTSRAM 1 58 # define CONFIG_SYS_DISCOVER_PHY 59 # define CONFIG_SYS_RX_ETH_BUFFER 32 60 # define CONFIG_SYS_TX_ETH_BUFFER 48 61 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 62 63 # define CONFIG_SYS_FEC0_PINMUX 0 64 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 65 # define CONFIG_SYS_FEC1_PINMUX 0 66 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 67 68 # define MCFFEC_TOUT_LOOP 50000 69 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 70 # ifndef CONFIG_SYS_DISCOVER_PHY 71 # define FECDUPLEX FULL 72 # define FECSPEED _100BASET 73 # else 74 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 75 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 76 # endif 77 # endif /* CONFIG_SYS_DISCOVER_PHY */ 78 79 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 80 # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 81 # define CONFIG_IPADDR 192.162.1.2 82 # define CONFIG_NETMASK 255.255.255.0 83 # define CONFIG_SERVERIP 192.162.1.1 84 # define CONFIG_GATEWAYIP 192.162.1.1 85 # define CONFIG_OVERWRITE_ETHADDR_ONCE 86 87 #endif 88 89 #ifdef CONFIG_CMD_USB 90 # define CONFIG_USB_OHCI_NEW 91 # define CONFIG_USB_STORAGE 92 93 # ifndef CONFIG_CMD_PCI 94 # define CONFIG_CMD_PCI 95 # endif 96 # define CONFIG_PCI_OHCI 97 # define CONFIG_DOS_PARTITION 98 99 # undef CONFIG_SYS_USB_OHCI_BOARD_INIT 100 # undef CONFIG_SYS_USB_OHCI_CPU_INIT 101 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 102 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 103 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 104 #endif 105 106 /* I2C */ 107 #define CONFIG_SYS_I2C 108 #define CONFIG_SYS_I2C_FSL 109 #define CONFIG_SYS_FSL_I2C_SPEED 80000 110 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 111 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 112 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 113 114 /* PCI */ 115 #ifdef CONFIG_CMD_PCI 116 #define CONFIG_PCI 1 117 #define CONFIG_PCI_PNP 1 118 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 119 120 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 121 122 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 123 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 124 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 125 126 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 127 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 128 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 129 130 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 131 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 132 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 133 #endif 134 135 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 136 #define CONFIG_UDP_CHECKSUM 137 138 #ifdef CONFIG_MCFFEC 139 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 140 # define CONFIG_IPADDR 192.162.1.2 141 # define CONFIG_NETMASK 255.255.255.0 142 # define CONFIG_SERVERIP 192.162.1.1 143 # define CONFIG_GATEWAYIP 192.162.1.1 144 # define CONFIG_OVERWRITE_ETHADDR_ONCE 145 #endif /* FEC_ENET */ 146 147 #define CONFIG_HOSTNAME M547xEVB 148 #define CONFIG_EXTRA_ENV_SETTINGS \ 149 "netdev=eth0\0" \ 150 "loadaddr=10000\0" \ 151 "u-boot=u-boot.bin\0" \ 152 "load=tftp ${loadaddr) ${u-boot}\0" \ 153 "upd=run load; run prog\0" \ 154 "prog=prot off bank 1;" \ 155 "era ff800000 ff83ffff;" \ 156 "cp.b ${loadaddr} ff800000 ${filesize};"\ 157 "save\0" \ 158 "" 159 160 #define CONFIG_PRAM 512 /* 512 KB */ 161 #define CONFIG_SYS_PROMPT "-> " 162 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 163 164 #ifdef CONFIG_CMD_KGDB 165 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 166 #else 167 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 168 #endif 169 170 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 171 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 172 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 173 #define CONFIG_SYS_LOAD_ADDR 0x00010000 174 175 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 176 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 177 178 #define CONFIG_SYS_MBAR 0xF0000000 179 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 180 #define CONFIG_SYS_INTSRAMSZ 0x8000 181 182 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 183 184 /* 185 * Low Level Configuration Settings 186 * (address mappings, register initial values, etc.) 187 * You should know what you are doing if you make changes here. 188 */ 189 /*----------------------------------------------------------------------- 190 * Definitions for initial stack pointer and data area (in DPRAM) 191 */ 192 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 193 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 194 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 195 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 196 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 197 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 198 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 199 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 200 201 /*----------------------------------------------------------------------- 202 * Start addresses for the final memory configuration 203 * (Set up by the startup code) 204 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 205 */ 206 #define CONFIG_SYS_SDRAM_BASE 0x00000000 207 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 208 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 209 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 210 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 211 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 212 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 213 #ifdef CONFIG_SYS_DRAMSZ1 214 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 215 #else 216 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 217 #endif 218 219 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 220 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 221 222 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 223 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 224 225 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 226 227 /* Reserve 256 kB for malloc() */ 228 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 229 /* 230 * For booting Linux, the board info and command line data 231 * have to be in the first 8 MB of memory, since this is 232 * the maximum mapped by the Linux kernel during initialization ?? 233 */ 234 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 235 236 /*----------------------------------------------------------------------- 237 * FLASH organization 238 */ 239 #define CONFIG_SYS_FLASH_CFI 240 #ifdef CONFIG_SYS_FLASH_CFI 241 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 242 # define CONFIG_FLASH_CFI_DRIVER 1 243 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 244 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 245 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 246 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 247 #ifdef CONFIG_SYS_NOR1SZ 248 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 249 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 250 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 251 #else 252 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 253 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 254 #endif 255 #endif 256 257 /* Configuration for environment 258 * Environment is not embedded in u-boot but at offset 0x40000 on the flash. 259 * First time runing may have env crc error warning if there is 260 * no correct environment on the flash. 261 */ 262 #define CONFIG_ENV_OFFSET 0x40000 263 #define CONFIG_ENV_SECT_SIZE 0x10000 264 #define CONFIG_ENV_IS_IN_FLASH 1 265 266 /*----------------------------------------------------------------------- 267 * Cache Configuration 268 */ 269 #define CONFIG_SYS_CACHELINE_SIZE 16 270 271 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 272 CONFIG_SYS_INIT_RAM_SIZE - 8) 273 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 274 CONFIG_SYS_INIT_RAM_SIZE - 4) 275 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 276 CF_CACR_IDCM) 277 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 278 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 279 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 280 CF_ACR_EN | CF_ACR_SM_ALL) 281 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 282 CF_CACR_IEC | CF_CACR_ICINVA) 283 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 284 CF_CACR_DEC | CF_CACR_DDCM_P | \ 285 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 286 287 /*----------------------------------------------------------------------- 288 * Chipselect bank definitions 289 */ 290 /* 291 * CS0 - NOR Flash 1, 2, 4, or 8MB 292 * CS1 - NOR Flash 293 * CS2 - Available 294 * CS3 - Available 295 * CS4 - Available 296 * CS5 - Available 297 */ 298 #define CONFIG_SYS_CS0_BASE 0xFF800000 299 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 300 #define CONFIG_SYS_CS0_CTRL 0x00101980 301 302 #ifdef CONFIG_SYS_NOR1SZ 303 #define CONFIG_SYS_CS1_BASE 0xE0000000 304 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 305 #define CONFIG_SYS_CS1_CTRL 0x00101D80 306 #endif 307 308 #endif /* _M5475EVB_H */ 309