1 /* 2 * Configuation settings for the Freescale MCF5475 board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5475EVB_H 15 #define _M5475EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_DISPLAY_BOARDINFO 23 24 #define CONFIG_MCFUART 25 #define CONFIG_SYS_UART_PORT (0) 26 #define CONFIG_BAUDRATE 115200 27 28 #undef CONFIG_HW_WATCHDOG 29 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 30 31 /* Command line configuration */ 32 #include <config_cmd_default.h> 33 34 #define CONFIG_CMD_CACHE 35 #undef CONFIG_CMD_DATE 36 #define CONFIG_CMD_ELF 37 #define CONFIG_CMD_FLASH 38 #define CONFIG_CMD_I2C 39 #define CONFIG_CMD_MEMORY 40 #define CONFIG_CMD_MISC 41 #define CONFIG_CMD_MII 42 #define CONFIG_CMD_NET 43 #define CONFIG_CMD_PCI 44 #define CONFIG_CMD_PING 45 #define CONFIG_CMD_REGINFO 46 #define CONFIG_CMD_USB 47 48 #define CONFIG_SLTTMR 49 50 #define CONFIG_FSLDMAFEC 51 #ifdef CONFIG_FSLDMAFEC 52 # define CONFIG_MII 1 53 # define CONFIG_MII_INIT 1 54 # define CONFIG_HAS_ETH1 55 56 # define CONFIG_SYS_DMA_USE_INTSRAM 1 57 # define CONFIG_SYS_DISCOVER_PHY 58 # define CONFIG_SYS_RX_ETH_BUFFER 32 59 # define CONFIG_SYS_TX_ETH_BUFFER 48 60 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 61 62 # define CONFIG_SYS_FEC0_PINMUX 0 63 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 64 # define CONFIG_SYS_FEC1_PINMUX 0 65 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 66 67 # define MCFFEC_TOUT_LOOP 50000 68 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 69 # ifndef CONFIG_SYS_DISCOVER_PHY 70 # define FECDUPLEX FULL 71 # define FECSPEED _100BASET 72 # else 73 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 74 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 75 # endif 76 # endif /* CONFIG_SYS_DISCOVER_PHY */ 77 78 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 79 # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 80 # define CONFIG_IPADDR 192.162.1.2 81 # define CONFIG_NETMASK 255.255.255.0 82 # define CONFIG_SERVERIP 192.162.1.1 83 # define CONFIG_GATEWAYIP 192.162.1.1 84 # define CONFIG_OVERWRITE_ETHADDR_ONCE 85 86 #endif 87 88 #ifdef CONFIG_CMD_USB 89 # define CONFIG_USB_OHCI_NEW 90 # define CONFIG_USB_STORAGE 91 92 # ifndef CONFIG_CMD_PCI 93 # define CONFIG_CMD_PCI 94 # endif 95 # define CONFIG_PCI_OHCI 96 # define CONFIG_DOS_PARTITION 97 98 # undef CONFIG_SYS_USB_OHCI_BOARD_INIT 99 # undef CONFIG_SYS_USB_OHCI_CPU_INIT 100 # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 101 # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 102 # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 103 #endif 104 105 /* I2C */ 106 #define CONFIG_SYS_I2C 107 #define CONFIG_SYS_I2C_FSL 108 #define CONFIG_SYS_FSL_I2C_SPEED 80000 109 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 110 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 111 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 112 113 /* PCI */ 114 #ifdef CONFIG_CMD_PCI 115 #define CONFIG_PCI 1 116 #define CONFIG_PCI_PNP 1 117 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 118 119 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 120 121 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 122 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 123 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 124 125 #define CONFIG_SYS_PCI_IO_BUS 0x71000000 126 #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 127 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 128 129 #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 130 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 131 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 132 #endif 133 134 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 135 #define CONFIG_UDP_CHECKSUM 136 137 #ifdef CONFIG_MCFFEC 138 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 139 # define CONFIG_IPADDR 192.162.1.2 140 # define CONFIG_NETMASK 255.255.255.0 141 # define CONFIG_SERVERIP 192.162.1.1 142 # define CONFIG_GATEWAYIP 192.162.1.1 143 # define CONFIG_OVERWRITE_ETHADDR_ONCE 144 #endif /* FEC_ENET */ 145 146 #define CONFIG_HOSTNAME M547xEVB 147 #define CONFIG_EXTRA_ENV_SETTINGS \ 148 "netdev=eth0\0" \ 149 "loadaddr=10000\0" \ 150 "u-boot=u-boot.bin\0" \ 151 "load=tftp ${loadaddr) ${u-boot}\0" \ 152 "upd=run load; run prog\0" \ 153 "prog=prot off bank 1;" \ 154 "era ff800000 ff83ffff;" \ 155 "cp.b ${loadaddr} ff800000 ${filesize};"\ 156 "save\0" \ 157 "" 158 159 #define CONFIG_PRAM 512 /* 512 KB */ 160 #define CONFIG_SYS_PROMPT "-> " 161 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 162 163 #ifdef CONFIG_CMD_KGDB 164 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 165 #else 166 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 167 #endif 168 169 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 170 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 171 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 172 #define CONFIG_SYS_LOAD_ADDR 0x00010000 173 174 #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 175 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 176 177 #define CONFIG_SYS_MBAR 0xF0000000 178 #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 179 #define CONFIG_SYS_INTSRAMSZ 0x8000 180 181 /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 182 183 /* 184 * Low Level Configuration Settings 185 * (address mappings, register initial values, etc.) 186 * You should know what you are doing if you make changes here. 187 */ 188 /*----------------------------------------------------------------------- 189 * Definitions for initial stack pointer and data area (in DPRAM) 190 */ 191 #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 192 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 193 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 194 #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 195 #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 196 #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 197 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 198 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 199 200 /*----------------------------------------------------------------------- 201 * Start addresses for the final memory configuration 202 * (Set up by the startup code) 203 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 204 */ 205 #define CONFIG_SYS_SDRAM_BASE 0x00000000 206 #define CONFIG_SYS_SDRAM_CFG1 0x73711630 207 #define CONFIG_SYS_SDRAM_CFG2 0x46770000 208 #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 209 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 210 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 211 #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 212 #ifdef CONFIG_SYS_DRAMSZ1 213 # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 214 #else 215 # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 216 #endif 217 218 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 219 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 220 221 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 222 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 223 224 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 225 226 /* Reserve 256 kB for malloc() */ 227 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 228 /* 229 * For booting Linux, the board info and command line data 230 * have to be in the first 8 MB of memory, since this is 231 * the maximum mapped by the Linux kernel during initialization ?? 232 */ 233 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 234 235 /*----------------------------------------------------------------------- 236 * FLASH organization 237 */ 238 #define CONFIG_SYS_FLASH_CFI 239 #ifdef CONFIG_SYS_FLASH_CFI 240 # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 241 # define CONFIG_FLASH_CFI_DRIVER 1 242 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 243 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 244 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 245 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 246 #ifdef CONFIG_SYS_NOR1SZ 247 # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 248 # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 249 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 250 #else 251 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 252 # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 253 #endif 254 #endif 255 256 /* Configuration for environment 257 * Environment is not embedded in u-boot but at offset 0x40000 on the flash. 258 * First time runing may have env crc error warning if there is 259 * no correct environment on the flash. 260 */ 261 #define CONFIG_ENV_OFFSET 0x40000 262 #define CONFIG_ENV_SECT_SIZE 0x10000 263 #define CONFIG_ENV_IS_IN_FLASH 1 264 265 /*----------------------------------------------------------------------- 266 * Cache Configuration 267 */ 268 #define CONFIG_SYS_CACHELINE_SIZE 16 269 270 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 271 CONFIG_SYS_INIT_RAM_SIZE - 8) 272 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 273 CONFIG_SYS_INIT_RAM_SIZE - 4) 274 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 275 CF_CACR_IDCM) 276 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 277 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 278 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 279 CF_ACR_EN | CF_ACR_SM_ALL) 280 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 281 CF_CACR_IEC | CF_CACR_ICINVA) 282 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 283 CF_CACR_DEC | CF_CACR_DDCM_P | \ 284 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 285 286 /*----------------------------------------------------------------------- 287 * Chipselect bank definitions 288 */ 289 /* 290 * CS0 - NOR Flash 1, 2, 4, or 8MB 291 * CS1 - NOR Flash 292 * CS2 - Available 293 * CS3 - Available 294 * CS4 - Available 295 * CS5 - Available 296 */ 297 #define CONFIG_SYS_CS0_BASE 0xFF800000 298 #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 299 #define CONFIG_SYS_CS0_CTRL 0x00101980 300 301 #ifdef CONFIG_SYS_NOR1SZ 302 #define CONFIG_SYS_CS1_BASE 0xE0000000 303 #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 304 #define CONFIG_SYS_CS1_CTRL 0x00101D80 305 #endif 306 307 #endif /* _M5475EVB_H */ 308